1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Texas Instruments DP83867 PHY 4 * 5 * Copyright (C) 2015 Texas Instruments Inc. 6 */ 7 8 #include <linux/ethtool.h> 9 #include <linux/kernel.h> 10 #include <linux/mii.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/phy.h> 14 #include <linux/delay.h> 15 16 #include <dt-bindings/net/ti-dp83867.h> 17 18 #define DP83867_PHY_ID 0x2000a231 19 #define DP83867_DEVADDR 0x1f 20 21 #define MII_DP83867_PHYCTRL 0x10 22 #define MII_DP83867_MICR 0x12 23 #define MII_DP83867_ISR 0x13 24 #define DP83867_CTRL 0x1f 25 #define DP83867_CFG3 0x1e 26 27 /* Extended Registers */ 28 #define DP83867_CFG4 0x0031 29 #define DP83867_RGMIICTL 0x0032 30 #define DP83867_STRAP_STS1 0x006E 31 #define DP83867_RGMIIDCTL 0x0086 32 #define DP83867_IO_MUX_CFG 0x0170 33 34 #define DP83867_SW_RESET BIT(15) 35 #define DP83867_SW_RESTART BIT(14) 36 37 /* MICR Interrupt bits */ 38 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 39 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 40 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 41 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 42 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 43 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 44 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 45 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 46 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 47 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 48 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 49 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 50 51 /* RGMIICTL bits */ 52 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 53 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 54 55 /* STRAP_STS1 bits */ 56 #define DP83867_STRAP_STS1_RESERVED BIT(11) 57 58 /* PHY CTRL bits */ 59 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 60 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) 61 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 62 63 /* RGMIIDCTL bits */ 64 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 65 66 /* IO_MUX_CFG bits */ 67 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 68 69 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 70 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 71 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 72 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) 73 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 74 75 /* CFG4 bits */ 76 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 77 78 enum { 79 DP83867_PORT_MIRROING_KEEP, 80 DP83867_PORT_MIRROING_EN, 81 DP83867_PORT_MIRROING_DIS, 82 }; 83 84 struct dp83867_private { 85 int rx_id_delay; 86 int tx_id_delay; 87 int fifo_depth; 88 int io_impedance; 89 int port_mirroring; 90 bool rxctrl_strap_quirk; 91 bool set_clk_output; 92 u32 clk_output_sel; 93 }; 94 95 static int dp83867_ack_interrupt(struct phy_device *phydev) 96 { 97 int err = phy_read(phydev, MII_DP83867_ISR); 98 99 if (err < 0) 100 return err; 101 102 return 0; 103 } 104 105 static int dp83867_config_intr(struct phy_device *phydev) 106 { 107 int micr_status; 108 109 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 110 micr_status = phy_read(phydev, MII_DP83867_MICR); 111 if (micr_status < 0) 112 return micr_status; 113 114 micr_status |= 115 (MII_DP83867_MICR_AN_ERR_INT_EN | 116 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 117 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 118 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 119 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 120 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 121 122 return phy_write(phydev, MII_DP83867_MICR, micr_status); 123 } 124 125 micr_status = 0x0; 126 return phy_write(phydev, MII_DP83867_MICR, micr_status); 127 } 128 129 static int dp83867_config_port_mirroring(struct phy_device *phydev) 130 { 131 struct dp83867_private *dp83867 = 132 (struct dp83867_private *)phydev->priv; 133 134 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 135 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 136 DP83867_CFG4_PORT_MIRROR_EN); 137 else 138 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 139 DP83867_CFG4_PORT_MIRROR_EN); 140 return 0; 141 } 142 143 #ifdef CONFIG_OF_MDIO 144 static int dp83867_of_init(struct phy_device *phydev) 145 { 146 struct dp83867_private *dp83867 = phydev->priv; 147 struct device *dev = &phydev->mdio.dev; 148 struct device_node *of_node = dev->of_node; 149 int ret; 150 151 if (!of_node) 152 return -ENODEV; 153 154 dp83867->io_impedance = -EINVAL; 155 156 /* Optional configuration */ 157 ret = of_property_read_u32(of_node, "ti,clk-output-sel", 158 &dp83867->clk_output_sel); 159 /* If not set, keep default */ 160 if (!ret) { 161 dp83867->set_clk_output = true; 162 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or 163 * DP83867_CLK_O_SEL_OFF. 164 */ 165 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && 166 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { 167 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", 168 dp83867->clk_output_sel); 169 return -EINVAL; 170 } 171 } 172 173 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 174 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 175 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 176 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 177 178 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, 179 "ti,dp83867-rxctrl-strap-quirk"); 180 181 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 182 &dp83867->rx_id_delay); 183 if (ret && 184 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 185 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) 186 return ret; 187 188 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 189 &dp83867->tx_id_delay); 190 if (ret && 191 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 192 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) 193 return ret; 194 195 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 196 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 197 198 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 199 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 200 201 return of_property_read_u32(of_node, "ti,fifo-depth", 202 &dp83867->fifo_depth); 203 } 204 #else 205 static int dp83867_of_init(struct phy_device *phydev) 206 { 207 return 0; 208 } 209 #endif /* CONFIG_OF_MDIO */ 210 211 static int dp83867_config_init(struct phy_device *phydev) 212 { 213 struct dp83867_private *dp83867; 214 int ret, val, bs; 215 u16 delay; 216 217 if (!phydev->priv) { 218 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 219 GFP_KERNEL); 220 if (!dp83867) 221 return -ENOMEM; 222 223 phydev->priv = dp83867; 224 ret = dp83867_of_init(phydev); 225 if (ret) 226 return ret; 227 } else { 228 dp83867 = (struct dp83867_private *)phydev->priv; 229 } 230 231 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */ 232 if (dp83867->rxctrl_strap_quirk) 233 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, 234 BIT(7)); 235 236 if (phy_interface_is_rgmii(phydev)) { 237 val = phy_read(phydev, MII_DP83867_PHYCTRL); 238 if (val < 0) 239 return val; 240 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; 241 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); 242 243 /* The code below checks if "port mirroring" N/A MODE4 has been 244 * enabled during power on bootstrap. 245 * 246 * Such N/A mode enabled by mistake can put PHY IC in some 247 * internal testing mode and disable RGMII transmission. 248 * 249 * In this particular case one needs to check STRAP_STS1 250 * register's bit 11 (marked as RESERVED). 251 */ 252 253 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 254 if (bs & DP83867_STRAP_STS1_RESERVED) 255 val &= ~DP83867_PHYCR_RESERVED_MASK; 256 257 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 258 if (ret) 259 return ret; 260 } 261 262 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 263 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 264 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 265 266 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 267 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 268 269 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 270 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 271 272 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 273 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 274 275 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 276 277 delay = (dp83867->rx_id_delay | 278 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 279 280 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 281 delay); 282 283 if (dp83867->io_impedance >= 0) 284 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 285 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL, 286 dp83867->io_impedance & 287 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL); 288 } 289 290 /* Enable Interrupt output INT_OE in CFG3 register */ 291 if (phy_interrupt_is_valid(phydev)) { 292 val = phy_read(phydev, DP83867_CFG3); 293 val |= BIT(7); 294 phy_write(phydev, DP83867_CFG3, val); 295 } 296 297 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 298 dp83867_config_port_mirroring(phydev); 299 300 /* Clock output selection if muxing property is set */ 301 if (dp83867->set_clk_output) { 302 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 303 304 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { 305 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE; 306 } else { 307 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; 308 val = dp83867->clk_output_sel << 309 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT; 310 } 311 312 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, 313 mask, val); 314 } 315 316 return 0; 317 } 318 319 static int dp83867_phy_reset(struct phy_device *phydev) 320 { 321 int err; 322 323 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 324 if (err < 0) 325 return err; 326 327 usleep_range(10, 20); 328 329 return dp83867_config_init(phydev); 330 } 331 332 static struct phy_driver dp83867_driver[] = { 333 { 334 .phy_id = DP83867_PHY_ID, 335 .phy_id_mask = 0xfffffff0, 336 .name = "TI DP83867", 337 /* PHY_GBIT_FEATURES */ 338 339 .config_init = dp83867_config_init, 340 .soft_reset = dp83867_phy_reset, 341 342 /* IRQ related */ 343 .ack_interrupt = dp83867_ack_interrupt, 344 .config_intr = dp83867_config_intr, 345 346 .suspend = genphy_suspend, 347 .resume = genphy_resume, 348 }, 349 }; 350 module_phy_driver(dp83867_driver); 351 352 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 353 { DP83867_PHY_ID, 0xfffffff0 }, 354 { } 355 }; 356 357 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 358 359 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 360 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 361 MODULE_LICENSE("GPL v2"); 362