1 /* 2 * Driver for the Texas Instruments DP83867 PHY 3 * 4 * Copyright (C) 2015 Texas Instruments Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/ethtool.h> 17 #include <linux/kernel.h> 18 #include <linux/mii.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/phy.h> 22 23 #include <dt-bindings/net/ti-dp83867.h> 24 25 #define DP83867_PHY_ID 0x2000a231 26 #define DP83867_DEVADDR 0x1f 27 28 #define MII_DP83867_PHYCTRL 0x10 29 #define MII_DP83867_MICR 0x12 30 #define MII_DP83867_ISR 0x13 31 #define DP83867_CTRL 0x1f 32 #define DP83867_CFG3 0x1e 33 34 /* Extended Registers */ 35 #define DP83867_CFG4 0x0031 36 #define DP83867_RGMIICTL 0x0032 37 #define DP83867_STRAP_STS1 0x006E 38 #define DP83867_RGMIIDCTL 0x0086 39 #define DP83867_IO_MUX_CFG 0x0170 40 41 #define DP83867_SW_RESET BIT(15) 42 #define DP83867_SW_RESTART BIT(14) 43 44 /* MICR Interrupt bits */ 45 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 46 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 47 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 48 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 49 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 50 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 51 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 52 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 53 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 54 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 55 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 56 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 57 58 /* RGMIICTL bits */ 59 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 60 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 61 62 /* STRAP_STS1 bits */ 63 #define DP83867_STRAP_STS1_RESERVED BIT(11) 64 65 /* PHY CTRL bits */ 66 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 67 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) 68 #define DP83867_PHYCR_RESERVED_MASK BIT(11) 69 70 /* RGMIIDCTL bits */ 71 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 72 73 /* IO_MUX_CFG bits */ 74 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 75 76 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 77 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 78 79 /* CFG4 bits */ 80 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) 81 82 enum { 83 DP83867_PORT_MIRROING_KEEP, 84 DP83867_PORT_MIRROING_EN, 85 DP83867_PORT_MIRROING_DIS, 86 }; 87 88 struct dp83867_private { 89 int rx_id_delay; 90 int tx_id_delay; 91 int fifo_depth; 92 int io_impedance; 93 int port_mirroring; 94 }; 95 96 static int dp83867_ack_interrupt(struct phy_device *phydev) 97 { 98 int err = phy_read(phydev, MII_DP83867_ISR); 99 100 if (err < 0) 101 return err; 102 103 return 0; 104 } 105 106 static int dp83867_config_intr(struct phy_device *phydev) 107 { 108 int micr_status; 109 110 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 111 micr_status = phy_read(phydev, MII_DP83867_MICR); 112 if (micr_status < 0) 113 return micr_status; 114 115 micr_status |= 116 (MII_DP83867_MICR_AN_ERR_INT_EN | 117 MII_DP83867_MICR_SPEED_CHNG_INT_EN | 118 MII_DP83867_MICR_AUTONEG_COMP_INT_EN | 119 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN | 120 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN | 121 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN); 122 123 return phy_write(phydev, MII_DP83867_MICR, micr_status); 124 } 125 126 micr_status = 0x0; 127 return phy_write(phydev, MII_DP83867_MICR, micr_status); 128 } 129 130 static int dp83867_config_port_mirroring(struct phy_device *phydev) 131 { 132 struct dp83867_private *dp83867 = 133 (struct dp83867_private *)phydev->priv; 134 u16 val; 135 136 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4); 137 138 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) 139 val |= DP83867_CFG4_PORT_MIRROR_EN; 140 else 141 val &= ~DP83867_CFG4_PORT_MIRROR_EN; 142 143 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val); 144 145 return 0; 146 } 147 148 #ifdef CONFIG_OF_MDIO 149 static int dp83867_of_init(struct phy_device *phydev) 150 { 151 struct dp83867_private *dp83867 = phydev->priv; 152 struct device *dev = &phydev->mdio.dev; 153 struct device_node *of_node = dev->of_node; 154 int ret; 155 156 if (!of_node) 157 return -ENODEV; 158 159 dp83867->io_impedance = -EINVAL; 160 161 /* Optional configuration */ 162 if (of_property_read_bool(of_node, "ti,max-output-impedance")) 163 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; 164 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) 165 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; 166 167 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", 168 &dp83867->rx_id_delay); 169 if (ret && 170 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 171 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) 172 return ret; 173 174 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", 175 &dp83867->tx_id_delay); 176 if (ret && 177 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 178 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) 179 return ret; 180 181 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) 182 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; 183 184 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) 185 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; 186 187 return of_property_read_u32(of_node, "ti,fifo-depth", 188 &dp83867->fifo_depth); 189 } 190 #else 191 static int dp83867_of_init(struct phy_device *phydev) 192 { 193 return 0; 194 } 195 #endif /* CONFIG_OF_MDIO */ 196 197 static int dp83867_config_init(struct phy_device *phydev) 198 { 199 struct dp83867_private *dp83867; 200 int ret, val, bs; 201 u16 delay; 202 203 if (!phydev->priv) { 204 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), 205 GFP_KERNEL); 206 if (!dp83867) 207 return -ENOMEM; 208 209 phydev->priv = dp83867; 210 ret = dp83867_of_init(phydev); 211 if (ret) 212 return ret; 213 } else { 214 dp83867 = (struct dp83867_private *)phydev->priv; 215 } 216 217 if (phy_interface_is_rgmii(phydev)) { 218 val = phy_read(phydev, MII_DP83867_PHYCTRL); 219 if (val < 0) 220 return val; 221 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; 222 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); 223 224 /* The code below checks if "port mirroring" N/A MODE4 has been 225 * enabled during power on bootstrap. 226 * 227 * Such N/A mode enabled by mistake can put PHY IC in some 228 * internal testing mode and disable RGMII transmission. 229 * 230 * In this particular case one needs to check STRAP_STS1 231 * register's bit 11 (marked as RESERVED). 232 */ 233 234 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); 235 if (bs & DP83867_STRAP_STS1_RESERVED) 236 val &= ~DP83867_PHYCR_RESERVED_MASK; 237 238 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); 239 if (ret) 240 return ret; 241 } 242 243 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 244 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 245 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); 246 247 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 248 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN); 249 250 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 251 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 252 253 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 254 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 255 256 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); 257 258 delay = (dp83867->rx_id_delay | 259 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 260 261 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, 262 delay); 263 264 if (dp83867->io_impedance >= 0) { 265 val = phy_read_mmd(phydev, DP83867_DEVADDR, 266 DP83867_IO_MUX_CFG); 267 268 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; 269 val |= dp83867->io_impedance & 270 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL; 271 272 phy_write_mmd(phydev, DP83867_DEVADDR, 273 DP83867_IO_MUX_CFG, val); 274 } 275 } 276 277 /* Enable Interrupt output INT_OE in CFG3 register */ 278 if (phy_interrupt_is_valid(phydev)) { 279 val = phy_read(phydev, DP83867_CFG3); 280 val |= BIT(7); 281 phy_write(phydev, DP83867_CFG3, val); 282 } 283 284 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) 285 dp83867_config_port_mirroring(phydev); 286 287 return 0; 288 } 289 290 static int dp83867_phy_reset(struct phy_device *phydev) 291 { 292 int err; 293 294 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); 295 if (err < 0) 296 return err; 297 298 return dp83867_config_init(phydev); 299 } 300 301 static struct phy_driver dp83867_driver[] = { 302 { 303 .phy_id = DP83867_PHY_ID, 304 .phy_id_mask = 0xfffffff0, 305 .name = "TI DP83867", 306 .features = PHY_GBIT_FEATURES, 307 .flags = PHY_HAS_INTERRUPT, 308 309 .config_init = dp83867_config_init, 310 .soft_reset = dp83867_phy_reset, 311 312 /* IRQ related */ 313 .ack_interrupt = dp83867_ack_interrupt, 314 .config_intr = dp83867_config_intr, 315 316 .config_aneg = genphy_config_aneg, 317 .read_status = genphy_read_status, 318 .suspend = genphy_suspend, 319 .resume = genphy_resume, 320 }, 321 }; 322 module_phy_driver(dp83867_driver); 323 324 static struct mdio_device_id __maybe_unused dp83867_tbl[] = { 325 { DP83867_PHY_ID, 0xfffffff0 }, 326 { } 327 }; 328 329 MODULE_DEVICE_TABLE(mdio, dp83867_tbl); 330 331 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver"); 332 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); 333 MODULE_LICENSE("GPL"); 334