1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/bitfield.h> 17 #include <linux/regulator/of_regulator.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/of.h> 21 #include <linux/phylink.h> 22 #include <linux/sfp.h> 23 #include <dt-bindings/net/qca-ar803x.h> 24 25 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 26 #define AT803X_SFC_ASSERT_CRS BIT(11) 27 #define AT803X_SFC_FORCE_LINK BIT(10) 28 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 29 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 30 #define AT803X_SFC_MANUAL_MDIX 0x1 31 #define AT803X_SFC_MANUAL_MDI 0x0 32 #define AT803X_SFC_SQE_TEST BIT(2) 33 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 34 #define AT803X_SFC_DISABLE_JABBER BIT(0) 35 36 #define AT803X_SPECIFIC_STATUS 0x11 37 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 38 #define AT803X_SS_SPEED_1000 2 39 #define AT803X_SS_SPEED_100 1 40 #define AT803X_SS_SPEED_10 0 41 #define AT803X_SS_DUPLEX BIT(13) 42 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 43 #define AT803X_SS_MDIX BIT(6) 44 45 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 46 #define QCA808X_SS_SPEED_2500 4 47 48 #define AT803X_INTR_ENABLE 0x12 49 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 50 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 51 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 52 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 53 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 54 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 55 #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 56 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 57 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 58 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 59 #define AT803X_INTR_ENABLE_WOL BIT(0) 60 61 #define AT803X_INTR_STATUS 0x13 62 63 #define AT803X_SMART_SPEED 0x14 64 #define AT803X_SMART_SPEED_ENABLE BIT(5) 65 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 66 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 67 #define AT803X_CDT 0x16 68 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 69 #define AT803X_CDT_ENABLE_TEST BIT(0) 70 #define AT803X_CDT_STATUS 0x1c 71 #define AT803X_CDT_STATUS_STAT_NORMAL 0 72 #define AT803X_CDT_STATUS_STAT_SHORT 1 73 #define AT803X_CDT_STATUS_STAT_OPEN 2 74 #define AT803X_CDT_STATUS_STAT_FAIL 3 75 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 76 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 77 #define AT803X_LED_CONTROL 0x18 78 79 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 80 #define AT803X_WOL_EN BIT(5) 81 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 82 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 83 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 84 #define AT803X_REG_CHIP_CONFIG 0x1f 85 #define AT803X_BT_BX_REG_SEL 0x8000 86 87 #define AT803X_DEBUG_ADDR 0x1D 88 #define AT803X_DEBUG_DATA 0x1E 89 90 #define AT803X_MODE_CFG_MASK 0x0F 91 #define AT803X_MODE_CFG_BASET_RGMII 0x00 92 #define AT803X_MODE_CFG_BASET_SGMII 0x01 93 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 94 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 95 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 96 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 97 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 98 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 99 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 100 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 101 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 102 103 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 104 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 105 106 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 107 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 108 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 109 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 110 111 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 112 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 113 114 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 115 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 116 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 117 #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) 118 119 #define AT803X_DEBUG_REG_3C 0x3C 120 121 #define AT803X_DEBUG_REG_GREEN 0x3D 122 #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 123 124 #define AT803X_DEBUG_REG_1F 0x1F 125 #define AT803X_DEBUG_PLL_ON BIT(2) 126 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 127 128 #define MDIO_AZ_DEBUG 0x800D 129 130 /* AT803x supports either the XTAL input pad, an internal PLL or the 131 * DSP as clock reference for the clock output pad. The XTAL reference 132 * is only used for 25 MHz output, all other frequencies need the PLL. 133 * The DSP as a clock reference is used in synchronous ethernet 134 * applications. 135 * 136 * By default the PLL is only enabled if there is a link. Otherwise 137 * the PHY will go into low power state and disabled the PLL. You can 138 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 139 * enabled. 140 */ 141 #define AT803X_MMD7_CLK25M 0x8016 142 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 143 #define AT803X_CLK_OUT_25MHZ_XTAL 0 144 #define AT803X_CLK_OUT_25MHZ_DSP 1 145 #define AT803X_CLK_OUT_50MHZ_PLL 2 146 #define AT803X_CLK_OUT_50MHZ_DSP 3 147 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 148 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 149 #define AT803X_CLK_OUT_125MHZ_PLL 6 150 #define AT803X_CLK_OUT_125MHZ_DSP 7 151 152 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 153 * but doesn't support choosing between XTAL/PLL and DSP. 154 */ 155 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 156 157 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 158 #define AT803X_CLK_OUT_STRENGTH_FULL 0 159 #define AT803X_CLK_OUT_STRENGTH_HALF 1 160 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 161 162 #define AT803X_DEFAULT_DOWNSHIFT 5 163 #define AT803X_MIN_DOWNSHIFT 2 164 #define AT803X_MAX_DOWNSHIFT 9 165 166 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 167 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 168 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 169 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 170 171 #define ATH9331_PHY_ID 0x004dd041 172 #define ATH8030_PHY_ID 0x004dd076 173 #define ATH8031_PHY_ID 0x004dd074 174 #define ATH8032_PHY_ID 0x004dd023 175 #define ATH8035_PHY_ID 0x004dd072 176 #define AT8030_PHY_ID_MASK 0xffffffef 177 178 #define QCA8081_PHY_ID 0x004dd101 179 180 #define QCA8327_A_PHY_ID 0x004dd033 181 #define QCA8327_B_PHY_ID 0x004dd034 182 #define QCA8337_PHY_ID 0x004dd036 183 #define QCA9561_PHY_ID 0x004dd042 184 #define QCA8K_PHY_ID_MASK 0xffffffff 185 186 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 187 188 #define AT803X_PAGE_FIBER 0 189 #define AT803X_PAGE_COPPER 1 190 191 /* don't turn off internal PLL */ 192 #define AT803X_KEEP_PLL_ENABLED BIT(0) 193 #define AT803X_DISABLE_SMARTEEE BIT(1) 194 195 /* disable hibernation mode */ 196 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 197 198 /* ADC threshold */ 199 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 200 #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 201 #define QCA808X_ADC_THRESHOLD_80MV 0 202 #define QCA808X_ADC_THRESHOLD_100MV 0xf0 203 #define QCA808X_ADC_THRESHOLD_200MV 0x0f 204 #define QCA808X_ADC_THRESHOLD_300MV 0xff 205 206 /* CLD control */ 207 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 208 #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 209 #define QCA808X_8023AZ_AFE_EN 0x90 210 211 /* AZ control */ 212 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 213 #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 214 215 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 216 #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 217 218 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 219 #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 220 221 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 222 #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 223 224 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 225 #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 226 227 #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 228 #define QCA808X_TOP_OPTION1_DATA 0x0 229 230 #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 231 #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 232 #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 233 #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 234 #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 235 #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 236 #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 237 #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 238 #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 239 #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 240 #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 241 #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 242 243 /* master/slave seed config */ 244 #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 245 #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 246 #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 247 #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 248 249 /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 250 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 251 */ 252 #define QCA808X_DBG_AN_TEST 0xb 253 #define QCA808X_HIBERNATION_EN BIT(15) 254 255 #define QCA808X_CDT_ENABLE_TEST BIT(15) 256 #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 257 #define QCA808X_CDT_LENGTH_UNIT BIT(10) 258 259 #define QCA808X_MMD3_CDT_STATUS 0x8064 260 #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 261 #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 262 #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 263 #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 264 #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 265 266 #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 267 #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 268 #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 269 #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 270 #define QCA808X_CDT_STATUS_STAT_FAIL 0 271 #define QCA808X_CDT_STATUS_STAT_NORMAL 1 272 #define QCA808X_CDT_STATUS_STAT_OPEN 2 273 #define QCA808X_CDT_STATUS_STAT_SHORT 3 274 275 /* QCA808X 1G chip type */ 276 #define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d 277 #define QCA808X_PHY_CHIP_TYPE_1G BIT(0) 278 279 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 280 MODULE_AUTHOR("Matus Ujhelyi"); 281 MODULE_LICENSE("GPL"); 282 283 enum stat_access_type { 284 PHY, 285 MMD 286 }; 287 288 struct at803x_hw_stat { 289 const char *string; 290 u8 reg; 291 u32 mask; 292 enum stat_access_type access_type; 293 }; 294 295 static struct at803x_hw_stat at803x_hw_stats[] = { 296 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 297 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 298 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 299 }; 300 301 struct at803x_priv { 302 int flags; 303 u16 clk_25m_reg; 304 u16 clk_25m_mask; 305 u8 smarteee_lpi_tw_1g; 306 u8 smarteee_lpi_tw_100m; 307 bool is_fiber; 308 bool is_1000basex; 309 struct regulator_dev *vddio_rdev; 310 struct regulator_dev *vddh_rdev; 311 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 312 }; 313 314 struct at803x_context { 315 u16 bmcr; 316 u16 advertise; 317 u16 control1000; 318 u16 int_enable; 319 u16 smart_speed; 320 u16 led_control; 321 }; 322 323 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 324 { 325 int ret; 326 327 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 328 if (ret < 0) 329 return ret; 330 331 return phy_write(phydev, AT803X_DEBUG_DATA, data); 332 } 333 334 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 335 { 336 int ret; 337 338 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 339 if (ret < 0) 340 return ret; 341 342 return phy_read(phydev, AT803X_DEBUG_DATA); 343 } 344 345 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 346 u16 clear, u16 set) 347 { 348 u16 val; 349 int ret; 350 351 ret = at803x_debug_reg_read(phydev, reg); 352 if (ret < 0) 353 return ret; 354 355 val = ret & 0xffff; 356 val &= ~clear; 357 val |= set; 358 359 return phy_write(phydev, AT803X_DEBUG_DATA, val); 360 } 361 362 static int at803x_write_page(struct phy_device *phydev, int page) 363 { 364 int mask; 365 int set; 366 367 if (page == AT803X_PAGE_COPPER) { 368 set = AT803X_BT_BX_REG_SEL; 369 mask = 0; 370 } else { 371 set = 0; 372 mask = AT803X_BT_BX_REG_SEL; 373 } 374 375 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 376 } 377 378 static int at803x_read_page(struct phy_device *phydev) 379 { 380 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 381 382 if (ccr < 0) 383 return ccr; 384 385 if (ccr & AT803X_BT_BX_REG_SEL) 386 return AT803X_PAGE_COPPER; 387 388 return AT803X_PAGE_FIBER; 389 } 390 391 static int at803x_enable_rx_delay(struct phy_device *phydev) 392 { 393 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 394 AT803X_DEBUG_RX_CLK_DLY_EN); 395 } 396 397 static int at803x_enable_tx_delay(struct phy_device *phydev) 398 { 399 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 400 AT803X_DEBUG_TX_CLK_DLY_EN); 401 } 402 403 static int at803x_disable_rx_delay(struct phy_device *phydev) 404 { 405 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 406 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 407 } 408 409 static int at803x_disable_tx_delay(struct phy_device *phydev) 410 { 411 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 412 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 413 } 414 415 /* save relevant PHY registers to private copy */ 416 static void at803x_context_save(struct phy_device *phydev, 417 struct at803x_context *context) 418 { 419 context->bmcr = phy_read(phydev, MII_BMCR); 420 context->advertise = phy_read(phydev, MII_ADVERTISE); 421 context->control1000 = phy_read(phydev, MII_CTRL1000); 422 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 423 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 424 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 425 } 426 427 /* restore relevant PHY registers from private copy */ 428 static void at803x_context_restore(struct phy_device *phydev, 429 const struct at803x_context *context) 430 { 431 phy_write(phydev, MII_BMCR, context->bmcr); 432 phy_write(phydev, MII_ADVERTISE, context->advertise); 433 phy_write(phydev, MII_CTRL1000, context->control1000); 434 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 435 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 436 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 437 } 438 439 static int at803x_set_wol(struct phy_device *phydev, 440 struct ethtool_wolinfo *wol) 441 { 442 int ret, irq_enabled; 443 444 if (wol->wolopts & WAKE_MAGIC) { 445 struct net_device *ndev = phydev->attached_dev; 446 const u8 *mac; 447 unsigned int i; 448 static const unsigned int offsets[] = { 449 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 450 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 451 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 452 }; 453 454 if (!ndev) 455 return -ENODEV; 456 457 mac = (const u8 *) ndev->dev_addr; 458 459 if (!is_valid_ether_addr(mac)) 460 return -EINVAL; 461 462 for (i = 0; i < 3; i++) 463 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 464 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 465 466 /* Enable WOL function */ 467 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 468 0, AT803X_WOL_EN); 469 if (ret) 470 return ret; 471 /* Enable WOL interrupt */ 472 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 473 if (ret) 474 return ret; 475 } else { 476 /* Disable WoL function */ 477 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 478 AT803X_WOL_EN, 0); 479 if (ret) 480 return ret; 481 /* Disable WOL interrupt */ 482 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 483 if (ret) 484 return ret; 485 } 486 487 /* Clear WOL status */ 488 ret = phy_read(phydev, AT803X_INTR_STATUS); 489 if (ret < 0) 490 return ret; 491 492 /* Check if there are other interrupts except for WOL triggered when PHY is 493 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 494 * be passed up to the interrupt PIN. 495 */ 496 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 497 if (irq_enabled < 0) 498 return irq_enabled; 499 500 irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 501 if (ret & irq_enabled && !phy_polling_mode(phydev)) 502 phy_trigger_machine(phydev); 503 504 return 0; 505 } 506 507 static void at803x_get_wol(struct phy_device *phydev, 508 struct ethtool_wolinfo *wol) 509 { 510 int value; 511 512 wol->supported = WAKE_MAGIC; 513 wol->wolopts = 0; 514 515 value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 516 if (value < 0) 517 return; 518 519 if (value & AT803X_WOL_EN) 520 wol->wolopts |= WAKE_MAGIC; 521 } 522 523 static int at803x_get_sset_count(struct phy_device *phydev) 524 { 525 return ARRAY_SIZE(at803x_hw_stats); 526 } 527 528 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 529 { 530 int i; 531 532 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 533 strscpy(data + i * ETH_GSTRING_LEN, 534 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 535 } 536 } 537 538 static u64 at803x_get_stat(struct phy_device *phydev, int i) 539 { 540 struct at803x_hw_stat stat = at803x_hw_stats[i]; 541 struct at803x_priv *priv = phydev->priv; 542 int val; 543 u64 ret; 544 545 if (stat.access_type == MMD) 546 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 547 else 548 val = phy_read(phydev, stat.reg); 549 550 if (val < 0) { 551 ret = U64_MAX; 552 } else { 553 val = val & stat.mask; 554 priv->stats[i] += val; 555 ret = priv->stats[i]; 556 } 557 558 return ret; 559 } 560 561 static void at803x_get_stats(struct phy_device *phydev, 562 struct ethtool_stats *stats, u64 *data) 563 { 564 int i; 565 566 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 567 data[i] = at803x_get_stat(phydev, i); 568 } 569 570 static int at803x_suspend(struct phy_device *phydev) 571 { 572 int value; 573 int wol_enabled; 574 575 value = phy_read(phydev, AT803X_INTR_ENABLE); 576 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 577 578 if (wol_enabled) 579 value = BMCR_ISOLATE; 580 else 581 value = BMCR_PDOWN; 582 583 phy_modify(phydev, MII_BMCR, 0, value); 584 585 return 0; 586 } 587 588 static int at803x_resume(struct phy_device *phydev) 589 { 590 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 591 } 592 593 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 594 unsigned int selector) 595 { 596 struct phy_device *phydev = rdev_get_drvdata(rdev); 597 598 if (selector) 599 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 600 0, AT803X_DEBUG_RGMII_1V8); 601 else 602 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 603 AT803X_DEBUG_RGMII_1V8, 0); 604 } 605 606 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 607 { 608 struct phy_device *phydev = rdev_get_drvdata(rdev); 609 int val; 610 611 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 612 if (val < 0) 613 return val; 614 615 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 616 } 617 618 static const struct regulator_ops vddio_regulator_ops = { 619 .list_voltage = regulator_list_voltage_table, 620 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 621 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 622 }; 623 624 static const unsigned int vddio_voltage_table[] = { 625 1500000, 626 1800000, 627 }; 628 629 static const struct regulator_desc vddio_desc = { 630 .name = "vddio", 631 .of_match = of_match_ptr("vddio-regulator"), 632 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 633 .volt_table = vddio_voltage_table, 634 .ops = &vddio_regulator_ops, 635 .type = REGULATOR_VOLTAGE, 636 .owner = THIS_MODULE, 637 }; 638 639 static const struct regulator_ops vddh_regulator_ops = { 640 }; 641 642 static const struct regulator_desc vddh_desc = { 643 .name = "vddh", 644 .of_match = of_match_ptr("vddh-regulator"), 645 .n_voltages = 1, 646 .fixed_uV = 2500000, 647 .ops = &vddh_regulator_ops, 648 .type = REGULATOR_VOLTAGE, 649 .owner = THIS_MODULE, 650 }; 651 652 static int at8031_register_regulators(struct phy_device *phydev) 653 { 654 struct at803x_priv *priv = phydev->priv; 655 struct device *dev = &phydev->mdio.dev; 656 struct regulator_config config = { }; 657 658 config.dev = dev; 659 config.driver_data = phydev; 660 661 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 662 if (IS_ERR(priv->vddio_rdev)) { 663 phydev_err(phydev, "failed to register VDDIO regulator\n"); 664 return PTR_ERR(priv->vddio_rdev); 665 } 666 667 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 668 if (IS_ERR(priv->vddh_rdev)) { 669 phydev_err(phydev, "failed to register VDDH regulator\n"); 670 return PTR_ERR(priv->vddh_rdev); 671 } 672 673 return 0; 674 } 675 676 static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 677 { 678 struct phy_device *phydev = upstream; 679 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 680 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 681 DECLARE_PHY_INTERFACE_MASK(interfaces); 682 phy_interface_t iface; 683 684 linkmode_zero(phy_support); 685 phylink_set(phy_support, 1000baseX_Full); 686 phylink_set(phy_support, 1000baseT_Full); 687 phylink_set(phy_support, Autoneg); 688 phylink_set(phy_support, Pause); 689 phylink_set(phy_support, Asym_Pause); 690 691 linkmode_zero(sfp_support); 692 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); 693 /* Some modules support 10G modes as well as others we support. 694 * Mask out non-supported modes so the correct interface is picked. 695 */ 696 linkmode_and(sfp_support, phy_support, sfp_support); 697 698 if (linkmode_empty(sfp_support)) { 699 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 700 return -EINVAL; 701 } 702 703 iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 704 705 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 706 * interface for use with SFP modules. 707 * However, some copper modules detected as having a preferred SGMII 708 * interface do default to and function in 1000Base-X mode, so just 709 * print a warning and allow such modules, as they may have some chance 710 * of working. 711 */ 712 if (iface == PHY_INTERFACE_MODE_SGMII) 713 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 714 else if (iface != PHY_INTERFACE_MODE_1000BASEX) 715 return -EINVAL; 716 717 return 0; 718 } 719 720 static const struct sfp_upstream_ops at803x_sfp_ops = { 721 .attach = phy_sfp_attach, 722 .detach = phy_sfp_detach, 723 .module_insert = at803x_sfp_insert, 724 }; 725 726 static int at803x_parse_dt(struct phy_device *phydev) 727 { 728 struct device_node *node = phydev->mdio.dev.of_node; 729 struct at803x_priv *priv = phydev->priv; 730 u32 freq, strength, tw; 731 unsigned int sel; 732 int ret; 733 734 if (!IS_ENABLED(CONFIG_OF_MDIO)) 735 return 0; 736 737 if (of_property_read_bool(node, "qca,disable-smarteee")) 738 priv->flags |= AT803X_DISABLE_SMARTEEE; 739 740 if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 741 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 742 743 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 744 if (!tw || tw > 255) { 745 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 746 return -EINVAL; 747 } 748 priv->smarteee_lpi_tw_1g = tw; 749 } 750 751 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 752 if (!tw || tw > 255) { 753 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 754 return -EINVAL; 755 } 756 priv->smarteee_lpi_tw_100m = tw; 757 } 758 759 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 760 if (!ret) { 761 switch (freq) { 762 case 25000000: 763 sel = AT803X_CLK_OUT_25MHZ_XTAL; 764 break; 765 case 50000000: 766 sel = AT803X_CLK_OUT_50MHZ_PLL; 767 break; 768 case 62500000: 769 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 770 break; 771 case 125000000: 772 sel = AT803X_CLK_OUT_125MHZ_PLL; 773 break; 774 default: 775 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 776 return -EINVAL; 777 } 778 779 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 780 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 781 782 /* Fixup for the AR8030/AR8035. This chip has another mask and 783 * doesn't support the DSP reference. Eg. the lowest bit of the 784 * mask. The upper two bits select the same frequencies. Mask 785 * the lowest bit here. 786 * 787 * Warning: 788 * There was no datasheet for the AR8030 available so this is 789 * just a guess. But the AR8035 is listed as pin compatible 790 * to the AR8030 so there might be a good chance it works on 791 * the AR8030 too. 792 */ 793 if (phydev->drv->phy_id == ATH8030_PHY_ID || 794 phydev->drv->phy_id == ATH8035_PHY_ID) { 795 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 796 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 797 } 798 } 799 800 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 801 if (!ret) { 802 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 803 switch (strength) { 804 case AR803X_STRENGTH_FULL: 805 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 806 break; 807 case AR803X_STRENGTH_HALF: 808 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 809 break; 810 case AR803X_STRENGTH_QUARTER: 811 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 812 break; 813 default: 814 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 815 return -EINVAL; 816 } 817 } 818 819 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 820 * options. 821 */ 822 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 823 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 824 priv->flags |= AT803X_KEEP_PLL_ENABLED; 825 826 ret = at8031_register_regulators(phydev); 827 if (ret < 0) 828 return ret; 829 830 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, 831 "vddio"); 832 if (ret) { 833 phydev_err(phydev, "failed to get VDDIO regulator\n"); 834 return ret; 835 } 836 837 /* Only AR8031/8033 support 1000Base-X for SFP modules */ 838 ret = phy_sfp_probe(phydev, &at803x_sfp_ops); 839 if (ret < 0) 840 return ret; 841 } 842 843 return 0; 844 } 845 846 static int at803x_probe(struct phy_device *phydev) 847 { 848 struct device *dev = &phydev->mdio.dev; 849 struct at803x_priv *priv; 850 int ret; 851 852 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 853 if (!priv) 854 return -ENOMEM; 855 856 phydev->priv = priv; 857 858 ret = at803x_parse_dt(phydev); 859 if (ret) 860 return ret; 861 862 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 863 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 864 int mode_cfg; 865 struct ethtool_wolinfo wol = { 866 .wolopts = 0, 867 }; 868 869 if (ccr < 0) 870 return ccr; 871 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 872 873 switch (mode_cfg) { 874 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 875 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 876 priv->is_1000basex = true; 877 fallthrough; 878 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 879 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 880 priv->is_fiber = true; 881 break; 882 } 883 884 /* Disable WOL by default */ 885 ret = at803x_set_wol(phydev, &wol); 886 if (ret < 0) { 887 phydev_err(phydev, "failed to disable WOL on probe: %d\n", ret); 888 return ret; 889 } 890 } 891 892 return 0; 893 } 894 895 static int at803x_get_features(struct phy_device *phydev) 896 { 897 struct at803x_priv *priv = phydev->priv; 898 int err; 899 900 err = genphy_read_abilities(phydev); 901 if (err) 902 return err; 903 904 if (phydev->drv->phy_id != ATH8031_PHY_ID) 905 return 0; 906 907 /* AR8031/AR8033 have different status registers 908 * for copper and fiber operation. However, the 909 * extended status register is the same for both 910 * operation modes. 911 * 912 * As a result of that, ESTATUS_1000_XFULL is set 913 * to 1 even when operating in copper TP mode. 914 * 915 * Remove this mode from the supported link modes 916 * when not operating in 1000BaseX mode. 917 */ 918 if (!priv->is_1000basex) 919 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 920 phydev->supported); 921 922 return 0; 923 } 924 925 static int at803x_smarteee_config(struct phy_device *phydev) 926 { 927 struct at803x_priv *priv = phydev->priv; 928 u16 mask = 0, val = 0; 929 int ret; 930 931 if (priv->flags & AT803X_DISABLE_SMARTEEE) 932 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 933 AT803X_MMD3_SMARTEEE_CTL3, 934 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 935 936 if (priv->smarteee_lpi_tw_1g) { 937 mask |= 0xff00; 938 val |= priv->smarteee_lpi_tw_1g << 8; 939 } 940 if (priv->smarteee_lpi_tw_100m) { 941 mask |= 0x00ff; 942 val |= priv->smarteee_lpi_tw_100m; 943 } 944 if (!mask) 945 return 0; 946 947 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 948 mask, val); 949 if (ret) 950 return ret; 951 952 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 953 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 954 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 955 } 956 957 static int at803x_clk_out_config(struct phy_device *phydev) 958 { 959 struct at803x_priv *priv = phydev->priv; 960 961 if (!priv->clk_25m_mask) 962 return 0; 963 964 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 965 priv->clk_25m_mask, priv->clk_25m_reg); 966 } 967 968 static int at8031_pll_config(struct phy_device *phydev) 969 { 970 struct at803x_priv *priv = phydev->priv; 971 972 /* The default after hardware reset is PLL OFF. After a soft reset, the 973 * values are retained. 974 */ 975 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 976 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 977 0, AT803X_DEBUG_PLL_ON); 978 else 979 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 980 AT803X_DEBUG_PLL_ON, 0); 981 } 982 983 static int at803x_hibernation_mode_config(struct phy_device *phydev) 984 { 985 struct at803x_priv *priv = phydev->priv; 986 987 /* The default after hardware reset is hibernation mode enabled. After 988 * software reset, the value is retained. 989 */ 990 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) 991 return 0; 992 993 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 994 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 995 } 996 997 static int at803x_config_init(struct phy_device *phydev) 998 { 999 struct at803x_priv *priv = phydev->priv; 1000 int ret; 1001 1002 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 1003 /* Some bootloaders leave the fiber page selected. 1004 * Switch to the appropriate page (fiber or copper), as otherwise we 1005 * read the PHY capabilities from the wrong page. 1006 */ 1007 phy_lock_mdio_bus(phydev); 1008 ret = at803x_write_page(phydev, 1009 priv->is_fiber ? AT803X_PAGE_FIBER : 1010 AT803X_PAGE_COPPER); 1011 phy_unlock_mdio_bus(phydev); 1012 if (ret) 1013 return ret; 1014 1015 ret = at8031_pll_config(phydev); 1016 if (ret < 0) 1017 return ret; 1018 } 1019 1020 /* The RX and TX delay default is: 1021 * after HW reset: RX delay enabled and TX delay disabled 1022 * after SW reset: RX delay enabled, while TX delay retains the 1023 * value before reset. 1024 */ 1025 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1026 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1027 ret = at803x_enable_rx_delay(phydev); 1028 else 1029 ret = at803x_disable_rx_delay(phydev); 1030 if (ret < 0) 1031 return ret; 1032 1033 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1034 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1035 ret = at803x_enable_tx_delay(phydev); 1036 else 1037 ret = at803x_disable_tx_delay(phydev); 1038 if (ret < 0) 1039 return ret; 1040 1041 ret = at803x_smarteee_config(phydev); 1042 if (ret < 0) 1043 return ret; 1044 1045 ret = at803x_clk_out_config(phydev); 1046 if (ret < 0) 1047 return ret; 1048 1049 ret = at803x_hibernation_mode_config(phydev); 1050 if (ret < 0) 1051 return ret; 1052 1053 /* Ar803x extended next page bit is enabled by default. Cisco 1054 * multigig switches read this bit and attempt to negotiate 10Gbps 1055 * rates even if the next page bit is disabled. This is incorrect 1056 * behaviour but we still need to accommodate it. XNP is only needed 1057 * for 10Gbps support, so disable XNP. 1058 */ 1059 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 1060 } 1061 1062 static int at803x_ack_interrupt(struct phy_device *phydev) 1063 { 1064 int err; 1065 1066 err = phy_read(phydev, AT803X_INTR_STATUS); 1067 1068 return (err < 0) ? err : 0; 1069 } 1070 1071 static int at803x_config_intr(struct phy_device *phydev) 1072 { 1073 struct at803x_priv *priv = phydev->priv; 1074 int err; 1075 int value; 1076 1077 value = phy_read(phydev, AT803X_INTR_ENABLE); 1078 1079 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1080 /* Clear any pending interrupts */ 1081 err = at803x_ack_interrupt(phydev); 1082 if (err) 1083 return err; 1084 1085 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 1086 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 1087 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 1088 value |= AT803X_INTR_ENABLE_LINK_FAIL; 1089 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 1090 if (priv->is_fiber) { 1091 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 1092 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 1093 } 1094 1095 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 1096 } else { 1097 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 1098 if (err) 1099 return err; 1100 1101 /* Clear any pending interrupts */ 1102 err = at803x_ack_interrupt(phydev); 1103 } 1104 1105 return err; 1106 } 1107 1108 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 1109 { 1110 int irq_status, int_enabled; 1111 1112 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 1113 if (irq_status < 0) { 1114 phy_error(phydev); 1115 return IRQ_NONE; 1116 } 1117 1118 /* Read the current enabled interrupts */ 1119 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 1120 if (int_enabled < 0) { 1121 phy_error(phydev); 1122 return IRQ_NONE; 1123 } 1124 1125 /* See if this was one of our enabled interrupts */ 1126 if (!(irq_status & int_enabled)) 1127 return IRQ_NONE; 1128 1129 phy_trigger_machine(phydev); 1130 1131 return IRQ_HANDLED; 1132 } 1133 1134 static void at803x_link_change_notify(struct phy_device *phydev) 1135 { 1136 /* 1137 * Conduct a hardware reset for AT8030 every time a link loss is 1138 * signalled. This is necessary to circumvent a hardware bug that 1139 * occurs when the cable is unplugged while TX packets are pending 1140 * in the FIFO. In such cases, the FIFO enters an error mode it 1141 * cannot recover from by software. 1142 */ 1143 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 1144 struct at803x_context context; 1145 1146 at803x_context_save(phydev, &context); 1147 1148 phy_device_reset(phydev, 1); 1149 msleep(1); 1150 phy_device_reset(phydev, 0); 1151 msleep(1); 1152 1153 at803x_context_restore(phydev, &context); 1154 1155 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 1156 } 1157 } 1158 1159 static int at803x_read_specific_status(struct phy_device *phydev) 1160 { 1161 int ss; 1162 1163 /* Read the AT8035 PHY-Specific Status register, which indicates the 1164 * speed and duplex that the PHY is actually using, irrespective of 1165 * whether we are in autoneg mode or not. 1166 */ 1167 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 1168 if (ss < 0) 1169 return ss; 1170 1171 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 1172 int sfc, speed; 1173 1174 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 1175 if (sfc < 0) 1176 return sfc; 1177 1178 /* qca8081 takes the different bits for speed value from at803x */ 1179 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1180 speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 1181 else 1182 speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 1183 1184 switch (speed) { 1185 case AT803X_SS_SPEED_10: 1186 phydev->speed = SPEED_10; 1187 break; 1188 case AT803X_SS_SPEED_100: 1189 phydev->speed = SPEED_100; 1190 break; 1191 case AT803X_SS_SPEED_1000: 1192 phydev->speed = SPEED_1000; 1193 break; 1194 case QCA808X_SS_SPEED_2500: 1195 phydev->speed = SPEED_2500; 1196 break; 1197 } 1198 if (ss & AT803X_SS_DUPLEX) 1199 phydev->duplex = DUPLEX_FULL; 1200 else 1201 phydev->duplex = DUPLEX_HALF; 1202 1203 if (ss & AT803X_SS_MDIX) 1204 phydev->mdix = ETH_TP_MDI_X; 1205 else 1206 phydev->mdix = ETH_TP_MDI; 1207 1208 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 1209 case AT803X_SFC_MANUAL_MDI: 1210 phydev->mdix_ctrl = ETH_TP_MDI; 1211 break; 1212 case AT803X_SFC_MANUAL_MDIX: 1213 phydev->mdix_ctrl = ETH_TP_MDI_X; 1214 break; 1215 case AT803X_SFC_AUTOMATIC_CROSSOVER: 1216 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1217 break; 1218 } 1219 } 1220 1221 return 0; 1222 } 1223 1224 static int at803x_read_status(struct phy_device *phydev) 1225 { 1226 struct at803x_priv *priv = phydev->priv; 1227 int err, old_link = phydev->link; 1228 1229 if (priv->is_1000basex) 1230 return genphy_c37_read_status(phydev); 1231 1232 /* Update the link, but return if there was an error */ 1233 err = genphy_update_link(phydev); 1234 if (err) 1235 return err; 1236 1237 /* why bother the PHY if nothing can have changed */ 1238 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 1239 return 0; 1240 1241 phydev->speed = SPEED_UNKNOWN; 1242 phydev->duplex = DUPLEX_UNKNOWN; 1243 phydev->pause = 0; 1244 phydev->asym_pause = 0; 1245 1246 err = genphy_read_lpa(phydev); 1247 if (err < 0) 1248 return err; 1249 1250 err = at803x_read_specific_status(phydev); 1251 if (err < 0) 1252 return err; 1253 1254 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1255 phy_resolve_aneg_pause(phydev); 1256 1257 return 0; 1258 } 1259 1260 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 1261 { 1262 u16 val; 1263 1264 switch (ctrl) { 1265 case ETH_TP_MDI: 1266 val = AT803X_SFC_MANUAL_MDI; 1267 break; 1268 case ETH_TP_MDI_X: 1269 val = AT803X_SFC_MANUAL_MDIX; 1270 break; 1271 case ETH_TP_MDI_AUTO: 1272 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 1273 break; 1274 default: 1275 return 0; 1276 } 1277 1278 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 1279 AT803X_SFC_MDI_CROSSOVER_MODE_M, 1280 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1281 } 1282 1283 static int at803x_config_aneg(struct phy_device *phydev) 1284 { 1285 struct at803x_priv *priv = phydev->priv; 1286 int ret; 1287 1288 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1289 if (ret < 0) 1290 return ret; 1291 1292 /* Changes of the midx bits are disruptive to the normal operation; 1293 * therefore any changes to these registers must be followed by a 1294 * software reset to take effect. 1295 */ 1296 if (ret == 1) { 1297 ret = genphy_soft_reset(phydev); 1298 if (ret < 0) 1299 return ret; 1300 } 1301 1302 if (priv->is_1000basex) 1303 return genphy_c37_config_aneg(phydev); 1304 1305 /* Do not restart auto-negotiation by setting ret to 0 defautly, 1306 * when calling __genphy_config_aneg later. 1307 */ 1308 ret = 0; 1309 1310 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1311 int phy_ctrl = 0; 1312 1313 /* The reg MII_BMCR also needs to be configured for force mode, the 1314 * genphy_config_aneg is also needed. 1315 */ 1316 if (phydev->autoneg == AUTONEG_DISABLE) 1317 genphy_c45_pma_setup_forced(phydev); 1318 1319 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1320 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1321 1322 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1323 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1324 if (ret < 0) 1325 return ret; 1326 } 1327 1328 return __genphy_config_aneg(phydev, ret); 1329 } 1330 1331 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1332 { 1333 int val; 1334 1335 val = phy_read(phydev, AT803X_SMART_SPEED); 1336 if (val < 0) 1337 return val; 1338 1339 if (val & AT803X_SMART_SPEED_ENABLE) 1340 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1341 else 1342 *d = DOWNSHIFT_DEV_DISABLE; 1343 1344 return 0; 1345 } 1346 1347 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1348 { 1349 u16 mask, set; 1350 int ret; 1351 1352 switch (cnt) { 1353 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1354 cnt = AT803X_DEFAULT_DOWNSHIFT; 1355 fallthrough; 1356 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1357 set = AT803X_SMART_SPEED_ENABLE | 1358 AT803X_SMART_SPEED_BYPASS_TIMER | 1359 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1360 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1361 break; 1362 case DOWNSHIFT_DEV_DISABLE: 1363 set = 0; 1364 mask = AT803X_SMART_SPEED_ENABLE | 1365 AT803X_SMART_SPEED_BYPASS_TIMER; 1366 break; 1367 default: 1368 return -EINVAL; 1369 } 1370 1371 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1372 1373 /* After changing the smart speed settings, we need to perform a 1374 * software reset, use phy_init_hw() to make sure we set the 1375 * reapply any values which might got lost during software reset. 1376 */ 1377 if (ret == 1) 1378 ret = phy_init_hw(phydev); 1379 1380 return ret; 1381 } 1382 1383 static int at803x_get_tunable(struct phy_device *phydev, 1384 struct ethtool_tunable *tuna, void *data) 1385 { 1386 switch (tuna->id) { 1387 case ETHTOOL_PHY_DOWNSHIFT: 1388 return at803x_get_downshift(phydev, data); 1389 default: 1390 return -EOPNOTSUPP; 1391 } 1392 } 1393 1394 static int at803x_set_tunable(struct phy_device *phydev, 1395 struct ethtool_tunable *tuna, const void *data) 1396 { 1397 switch (tuna->id) { 1398 case ETHTOOL_PHY_DOWNSHIFT: 1399 return at803x_set_downshift(phydev, *(const u8 *)data); 1400 default: 1401 return -EOPNOTSUPP; 1402 } 1403 } 1404 1405 static int at803x_cable_test_result_trans(u16 status) 1406 { 1407 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1408 case AT803X_CDT_STATUS_STAT_NORMAL: 1409 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1410 case AT803X_CDT_STATUS_STAT_SHORT: 1411 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1412 case AT803X_CDT_STATUS_STAT_OPEN: 1413 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1414 case AT803X_CDT_STATUS_STAT_FAIL: 1415 default: 1416 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1417 } 1418 } 1419 1420 static bool at803x_cdt_test_failed(u16 status) 1421 { 1422 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1423 AT803X_CDT_STATUS_STAT_FAIL; 1424 } 1425 1426 static bool at803x_cdt_fault_length_valid(u16 status) 1427 { 1428 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1429 case AT803X_CDT_STATUS_STAT_OPEN: 1430 case AT803X_CDT_STATUS_STAT_SHORT: 1431 return true; 1432 } 1433 return false; 1434 } 1435 1436 static int at803x_cdt_fault_length(u16 status) 1437 { 1438 int dt; 1439 1440 /* According to the datasheet the distance to the fault is 1441 * DELTA_TIME * 0.824 meters. 1442 * 1443 * The author suspect the correct formula is: 1444 * 1445 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1446 * 1447 * where c is the speed of light, VF is the velocity factor of 1448 * the twisted pair cable, 125MHz the counter frequency and 1449 * we need to divide by 2 because the hardware will measure the 1450 * round trip time to the fault and back to the PHY. 1451 * 1452 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1453 * datasheet. 1454 */ 1455 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1456 1457 return (dt * 824) / 10; 1458 } 1459 1460 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1461 { 1462 u16 cdt; 1463 1464 /* qca8081 takes the different bit 15 to enable CDT test */ 1465 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1466 cdt = QCA808X_CDT_ENABLE_TEST | 1467 QCA808X_CDT_LENGTH_UNIT | 1468 QCA808X_CDT_INTER_CHECK_DIS; 1469 else 1470 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1471 AT803X_CDT_ENABLE_TEST; 1472 1473 return phy_write(phydev, AT803X_CDT, cdt); 1474 } 1475 1476 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1477 { 1478 int val, ret; 1479 u16 cdt_en; 1480 1481 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1482 cdt_en = QCA808X_CDT_ENABLE_TEST; 1483 else 1484 cdt_en = AT803X_CDT_ENABLE_TEST; 1485 1486 /* One test run takes about 25ms */ 1487 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1488 !(val & cdt_en), 1489 30000, 100000, true); 1490 1491 return ret < 0 ? ret : 0; 1492 } 1493 1494 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1495 { 1496 static const int ethtool_pair[] = { 1497 ETHTOOL_A_CABLE_PAIR_A, 1498 ETHTOOL_A_CABLE_PAIR_B, 1499 ETHTOOL_A_CABLE_PAIR_C, 1500 ETHTOOL_A_CABLE_PAIR_D, 1501 }; 1502 int ret, val; 1503 1504 ret = at803x_cdt_start(phydev, pair); 1505 if (ret) 1506 return ret; 1507 1508 ret = at803x_cdt_wait_for_completion(phydev); 1509 if (ret) 1510 return ret; 1511 1512 val = phy_read(phydev, AT803X_CDT_STATUS); 1513 if (val < 0) 1514 return val; 1515 1516 if (at803x_cdt_test_failed(val)) 1517 return 0; 1518 1519 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1520 at803x_cable_test_result_trans(val)); 1521 1522 if (at803x_cdt_fault_length_valid(val)) 1523 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1524 at803x_cdt_fault_length(val)); 1525 1526 return 1; 1527 } 1528 1529 static int at803x_cable_test_get_status(struct phy_device *phydev, 1530 bool *finished) 1531 { 1532 unsigned long pair_mask; 1533 int retries = 20; 1534 int pair, ret; 1535 1536 if (phydev->phy_id == ATH9331_PHY_ID || 1537 phydev->phy_id == ATH8032_PHY_ID || 1538 phydev->phy_id == QCA9561_PHY_ID) 1539 pair_mask = 0x3; 1540 else 1541 pair_mask = 0xf; 1542 1543 *finished = false; 1544 1545 /* According to the datasheet the CDT can be performed when 1546 * there is no link partner or when the link partner is 1547 * auto-negotiating. Starting the test will restart the AN 1548 * automatically. It seems that doing this repeatedly we will 1549 * get a slot where our link partner won't disturb our 1550 * measurement. 1551 */ 1552 while (pair_mask && retries--) { 1553 for_each_set_bit(pair, &pair_mask, 4) { 1554 ret = at803x_cable_test_one_pair(phydev, pair); 1555 if (ret < 0) 1556 return ret; 1557 if (ret) 1558 clear_bit(pair, &pair_mask); 1559 } 1560 if (pair_mask) 1561 msleep(250); 1562 } 1563 1564 *finished = true; 1565 1566 return 0; 1567 } 1568 1569 static int at803x_cable_test_start(struct phy_device *phydev) 1570 { 1571 /* Enable auto-negotiation, but advertise no capabilities, no link 1572 * will be established. A restart of the auto-negotiation is not 1573 * required, because the cable test will automatically break the link. 1574 */ 1575 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1576 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1577 if (phydev->phy_id != ATH9331_PHY_ID && 1578 phydev->phy_id != ATH8032_PHY_ID && 1579 phydev->phy_id != QCA9561_PHY_ID) 1580 phy_write(phydev, MII_CTRL1000, 0); 1581 1582 /* we do all the (time consuming) work later */ 1583 return 0; 1584 } 1585 1586 static int qca83xx_config_init(struct phy_device *phydev) 1587 { 1588 u8 switch_revision; 1589 1590 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1591 1592 switch (switch_revision) { 1593 case 1: 1594 /* For 100M waveform */ 1595 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1596 /* Turn on Gigabit clock */ 1597 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1598 break; 1599 1600 case 2: 1601 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1602 fallthrough; 1603 case 4: 1604 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1605 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 1606 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1607 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1608 break; 1609 } 1610 1611 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 1612 * Disable on init and enable only with 100m speed following 1613 * qca original source code. 1614 */ 1615 if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 1616 phydev->drv->phy_id == QCA8327_B_PHY_ID) 1617 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1618 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1619 1620 /* Following original QCA sourcecode set port to prefer master */ 1621 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 1622 1623 return 0; 1624 } 1625 1626 static void qca83xx_link_change_notify(struct phy_device *phydev) 1627 { 1628 /* QCA8337 doesn't require DAC Amplitude adjustement */ 1629 if (phydev->drv->phy_id == QCA8337_PHY_ID) 1630 return; 1631 1632 /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 1633 if (phydev->state == PHY_RUNNING) { 1634 if (phydev->speed == SPEED_100) 1635 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1636 QCA8327_DEBUG_MANU_CTRL_EN, 1637 QCA8327_DEBUG_MANU_CTRL_EN); 1638 } else { 1639 /* Reset DAC Amplitude adjustment */ 1640 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1641 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1642 } 1643 } 1644 1645 static int qca83xx_resume(struct phy_device *phydev) 1646 { 1647 int ret, val; 1648 1649 /* Skip reset if not suspended */ 1650 if (!phydev->suspended) 1651 return 0; 1652 1653 /* Reinit the port, reset values set by suspend */ 1654 qca83xx_config_init(phydev); 1655 1656 /* Reset the port on port resume */ 1657 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1658 1659 /* On resume from suspend the switch execute a reset and 1660 * restart auto-negotiation. Wait for reset to complete. 1661 */ 1662 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1663 50000, 600000, true); 1664 if (ret) 1665 return ret; 1666 1667 msleep(1); 1668 1669 return 0; 1670 } 1671 1672 static int qca83xx_suspend(struct phy_device *phydev) 1673 { 1674 u16 mask = 0; 1675 1676 /* Only QCA8337 support actual suspend. 1677 * QCA8327 cause port unreliability when phy suspend 1678 * is set. 1679 */ 1680 if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1681 genphy_suspend(phydev); 1682 } else { 1683 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1684 phy_modify(phydev, MII_BMCR, mask, 0); 1685 } 1686 1687 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1688 AT803X_DEBUG_GATE_CLK_IN1000, 0); 1689 1690 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1691 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1692 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1693 1694 return 0; 1695 } 1696 1697 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 1698 { 1699 int ret; 1700 1701 /* Enable fast retrain */ 1702 ret = genphy_c45_fast_retrain(phydev, true); 1703 if (ret) 1704 return ret; 1705 1706 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 1707 QCA808X_TOP_OPTION1_DATA); 1708 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 1709 QCA808X_MSE_THRESHOLD_20DB_VALUE); 1710 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 1711 QCA808X_MSE_THRESHOLD_17DB_VALUE); 1712 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 1713 QCA808X_MSE_THRESHOLD_27DB_VALUE); 1714 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 1715 QCA808X_MSE_THRESHOLD_28DB_VALUE); 1716 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 1717 QCA808X_MMD3_DEBUG_1_VALUE); 1718 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 1719 QCA808X_MMD3_DEBUG_4_VALUE); 1720 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 1721 QCA808X_MMD3_DEBUG_5_VALUE); 1722 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 1723 QCA808X_MMD3_DEBUG_3_VALUE); 1724 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 1725 QCA808X_MMD3_DEBUG_6_VALUE); 1726 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 1727 QCA808X_MMD3_DEBUG_2_VALUE); 1728 1729 return 0; 1730 } 1731 1732 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 1733 { 1734 u16 seed_value; 1735 1736 if (!enable) 1737 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1738 QCA808X_MASTER_SLAVE_SEED_ENABLE, 0); 1739 1740 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE); 1741 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1742 QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE, 1743 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) | 1744 QCA808X_MASTER_SLAVE_SEED_ENABLE); 1745 } 1746 1747 static bool qca808x_is_prefer_master(struct phy_device *phydev) 1748 { 1749 return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) || 1750 (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED); 1751 } 1752 1753 static int qca808x_config_init(struct phy_device *phydev) 1754 { 1755 int ret; 1756 1757 /* Active adc&vga on 802.3az for the link 1000M and 100M */ 1758 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 1759 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 1760 if (ret) 1761 return ret; 1762 1763 /* Adjust the threshold on 802.3az for the link 1000M */ 1764 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 1765 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 1766 if (ret) 1767 return ret; 1768 1769 /* Config the fast retrain for the link 2500M */ 1770 ret = qca808x_phy_fast_retrain_config(phydev); 1771 if (ret) 1772 return ret; 1773 1774 ret = genphy_read_master_slave(phydev); 1775 if (ret < 0) 1776 return ret; 1777 1778 if (!qca808x_is_prefer_master(phydev)) { 1779 /* Enable seed and configure lower ramdom seed to make phy linked as slave mode */ 1780 ret = qca808x_phy_ms_seed_enable(phydev, true); 1781 if (ret) 1782 return ret; 1783 } 1784 1785 /* Configure adc threshold as 100mv for the link 10M */ 1786 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 1787 QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 1788 } 1789 1790 static int qca808x_read_status(struct phy_device *phydev) 1791 { 1792 int ret; 1793 1794 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1795 if (ret < 0) 1796 return ret; 1797 1798 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 1799 ret & MDIO_AN_10GBT_STAT_LP2_5G); 1800 1801 ret = genphy_read_status(phydev); 1802 if (ret) 1803 return ret; 1804 1805 ret = at803x_read_specific_status(phydev); 1806 if (ret < 0) 1807 return ret; 1808 1809 if (phydev->link) { 1810 if (phydev->speed == SPEED_2500) 1811 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1812 else 1813 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1814 } else { 1815 /* generate seed as a lower random value to make PHY linked as SLAVE easily, 1816 * except for master/slave configuration fault detected or the master mode 1817 * preferred. 1818 * 1819 * the reason for not putting this code into the function link_change_notify is 1820 * the corner case where the link partner is also the qca8081 PHY and the seed 1821 * value is configured as the same value, the link can't be up and no link change 1822 * occurs. 1823 */ 1824 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR || 1825 qca808x_is_prefer_master(phydev)) { 1826 qca808x_phy_ms_seed_enable(phydev, false); 1827 } else { 1828 qca808x_phy_ms_seed_enable(phydev, true); 1829 } 1830 } 1831 1832 return 0; 1833 } 1834 1835 static int qca808x_soft_reset(struct phy_device *phydev) 1836 { 1837 int ret; 1838 1839 ret = genphy_soft_reset(phydev); 1840 if (ret < 0) 1841 return ret; 1842 1843 return qca808x_phy_ms_seed_enable(phydev, true); 1844 } 1845 1846 static bool qca808x_cdt_fault_length_valid(int cdt_code) 1847 { 1848 switch (cdt_code) { 1849 case QCA808X_CDT_STATUS_STAT_SHORT: 1850 case QCA808X_CDT_STATUS_STAT_OPEN: 1851 return true; 1852 default: 1853 return false; 1854 } 1855 } 1856 1857 static int qca808x_cable_test_result_trans(int cdt_code) 1858 { 1859 switch (cdt_code) { 1860 case QCA808X_CDT_STATUS_STAT_NORMAL: 1861 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1862 case QCA808X_CDT_STATUS_STAT_SHORT: 1863 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1864 case QCA808X_CDT_STATUS_STAT_OPEN: 1865 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1866 case QCA808X_CDT_STATUS_STAT_FAIL: 1867 default: 1868 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1869 } 1870 } 1871 1872 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 1873 { 1874 int val; 1875 u32 cdt_length_reg = 0; 1876 1877 switch (pair) { 1878 case ETHTOOL_A_CABLE_PAIR_A: 1879 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 1880 break; 1881 case ETHTOOL_A_CABLE_PAIR_B: 1882 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 1883 break; 1884 case ETHTOOL_A_CABLE_PAIR_C: 1885 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 1886 break; 1887 case ETHTOOL_A_CABLE_PAIR_D: 1888 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 1889 break; 1890 default: 1891 return -EINVAL; 1892 } 1893 1894 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 1895 if (val < 0) 1896 return val; 1897 1898 return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 1899 } 1900 1901 static int qca808x_cable_test_start(struct phy_device *phydev) 1902 { 1903 int ret; 1904 1905 /* perform CDT with the following configs: 1906 * 1. disable hibernation. 1907 * 2. force PHY working in MDI mode. 1908 * 3. for PHY working in 1000BaseT. 1909 * 4. configure the threshold. 1910 */ 1911 1912 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 1913 if (ret < 0) 1914 return ret; 1915 1916 ret = at803x_config_mdix(phydev, ETH_TP_MDI); 1917 if (ret < 0) 1918 return ret; 1919 1920 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 1921 phydev->duplex = DUPLEX_FULL; 1922 phydev->speed = SPEED_1000; 1923 ret = genphy_c45_pma_setup_forced(phydev); 1924 if (ret < 0) 1925 return ret; 1926 1927 ret = genphy_setup_forced(phydev); 1928 if (ret < 0) 1929 return ret; 1930 1931 /* configure the thresholds for open, short, pair ok test */ 1932 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 1933 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 1934 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 1935 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 1936 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 1937 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 1938 1939 return 0; 1940 } 1941 1942 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 1943 { 1944 int ret, val; 1945 int pair_a, pair_b, pair_c, pair_d; 1946 1947 *finished = false; 1948 1949 ret = at803x_cdt_start(phydev, 0); 1950 if (ret) 1951 return ret; 1952 1953 ret = at803x_cdt_wait_for_completion(phydev); 1954 if (ret) 1955 return ret; 1956 1957 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 1958 if (val < 0) 1959 return val; 1960 1961 pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 1962 pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 1963 pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 1964 pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 1965 1966 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1967 qca808x_cable_test_result_trans(pair_a)); 1968 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 1969 qca808x_cable_test_result_trans(pair_b)); 1970 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 1971 qca808x_cable_test_result_trans(pair_c)); 1972 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 1973 qca808x_cable_test_result_trans(pair_d)); 1974 1975 if (qca808x_cdt_fault_length_valid(pair_a)) 1976 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 1977 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 1978 if (qca808x_cdt_fault_length_valid(pair_b)) 1979 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 1980 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 1981 if (qca808x_cdt_fault_length_valid(pair_c)) 1982 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 1983 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 1984 if (qca808x_cdt_fault_length_valid(pair_d)) 1985 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 1986 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 1987 1988 *finished = true; 1989 1990 return 0; 1991 } 1992 1993 static int qca808x_get_features(struct phy_device *phydev) 1994 { 1995 int ret; 1996 1997 ret = genphy_c45_pma_read_abilities(phydev); 1998 if (ret) 1999 return ret; 2000 2001 /* The autoneg ability is not existed in bit3 of MMD7.1, 2002 * but it is supported by qca808x PHY, so we add it here 2003 * manually. 2004 */ 2005 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); 2006 2007 /* As for the qca8081 1G version chip, the 2500baseT ability is also 2008 * existed in the bit0 of MMD1.21, we need to remove it manually if 2009 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d. 2010 */ 2011 ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE); 2012 if (ret < 0) 2013 return ret; 2014 2015 if (QCA808X_PHY_CHIP_TYPE_1G & ret) 2016 linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); 2017 2018 return 0; 2019 } 2020 2021 static struct phy_driver at803x_driver[] = { 2022 { 2023 /* Qualcomm Atheros AR8035 */ 2024 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 2025 .name = "Qualcomm Atheros AR8035", 2026 .flags = PHY_POLL_CABLE_TEST, 2027 .probe = at803x_probe, 2028 .config_aneg = at803x_config_aneg, 2029 .config_init = at803x_config_init, 2030 .soft_reset = genphy_soft_reset, 2031 .set_wol = at803x_set_wol, 2032 .get_wol = at803x_get_wol, 2033 .suspend = at803x_suspend, 2034 .resume = at803x_resume, 2035 /* PHY_GBIT_FEATURES */ 2036 .read_status = at803x_read_status, 2037 .config_intr = at803x_config_intr, 2038 .handle_interrupt = at803x_handle_interrupt, 2039 .get_tunable = at803x_get_tunable, 2040 .set_tunable = at803x_set_tunable, 2041 .cable_test_start = at803x_cable_test_start, 2042 .cable_test_get_status = at803x_cable_test_get_status, 2043 }, { 2044 /* Qualcomm Atheros AR8030 */ 2045 .phy_id = ATH8030_PHY_ID, 2046 .name = "Qualcomm Atheros AR8030", 2047 .phy_id_mask = AT8030_PHY_ID_MASK, 2048 .probe = at803x_probe, 2049 .config_init = at803x_config_init, 2050 .link_change_notify = at803x_link_change_notify, 2051 .set_wol = at803x_set_wol, 2052 .get_wol = at803x_get_wol, 2053 .suspend = at803x_suspend, 2054 .resume = at803x_resume, 2055 /* PHY_BASIC_FEATURES */ 2056 .config_intr = at803x_config_intr, 2057 .handle_interrupt = at803x_handle_interrupt, 2058 }, { 2059 /* Qualcomm Atheros AR8031/AR8033 */ 2060 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 2061 .name = "Qualcomm Atheros AR8031/AR8033", 2062 .flags = PHY_POLL_CABLE_TEST, 2063 .probe = at803x_probe, 2064 .config_init = at803x_config_init, 2065 .config_aneg = at803x_config_aneg, 2066 .soft_reset = genphy_soft_reset, 2067 .set_wol = at803x_set_wol, 2068 .get_wol = at803x_get_wol, 2069 .suspend = at803x_suspend, 2070 .resume = at803x_resume, 2071 .read_page = at803x_read_page, 2072 .write_page = at803x_write_page, 2073 .get_features = at803x_get_features, 2074 .read_status = at803x_read_status, 2075 .config_intr = &at803x_config_intr, 2076 .handle_interrupt = at803x_handle_interrupt, 2077 .get_tunable = at803x_get_tunable, 2078 .set_tunable = at803x_set_tunable, 2079 .cable_test_start = at803x_cable_test_start, 2080 .cable_test_get_status = at803x_cable_test_get_status, 2081 }, { 2082 /* Qualcomm Atheros AR8032 */ 2083 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 2084 .name = "Qualcomm Atheros AR8032", 2085 .probe = at803x_probe, 2086 .flags = PHY_POLL_CABLE_TEST, 2087 .config_init = at803x_config_init, 2088 .link_change_notify = at803x_link_change_notify, 2089 .set_wol = at803x_set_wol, 2090 .get_wol = at803x_get_wol, 2091 .suspend = at803x_suspend, 2092 .resume = at803x_resume, 2093 /* PHY_BASIC_FEATURES */ 2094 .config_intr = at803x_config_intr, 2095 .handle_interrupt = at803x_handle_interrupt, 2096 .cable_test_start = at803x_cable_test_start, 2097 .cable_test_get_status = at803x_cable_test_get_status, 2098 }, { 2099 /* ATHEROS AR9331 */ 2100 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 2101 .name = "Qualcomm Atheros AR9331 built-in PHY", 2102 .probe = at803x_probe, 2103 .suspend = at803x_suspend, 2104 .resume = at803x_resume, 2105 .flags = PHY_POLL_CABLE_TEST, 2106 /* PHY_BASIC_FEATURES */ 2107 .config_intr = &at803x_config_intr, 2108 .handle_interrupt = at803x_handle_interrupt, 2109 .cable_test_start = at803x_cable_test_start, 2110 .cable_test_get_status = at803x_cable_test_get_status, 2111 .read_status = at803x_read_status, 2112 .soft_reset = genphy_soft_reset, 2113 .config_aneg = at803x_config_aneg, 2114 }, { 2115 /* Qualcomm Atheros QCA9561 */ 2116 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 2117 .name = "Qualcomm Atheros QCA9561 built-in PHY", 2118 .probe = at803x_probe, 2119 .suspend = at803x_suspend, 2120 .resume = at803x_resume, 2121 .flags = PHY_POLL_CABLE_TEST, 2122 /* PHY_BASIC_FEATURES */ 2123 .config_intr = &at803x_config_intr, 2124 .handle_interrupt = at803x_handle_interrupt, 2125 .cable_test_start = at803x_cable_test_start, 2126 .cable_test_get_status = at803x_cable_test_get_status, 2127 .read_status = at803x_read_status, 2128 .soft_reset = genphy_soft_reset, 2129 .config_aneg = at803x_config_aneg, 2130 }, { 2131 /* QCA8337 */ 2132 .phy_id = QCA8337_PHY_ID, 2133 .phy_id_mask = QCA8K_PHY_ID_MASK, 2134 .name = "Qualcomm Atheros 8337 internal PHY", 2135 /* PHY_GBIT_FEATURES */ 2136 .link_change_notify = qca83xx_link_change_notify, 2137 .probe = at803x_probe, 2138 .flags = PHY_IS_INTERNAL, 2139 .config_init = qca83xx_config_init, 2140 .soft_reset = genphy_soft_reset, 2141 .get_sset_count = at803x_get_sset_count, 2142 .get_strings = at803x_get_strings, 2143 .get_stats = at803x_get_stats, 2144 .suspend = qca83xx_suspend, 2145 .resume = qca83xx_resume, 2146 }, { 2147 /* QCA8327-A from switch QCA8327-AL1A */ 2148 .phy_id = QCA8327_A_PHY_ID, 2149 .phy_id_mask = QCA8K_PHY_ID_MASK, 2150 .name = "Qualcomm Atheros 8327-A internal PHY", 2151 /* PHY_GBIT_FEATURES */ 2152 .link_change_notify = qca83xx_link_change_notify, 2153 .probe = at803x_probe, 2154 .flags = PHY_IS_INTERNAL, 2155 .config_init = qca83xx_config_init, 2156 .soft_reset = genphy_soft_reset, 2157 .get_sset_count = at803x_get_sset_count, 2158 .get_strings = at803x_get_strings, 2159 .get_stats = at803x_get_stats, 2160 .suspend = qca83xx_suspend, 2161 .resume = qca83xx_resume, 2162 }, { 2163 /* QCA8327-B from switch QCA8327-BL1A */ 2164 .phy_id = QCA8327_B_PHY_ID, 2165 .phy_id_mask = QCA8K_PHY_ID_MASK, 2166 .name = "Qualcomm Atheros 8327-B internal PHY", 2167 /* PHY_GBIT_FEATURES */ 2168 .link_change_notify = qca83xx_link_change_notify, 2169 .probe = at803x_probe, 2170 .flags = PHY_IS_INTERNAL, 2171 .config_init = qca83xx_config_init, 2172 .soft_reset = genphy_soft_reset, 2173 .get_sset_count = at803x_get_sset_count, 2174 .get_strings = at803x_get_strings, 2175 .get_stats = at803x_get_stats, 2176 .suspend = qca83xx_suspend, 2177 .resume = qca83xx_resume, 2178 }, { 2179 /* Qualcomm QCA8081 */ 2180 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2181 .name = "Qualcomm QCA8081", 2182 .flags = PHY_POLL_CABLE_TEST, 2183 .probe = at803x_probe, 2184 .config_intr = at803x_config_intr, 2185 .handle_interrupt = at803x_handle_interrupt, 2186 .get_tunable = at803x_get_tunable, 2187 .set_tunable = at803x_set_tunable, 2188 .set_wol = at803x_set_wol, 2189 .get_wol = at803x_get_wol, 2190 .get_features = qca808x_get_features, 2191 .config_aneg = at803x_config_aneg, 2192 .suspend = genphy_suspend, 2193 .resume = genphy_resume, 2194 .read_status = qca808x_read_status, 2195 .config_init = qca808x_config_init, 2196 .soft_reset = qca808x_soft_reset, 2197 .cable_test_start = qca808x_cable_test_start, 2198 .cable_test_get_status = qca808x_cable_test_get_status, 2199 }, }; 2200 2201 module_phy_driver(at803x_driver); 2202 2203 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 2204 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 2205 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 2206 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 2207 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 2208 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 2209 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2210 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2211 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2212 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2213 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 2214 { } 2215 }; 2216 2217 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2218