1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <dt-bindings/net/qca-ar803x.h> 23 24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 25 #define AT803X_SFC_ASSERT_CRS BIT(11) 26 #define AT803X_SFC_FORCE_LINK BIT(10) 27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 29 #define AT803X_SFC_MANUAL_MDIX 0x1 30 #define AT803X_SFC_MANUAL_MDI 0x0 31 #define AT803X_SFC_SQE_TEST BIT(2) 32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 33 #define AT803X_SFC_DISABLE_JABBER BIT(0) 34 35 #define AT803X_SPECIFIC_STATUS 0x11 36 #define AT803X_SS_SPEED_MASK (3 << 14) 37 #define AT803X_SS_SPEED_1000 (2 << 14) 38 #define AT803X_SS_SPEED_100 (1 << 14) 39 #define AT803X_SS_SPEED_10 (0 << 14) 40 #define AT803X_SS_DUPLEX BIT(13) 41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 42 #define AT803X_SS_MDIX BIT(6) 43 44 #define AT803X_INTR_ENABLE 0x12 45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 53 #define AT803X_INTR_ENABLE_WOL BIT(0) 54 55 #define AT803X_INTR_STATUS 0x13 56 57 #define AT803X_SMART_SPEED 0x14 58 #define AT803X_SMART_SPEED_ENABLE BIT(5) 59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 61 #define AT803X_CDT 0x16 62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 63 #define AT803X_CDT_ENABLE_TEST BIT(0) 64 #define AT803X_CDT_STATUS 0x1c 65 #define AT803X_CDT_STATUS_STAT_NORMAL 0 66 #define AT803X_CDT_STATUS_STAT_SHORT 1 67 #define AT803X_CDT_STATUS_STAT_OPEN 2 68 #define AT803X_CDT_STATUS_STAT_FAIL 3 69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 71 #define AT803X_LED_CONTROL 0x18 72 73 #define AT803X_DEVICE_ADDR 0x03 74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 77 #define AT803X_REG_CHIP_CONFIG 0x1f 78 #define AT803X_BT_BX_REG_SEL 0x8000 79 80 #define AT803X_DEBUG_ADDR 0x1D 81 #define AT803X_DEBUG_DATA 0x1E 82 83 #define AT803X_MODE_CFG_MASK 0x0F 84 #define AT803X_MODE_CFG_SGMII 0x01 85 86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 88 89 #define AT803X_DEBUG_REG_0 0x00 90 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 91 92 #define AT803X_DEBUG_REG_5 0x05 93 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 94 95 #define AT803X_DEBUG_REG_3C 0x3C 96 97 #define AT803X_DEBUG_REG_3D 0x3D 98 99 #define AT803X_DEBUG_REG_1F 0x1F 100 #define AT803X_DEBUG_PLL_ON BIT(2) 101 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 102 103 #define MDIO_AZ_DEBUG 0x800D 104 105 /* AT803x supports either the XTAL input pad, an internal PLL or the 106 * DSP as clock reference for the clock output pad. The XTAL reference 107 * is only used for 25 MHz output, all other frequencies need the PLL. 108 * The DSP as a clock reference is used in synchronous ethernet 109 * applications. 110 * 111 * By default the PLL is only enabled if there is a link. Otherwise 112 * the PHY will go into low power state and disabled the PLL. You can 113 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 114 * enabled. 115 */ 116 #define AT803X_MMD7_CLK25M 0x8016 117 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 118 #define AT803X_CLK_OUT_25MHZ_XTAL 0 119 #define AT803X_CLK_OUT_25MHZ_DSP 1 120 #define AT803X_CLK_OUT_50MHZ_PLL 2 121 #define AT803X_CLK_OUT_50MHZ_DSP 3 122 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 123 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 124 #define AT803X_CLK_OUT_125MHZ_PLL 6 125 #define AT803X_CLK_OUT_125MHZ_DSP 7 126 127 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 128 * but doesn't support choosing between XTAL/PLL and DSP. 129 */ 130 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 131 132 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 133 #define AT803X_CLK_OUT_STRENGTH_FULL 0 134 #define AT803X_CLK_OUT_STRENGTH_HALF 1 135 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 136 137 #define AT803X_DEFAULT_DOWNSHIFT 5 138 #define AT803X_MIN_DOWNSHIFT 2 139 #define AT803X_MAX_DOWNSHIFT 9 140 141 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 142 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 143 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 144 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 145 146 #define ATH9331_PHY_ID 0x004dd041 147 #define ATH8030_PHY_ID 0x004dd076 148 #define ATH8031_PHY_ID 0x004dd074 149 #define ATH8032_PHY_ID 0x004dd023 150 #define ATH8035_PHY_ID 0x004dd072 151 #define AT8030_PHY_ID_MASK 0xffffffef 152 153 #define QCA8327_PHY_ID 0x004dd034 154 #define QCA8337_PHY_ID 0x004dd036 155 #define QCA8K_PHY_ID_MASK 0xffffffff 156 157 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 158 159 #define AT803X_PAGE_FIBER 0 160 #define AT803X_PAGE_COPPER 1 161 162 /* don't turn off internal PLL */ 163 #define AT803X_KEEP_PLL_ENABLED BIT(0) 164 #define AT803X_DISABLE_SMARTEEE BIT(1) 165 166 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 167 MODULE_AUTHOR("Matus Ujhelyi"); 168 MODULE_LICENSE("GPL"); 169 170 enum stat_access_type { 171 PHY, 172 MMD 173 }; 174 175 struct at803x_hw_stat { 176 const char *string; 177 u8 reg; 178 u32 mask; 179 enum stat_access_type access_type; 180 }; 181 182 static struct at803x_hw_stat at803x_hw_stats[] = { 183 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 184 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 185 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 186 }; 187 188 struct at803x_priv { 189 int flags; 190 u16 clk_25m_reg; 191 u16 clk_25m_mask; 192 u8 smarteee_lpi_tw_1g; 193 u8 smarteee_lpi_tw_100m; 194 struct regulator_dev *vddio_rdev; 195 struct regulator_dev *vddh_rdev; 196 struct regulator *vddio; 197 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 198 }; 199 200 struct at803x_context { 201 u16 bmcr; 202 u16 advertise; 203 u16 control1000; 204 u16 int_enable; 205 u16 smart_speed; 206 u16 led_control; 207 }; 208 209 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 210 { 211 int ret; 212 213 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 214 if (ret < 0) 215 return ret; 216 217 return phy_write(phydev, AT803X_DEBUG_DATA, data); 218 } 219 220 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 221 { 222 int ret; 223 224 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 225 if (ret < 0) 226 return ret; 227 228 return phy_read(phydev, AT803X_DEBUG_DATA); 229 } 230 231 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 232 u16 clear, u16 set) 233 { 234 u16 val; 235 int ret; 236 237 ret = at803x_debug_reg_read(phydev, reg); 238 if (ret < 0) 239 return ret; 240 241 val = ret & 0xffff; 242 val &= ~clear; 243 val |= set; 244 245 return phy_write(phydev, AT803X_DEBUG_DATA, val); 246 } 247 248 static int at803x_write_page(struct phy_device *phydev, int page) 249 { 250 int mask; 251 int set; 252 253 if (page == AT803X_PAGE_COPPER) { 254 set = AT803X_BT_BX_REG_SEL; 255 mask = 0; 256 } else { 257 set = 0; 258 mask = AT803X_BT_BX_REG_SEL; 259 } 260 261 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 262 } 263 264 static int at803x_read_page(struct phy_device *phydev) 265 { 266 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 267 268 if (ccr < 0) 269 return ccr; 270 271 if (ccr & AT803X_BT_BX_REG_SEL) 272 return AT803X_PAGE_COPPER; 273 274 return AT803X_PAGE_FIBER; 275 } 276 277 static int at803x_enable_rx_delay(struct phy_device *phydev) 278 { 279 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 280 AT803X_DEBUG_RX_CLK_DLY_EN); 281 } 282 283 static int at803x_enable_tx_delay(struct phy_device *phydev) 284 { 285 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 286 AT803X_DEBUG_TX_CLK_DLY_EN); 287 } 288 289 static int at803x_disable_rx_delay(struct phy_device *phydev) 290 { 291 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 292 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 293 } 294 295 static int at803x_disable_tx_delay(struct phy_device *phydev) 296 { 297 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 298 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 299 } 300 301 /* save relevant PHY registers to private copy */ 302 static void at803x_context_save(struct phy_device *phydev, 303 struct at803x_context *context) 304 { 305 context->bmcr = phy_read(phydev, MII_BMCR); 306 context->advertise = phy_read(phydev, MII_ADVERTISE); 307 context->control1000 = phy_read(phydev, MII_CTRL1000); 308 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 309 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 310 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 311 } 312 313 /* restore relevant PHY registers from private copy */ 314 static void at803x_context_restore(struct phy_device *phydev, 315 const struct at803x_context *context) 316 { 317 phy_write(phydev, MII_BMCR, context->bmcr); 318 phy_write(phydev, MII_ADVERTISE, context->advertise); 319 phy_write(phydev, MII_CTRL1000, context->control1000); 320 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 321 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 322 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 323 } 324 325 static int at803x_set_wol(struct phy_device *phydev, 326 struct ethtool_wolinfo *wol) 327 { 328 struct net_device *ndev = phydev->attached_dev; 329 const u8 *mac; 330 int ret; 331 u32 value; 332 unsigned int i, offsets[] = { 333 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 334 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 335 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 336 }; 337 338 if (!ndev) 339 return -ENODEV; 340 341 if (wol->wolopts & WAKE_MAGIC) { 342 mac = (const u8 *) ndev->dev_addr; 343 344 if (!is_valid_ether_addr(mac)) 345 return -EINVAL; 346 347 for (i = 0; i < 3; i++) 348 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 349 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 350 351 value = phy_read(phydev, AT803X_INTR_ENABLE); 352 value |= AT803X_INTR_ENABLE_WOL; 353 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 354 if (ret) 355 return ret; 356 value = phy_read(phydev, AT803X_INTR_STATUS); 357 } else { 358 value = phy_read(phydev, AT803X_INTR_ENABLE); 359 value &= (~AT803X_INTR_ENABLE_WOL); 360 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 361 if (ret) 362 return ret; 363 value = phy_read(phydev, AT803X_INTR_STATUS); 364 } 365 366 return ret; 367 } 368 369 static void at803x_get_wol(struct phy_device *phydev, 370 struct ethtool_wolinfo *wol) 371 { 372 u32 value; 373 374 wol->supported = WAKE_MAGIC; 375 wol->wolopts = 0; 376 377 value = phy_read(phydev, AT803X_INTR_ENABLE); 378 if (value & AT803X_INTR_ENABLE_WOL) 379 wol->wolopts |= WAKE_MAGIC; 380 } 381 382 static int at803x_get_sset_count(struct phy_device *phydev) 383 { 384 return ARRAY_SIZE(at803x_hw_stats); 385 } 386 387 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 388 { 389 int i; 390 391 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 392 strscpy(data + i * ETH_GSTRING_LEN, 393 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 394 } 395 } 396 397 static u64 at803x_get_stat(struct phy_device *phydev, int i) 398 { 399 struct at803x_hw_stat stat = at803x_hw_stats[i]; 400 struct at803x_priv *priv = phydev->priv; 401 int val; 402 u64 ret; 403 404 if (stat.access_type == MMD) 405 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 406 else 407 val = phy_read(phydev, stat.reg); 408 409 if (val < 0) { 410 ret = U64_MAX; 411 } else { 412 val = val & stat.mask; 413 priv->stats[i] += val; 414 ret = priv->stats[i]; 415 } 416 417 return ret; 418 } 419 420 static void at803x_get_stats(struct phy_device *phydev, 421 struct ethtool_stats *stats, u64 *data) 422 { 423 int i; 424 425 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 426 data[i] = at803x_get_stat(phydev, i); 427 } 428 429 static int at803x_suspend(struct phy_device *phydev) 430 { 431 int value; 432 int wol_enabled; 433 434 value = phy_read(phydev, AT803X_INTR_ENABLE); 435 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 436 437 if (wol_enabled) 438 value = BMCR_ISOLATE; 439 else 440 value = BMCR_PDOWN; 441 442 phy_modify(phydev, MII_BMCR, 0, value); 443 444 return 0; 445 } 446 447 static int at803x_resume(struct phy_device *phydev) 448 { 449 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 450 } 451 452 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 453 unsigned int selector) 454 { 455 struct phy_device *phydev = rdev_get_drvdata(rdev); 456 457 if (selector) 458 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 459 0, AT803X_DEBUG_RGMII_1V8); 460 else 461 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 462 AT803X_DEBUG_RGMII_1V8, 0); 463 } 464 465 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 466 { 467 struct phy_device *phydev = rdev_get_drvdata(rdev); 468 int val; 469 470 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 471 if (val < 0) 472 return val; 473 474 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 475 } 476 477 static const struct regulator_ops vddio_regulator_ops = { 478 .list_voltage = regulator_list_voltage_table, 479 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 480 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 481 }; 482 483 static const unsigned int vddio_voltage_table[] = { 484 1500000, 485 1800000, 486 }; 487 488 static const struct regulator_desc vddio_desc = { 489 .name = "vddio", 490 .of_match = of_match_ptr("vddio-regulator"), 491 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 492 .volt_table = vddio_voltage_table, 493 .ops = &vddio_regulator_ops, 494 .type = REGULATOR_VOLTAGE, 495 .owner = THIS_MODULE, 496 }; 497 498 static const struct regulator_ops vddh_regulator_ops = { 499 }; 500 501 static const struct regulator_desc vddh_desc = { 502 .name = "vddh", 503 .of_match = of_match_ptr("vddh-regulator"), 504 .n_voltages = 1, 505 .fixed_uV = 2500000, 506 .ops = &vddh_regulator_ops, 507 .type = REGULATOR_VOLTAGE, 508 .owner = THIS_MODULE, 509 }; 510 511 static int at8031_register_regulators(struct phy_device *phydev) 512 { 513 struct at803x_priv *priv = phydev->priv; 514 struct device *dev = &phydev->mdio.dev; 515 struct regulator_config config = { }; 516 517 config.dev = dev; 518 config.driver_data = phydev; 519 520 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 521 if (IS_ERR(priv->vddio_rdev)) { 522 phydev_err(phydev, "failed to register VDDIO regulator\n"); 523 return PTR_ERR(priv->vddio_rdev); 524 } 525 526 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 527 if (IS_ERR(priv->vddh_rdev)) { 528 phydev_err(phydev, "failed to register VDDH regulator\n"); 529 return PTR_ERR(priv->vddh_rdev); 530 } 531 532 return 0; 533 } 534 535 static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) 536 { 537 return (phydev->phy_id & phydev->drv->phy_id_mask) 538 == (phy_id & phydev->drv->phy_id_mask); 539 } 540 541 static int at803x_parse_dt(struct phy_device *phydev) 542 { 543 struct device_node *node = phydev->mdio.dev.of_node; 544 struct at803x_priv *priv = phydev->priv; 545 u32 freq, strength, tw; 546 unsigned int sel; 547 int ret; 548 549 if (!IS_ENABLED(CONFIG_OF_MDIO)) 550 return 0; 551 552 if (of_property_read_bool(node, "qca,disable-smarteee")) 553 priv->flags |= AT803X_DISABLE_SMARTEEE; 554 555 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 556 if (!tw || tw > 255) { 557 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 558 return -EINVAL; 559 } 560 priv->smarteee_lpi_tw_1g = tw; 561 } 562 563 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 564 if (!tw || tw > 255) { 565 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 566 return -EINVAL; 567 } 568 priv->smarteee_lpi_tw_100m = tw; 569 } 570 571 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 572 if (!ret) { 573 switch (freq) { 574 case 25000000: 575 sel = AT803X_CLK_OUT_25MHZ_XTAL; 576 break; 577 case 50000000: 578 sel = AT803X_CLK_OUT_50MHZ_PLL; 579 break; 580 case 62500000: 581 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 582 break; 583 case 125000000: 584 sel = AT803X_CLK_OUT_125MHZ_PLL; 585 break; 586 default: 587 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 588 return -EINVAL; 589 } 590 591 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 592 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 593 594 /* Fixup for the AR8030/AR8035. This chip has another mask and 595 * doesn't support the DSP reference. Eg. the lowest bit of the 596 * mask. The upper two bits select the same frequencies. Mask 597 * the lowest bit here. 598 * 599 * Warning: 600 * There was no datasheet for the AR8030 available so this is 601 * just a guess. But the AR8035 is listed as pin compatible 602 * to the AR8030 so there might be a good chance it works on 603 * the AR8030 too. 604 */ 605 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || 606 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { 607 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 608 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 609 } 610 } 611 612 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 613 if (!ret) { 614 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 615 switch (strength) { 616 case AR803X_STRENGTH_FULL: 617 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 618 break; 619 case AR803X_STRENGTH_HALF: 620 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 621 break; 622 case AR803X_STRENGTH_QUARTER: 623 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 624 break; 625 default: 626 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 627 return -EINVAL; 628 } 629 } 630 631 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 632 * options. 633 */ 634 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 635 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 636 priv->flags |= AT803X_KEEP_PLL_ENABLED; 637 638 ret = at8031_register_regulators(phydev); 639 if (ret < 0) 640 return ret; 641 642 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 643 "vddio"); 644 if (IS_ERR(priv->vddio)) { 645 phydev_err(phydev, "failed to get VDDIO regulator\n"); 646 return PTR_ERR(priv->vddio); 647 } 648 } 649 650 return 0; 651 } 652 653 static int at803x_probe(struct phy_device *phydev) 654 { 655 struct device *dev = &phydev->mdio.dev; 656 struct at803x_priv *priv; 657 int ret; 658 659 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 660 if (!priv) 661 return -ENOMEM; 662 663 phydev->priv = priv; 664 665 ret = at803x_parse_dt(phydev); 666 if (ret) 667 return ret; 668 669 if (priv->vddio) { 670 ret = regulator_enable(priv->vddio); 671 if (ret < 0) 672 return ret; 673 } 674 675 /* Some bootloaders leave the fiber page selected. 676 * Switch to the copper page, as otherwise we read 677 * the PHY capabilities from the fiber side. 678 */ 679 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 680 phy_lock_mdio_bus(phydev); 681 ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); 682 phy_unlock_mdio_bus(phydev); 683 if (ret) 684 goto err; 685 } 686 687 return 0; 688 689 err: 690 if (priv->vddio) 691 regulator_disable(priv->vddio); 692 693 return ret; 694 } 695 696 static void at803x_remove(struct phy_device *phydev) 697 { 698 struct at803x_priv *priv = phydev->priv; 699 700 if (priv->vddio) 701 regulator_disable(priv->vddio); 702 } 703 704 static int at803x_smarteee_config(struct phy_device *phydev) 705 { 706 struct at803x_priv *priv = phydev->priv; 707 u16 mask = 0, val = 0; 708 int ret; 709 710 if (priv->flags & AT803X_DISABLE_SMARTEEE) 711 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 712 AT803X_MMD3_SMARTEEE_CTL3, 713 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 714 715 if (priv->smarteee_lpi_tw_1g) { 716 mask |= 0xff00; 717 val |= priv->smarteee_lpi_tw_1g << 8; 718 } 719 if (priv->smarteee_lpi_tw_100m) { 720 mask |= 0x00ff; 721 val |= priv->smarteee_lpi_tw_100m; 722 } 723 if (!mask) 724 return 0; 725 726 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 727 mask, val); 728 if (ret) 729 return ret; 730 731 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 732 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 733 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 734 } 735 736 static int at803x_clk_out_config(struct phy_device *phydev) 737 { 738 struct at803x_priv *priv = phydev->priv; 739 740 if (!priv->clk_25m_mask) 741 return 0; 742 743 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 744 priv->clk_25m_mask, priv->clk_25m_reg); 745 } 746 747 static int at8031_pll_config(struct phy_device *phydev) 748 { 749 struct at803x_priv *priv = phydev->priv; 750 751 /* The default after hardware reset is PLL OFF. After a soft reset, the 752 * values are retained. 753 */ 754 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 755 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 756 0, AT803X_DEBUG_PLL_ON); 757 else 758 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 759 AT803X_DEBUG_PLL_ON, 0); 760 } 761 762 static int at803x_config_init(struct phy_device *phydev) 763 { 764 int ret; 765 766 /* The RX and TX delay default is: 767 * after HW reset: RX delay enabled and TX delay disabled 768 * after SW reset: RX delay enabled, while TX delay retains the 769 * value before reset. 770 */ 771 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 772 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 773 ret = at803x_enable_rx_delay(phydev); 774 else 775 ret = at803x_disable_rx_delay(phydev); 776 if (ret < 0) 777 return ret; 778 779 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 780 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 781 ret = at803x_enable_tx_delay(phydev); 782 else 783 ret = at803x_disable_tx_delay(phydev); 784 if (ret < 0) 785 return ret; 786 787 ret = at803x_smarteee_config(phydev); 788 if (ret < 0) 789 return ret; 790 791 ret = at803x_clk_out_config(phydev); 792 if (ret < 0) 793 return ret; 794 795 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 796 ret = at8031_pll_config(phydev); 797 if (ret < 0) 798 return ret; 799 } 800 801 /* Ar803x extended next page bit is enabled by default. Cisco 802 * multigig switches read this bit and attempt to negotiate 10Gbps 803 * rates even if the next page bit is disabled. This is incorrect 804 * behaviour but we still need to accommodate it. XNP is only needed 805 * for 10Gbps support, so disable XNP. 806 */ 807 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 808 } 809 810 static int at803x_ack_interrupt(struct phy_device *phydev) 811 { 812 int err; 813 814 err = phy_read(phydev, AT803X_INTR_STATUS); 815 816 return (err < 0) ? err : 0; 817 } 818 819 static int at803x_config_intr(struct phy_device *phydev) 820 { 821 int err; 822 int value; 823 824 value = phy_read(phydev, AT803X_INTR_ENABLE); 825 826 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 827 /* Clear any pending interrupts */ 828 err = at803x_ack_interrupt(phydev); 829 if (err) 830 return err; 831 832 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 833 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 834 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 835 value |= AT803X_INTR_ENABLE_LINK_FAIL; 836 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 837 838 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 839 } else { 840 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 841 if (err) 842 return err; 843 844 /* Clear any pending interrupts */ 845 err = at803x_ack_interrupt(phydev); 846 } 847 848 return err; 849 } 850 851 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 852 { 853 int irq_status, int_enabled; 854 855 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 856 if (irq_status < 0) { 857 phy_error(phydev); 858 return IRQ_NONE; 859 } 860 861 /* Read the current enabled interrupts */ 862 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 863 if (int_enabled < 0) { 864 phy_error(phydev); 865 return IRQ_NONE; 866 } 867 868 /* See if this was one of our enabled interrupts */ 869 if (!(irq_status & int_enabled)) 870 return IRQ_NONE; 871 872 phy_trigger_machine(phydev); 873 874 return IRQ_HANDLED; 875 } 876 877 static void at803x_link_change_notify(struct phy_device *phydev) 878 { 879 /* 880 * Conduct a hardware reset for AT8030 every time a link loss is 881 * signalled. This is necessary to circumvent a hardware bug that 882 * occurs when the cable is unplugged while TX packets are pending 883 * in the FIFO. In such cases, the FIFO enters an error mode it 884 * cannot recover from by software. 885 */ 886 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 887 struct at803x_context context; 888 889 at803x_context_save(phydev, &context); 890 891 phy_device_reset(phydev, 1); 892 msleep(1); 893 phy_device_reset(phydev, 0); 894 msleep(1); 895 896 at803x_context_restore(phydev, &context); 897 898 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 899 } 900 } 901 902 static int at803x_read_status(struct phy_device *phydev) 903 { 904 int ss, err, old_link = phydev->link; 905 906 /* Update the link, but return if there was an error */ 907 err = genphy_update_link(phydev); 908 if (err) 909 return err; 910 911 /* why bother the PHY if nothing can have changed */ 912 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 913 return 0; 914 915 phydev->speed = SPEED_UNKNOWN; 916 phydev->duplex = DUPLEX_UNKNOWN; 917 phydev->pause = 0; 918 phydev->asym_pause = 0; 919 920 err = genphy_read_lpa(phydev); 921 if (err < 0) 922 return err; 923 924 /* Read the AT8035 PHY-Specific Status register, which indicates the 925 * speed and duplex that the PHY is actually using, irrespective of 926 * whether we are in autoneg mode or not. 927 */ 928 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 929 if (ss < 0) 930 return ss; 931 932 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 933 int sfc; 934 935 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 936 if (sfc < 0) 937 return sfc; 938 939 switch (ss & AT803X_SS_SPEED_MASK) { 940 case AT803X_SS_SPEED_10: 941 phydev->speed = SPEED_10; 942 break; 943 case AT803X_SS_SPEED_100: 944 phydev->speed = SPEED_100; 945 break; 946 case AT803X_SS_SPEED_1000: 947 phydev->speed = SPEED_1000; 948 break; 949 } 950 if (ss & AT803X_SS_DUPLEX) 951 phydev->duplex = DUPLEX_FULL; 952 else 953 phydev->duplex = DUPLEX_HALF; 954 955 if (ss & AT803X_SS_MDIX) 956 phydev->mdix = ETH_TP_MDI_X; 957 else 958 phydev->mdix = ETH_TP_MDI; 959 960 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 961 case AT803X_SFC_MANUAL_MDI: 962 phydev->mdix_ctrl = ETH_TP_MDI; 963 break; 964 case AT803X_SFC_MANUAL_MDIX: 965 phydev->mdix_ctrl = ETH_TP_MDI_X; 966 break; 967 case AT803X_SFC_AUTOMATIC_CROSSOVER: 968 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 969 break; 970 } 971 } 972 973 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 974 phy_resolve_aneg_pause(phydev); 975 976 return 0; 977 } 978 979 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 980 { 981 u16 val; 982 983 switch (ctrl) { 984 case ETH_TP_MDI: 985 val = AT803X_SFC_MANUAL_MDI; 986 break; 987 case ETH_TP_MDI_X: 988 val = AT803X_SFC_MANUAL_MDIX; 989 break; 990 case ETH_TP_MDI_AUTO: 991 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 992 break; 993 default: 994 return 0; 995 } 996 997 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 998 AT803X_SFC_MDI_CROSSOVER_MODE_M, 999 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1000 } 1001 1002 static int at803x_config_aneg(struct phy_device *phydev) 1003 { 1004 int ret; 1005 1006 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1007 if (ret < 0) 1008 return ret; 1009 1010 /* Changes of the midx bits are disruptive to the normal operation; 1011 * therefore any changes to these registers must be followed by a 1012 * software reset to take effect. 1013 */ 1014 if (ret == 1) { 1015 ret = genphy_soft_reset(phydev); 1016 if (ret < 0) 1017 return ret; 1018 } 1019 1020 return genphy_config_aneg(phydev); 1021 } 1022 1023 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1024 { 1025 int val; 1026 1027 val = phy_read(phydev, AT803X_SMART_SPEED); 1028 if (val < 0) 1029 return val; 1030 1031 if (val & AT803X_SMART_SPEED_ENABLE) 1032 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1033 else 1034 *d = DOWNSHIFT_DEV_DISABLE; 1035 1036 return 0; 1037 } 1038 1039 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1040 { 1041 u16 mask, set; 1042 int ret; 1043 1044 switch (cnt) { 1045 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1046 cnt = AT803X_DEFAULT_DOWNSHIFT; 1047 fallthrough; 1048 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1049 set = AT803X_SMART_SPEED_ENABLE | 1050 AT803X_SMART_SPEED_BYPASS_TIMER | 1051 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1052 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1053 break; 1054 case DOWNSHIFT_DEV_DISABLE: 1055 set = 0; 1056 mask = AT803X_SMART_SPEED_ENABLE | 1057 AT803X_SMART_SPEED_BYPASS_TIMER; 1058 break; 1059 default: 1060 return -EINVAL; 1061 } 1062 1063 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1064 1065 /* After changing the smart speed settings, we need to perform a 1066 * software reset, use phy_init_hw() to make sure we set the 1067 * reapply any values which might got lost during software reset. 1068 */ 1069 if (ret == 1) 1070 ret = phy_init_hw(phydev); 1071 1072 return ret; 1073 } 1074 1075 static int at803x_get_tunable(struct phy_device *phydev, 1076 struct ethtool_tunable *tuna, void *data) 1077 { 1078 switch (tuna->id) { 1079 case ETHTOOL_PHY_DOWNSHIFT: 1080 return at803x_get_downshift(phydev, data); 1081 default: 1082 return -EOPNOTSUPP; 1083 } 1084 } 1085 1086 static int at803x_set_tunable(struct phy_device *phydev, 1087 struct ethtool_tunable *tuna, const void *data) 1088 { 1089 switch (tuna->id) { 1090 case ETHTOOL_PHY_DOWNSHIFT: 1091 return at803x_set_downshift(phydev, *(const u8 *)data); 1092 default: 1093 return -EOPNOTSUPP; 1094 } 1095 } 1096 1097 static int at803x_cable_test_result_trans(u16 status) 1098 { 1099 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1100 case AT803X_CDT_STATUS_STAT_NORMAL: 1101 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1102 case AT803X_CDT_STATUS_STAT_SHORT: 1103 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1104 case AT803X_CDT_STATUS_STAT_OPEN: 1105 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1106 case AT803X_CDT_STATUS_STAT_FAIL: 1107 default: 1108 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1109 } 1110 } 1111 1112 static bool at803x_cdt_test_failed(u16 status) 1113 { 1114 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1115 AT803X_CDT_STATUS_STAT_FAIL; 1116 } 1117 1118 static bool at803x_cdt_fault_length_valid(u16 status) 1119 { 1120 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1121 case AT803X_CDT_STATUS_STAT_OPEN: 1122 case AT803X_CDT_STATUS_STAT_SHORT: 1123 return true; 1124 } 1125 return false; 1126 } 1127 1128 static int at803x_cdt_fault_length(u16 status) 1129 { 1130 int dt; 1131 1132 /* According to the datasheet the distance to the fault is 1133 * DELTA_TIME * 0.824 meters. 1134 * 1135 * The author suspect the correct formula is: 1136 * 1137 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1138 * 1139 * where c is the speed of light, VF is the velocity factor of 1140 * the twisted pair cable, 125MHz the counter frequency and 1141 * we need to divide by 2 because the hardware will measure the 1142 * round trip time to the fault and back to the PHY. 1143 * 1144 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1145 * datasheet. 1146 */ 1147 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1148 1149 return (dt * 824) / 10; 1150 } 1151 1152 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1153 { 1154 u16 cdt; 1155 1156 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1157 AT803X_CDT_ENABLE_TEST; 1158 1159 return phy_write(phydev, AT803X_CDT, cdt); 1160 } 1161 1162 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1163 { 1164 int val, ret; 1165 1166 /* One test run takes about 25ms */ 1167 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1168 !(val & AT803X_CDT_ENABLE_TEST), 1169 30000, 100000, true); 1170 1171 return ret < 0 ? ret : 0; 1172 } 1173 1174 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1175 { 1176 static const int ethtool_pair[] = { 1177 ETHTOOL_A_CABLE_PAIR_A, 1178 ETHTOOL_A_CABLE_PAIR_B, 1179 ETHTOOL_A_CABLE_PAIR_C, 1180 ETHTOOL_A_CABLE_PAIR_D, 1181 }; 1182 int ret, val; 1183 1184 ret = at803x_cdt_start(phydev, pair); 1185 if (ret) 1186 return ret; 1187 1188 ret = at803x_cdt_wait_for_completion(phydev); 1189 if (ret) 1190 return ret; 1191 1192 val = phy_read(phydev, AT803X_CDT_STATUS); 1193 if (val < 0) 1194 return val; 1195 1196 if (at803x_cdt_test_failed(val)) 1197 return 0; 1198 1199 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1200 at803x_cable_test_result_trans(val)); 1201 1202 if (at803x_cdt_fault_length_valid(val)) 1203 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1204 at803x_cdt_fault_length(val)); 1205 1206 return 1; 1207 } 1208 1209 static int at803x_cable_test_get_status(struct phy_device *phydev, 1210 bool *finished) 1211 { 1212 unsigned long pair_mask; 1213 int retries = 20; 1214 int pair, ret; 1215 1216 if (phydev->phy_id == ATH9331_PHY_ID || 1217 phydev->phy_id == ATH8032_PHY_ID) 1218 pair_mask = 0x3; 1219 else 1220 pair_mask = 0xf; 1221 1222 *finished = false; 1223 1224 /* According to the datasheet the CDT can be performed when 1225 * there is no link partner or when the link partner is 1226 * auto-negotiating. Starting the test will restart the AN 1227 * automatically. It seems that doing this repeatedly we will 1228 * get a slot where our link partner won't disturb our 1229 * measurement. 1230 */ 1231 while (pair_mask && retries--) { 1232 for_each_set_bit(pair, &pair_mask, 4) { 1233 ret = at803x_cable_test_one_pair(phydev, pair); 1234 if (ret < 0) 1235 return ret; 1236 if (ret) 1237 clear_bit(pair, &pair_mask); 1238 } 1239 if (pair_mask) 1240 msleep(250); 1241 } 1242 1243 *finished = true; 1244 1245 return 0; 1246 } 1247 1248 static int at803x_cable_test_start(struct phy_device *phydev) 1249 { 1250 /* Enable auto-negotiation, but advertise no capabilities, no link 1251 * will be established. A restart of the auto-negotiation is not 1252 * required, because the cable test will automatically break the link. 1253 */ 1254 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1255 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1256 if (phydev->phy_id != ATH9331_PHY_ID && 1257 phydev->phy_id != ATH8032_PHY_ID) 1258 phy_write(phydev, MII_CTRL1000, 0); 1259 1260 /* we do all the (time consuming) work later */ 1261 return 0; 1262 } 1263 1264 static int qca83xx_config_init(struct phy_device *phydev) 1265 { 1266 u8 switch_revision; 1267 1268 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1269 1270 switch (switch_revision) { 1271 case 1: 1272 /* For 100M waveform */ 1273 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea); 1274 /* Turn on Gigabit clock */ 1275 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0); 1276 break; 1277 1278 case 2: 1279 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1280 fallthrough; 1281 case 4: 1282 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1283 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860); 1284 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46); 1285 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1286 break; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static struct phy_driver at803x_driver[] = { 1293 { 1294 /* Qualcomm Atheros AR8035 */ 1295 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1296 .name = "Qualcomm Atheros AR8035", 1297 .flags = PHY_POLL_CABLE_TEST, 1298 .probe = at803x_probe, 1299 .remove = at803x_remove, 1300 .config_aneg = at803x_config_aneg, 1301 .config_init = at803x_config_init, 1302 .soft_reset = genphy_soft_reset, 1303 .set_wol = at803x_set_wol, 1304 .get_wol = at803x_get_wol, 1305 .suspend = at803x_suspend, 1306 .resume = at803x_resume, 1307 /* PHY_GBIT_FEATURES */ 1308 .read_status = at803x_read_status, 1309 .config_intr = at803x_config_intr, 1310 .handle_interrupt = at803x_handle_interrupt, 1311 .get_tunable = at803x_get_tunable, 1312 .set_tunable = at803x_set_tunable, 1313 .cable_test_start = at803x_cable_test_start, 1314 .cable_test_get_status = at803x_cable_test_get_status, 1315 }, { 1316 /* Qualcomm Atheros AR8030 */ 1317 .phy_id = ATH8030_PHY_ID, 1318 .name = "Qualcomm Atheros AR8030", 1319 .phy_id_mask = AT8030_PHY_ID_MASK, 1320 .probe = at803x_probe, 1321 .remove = at803x_remove, 1322 .config_init = at803x_config_init, 1323 .link_change_notify = at803x_link_change_notify, 1324 .set_wol = at803x_set_wol, 1325 .get_wol = at803x_get_wol, 1326 .suspend = at803x_suspend, 1327 .resume = at803x_resume, 1328 /* PHY_BASIC_FEATURES */ 1329 .config_intr = at803x_config_intr, 1330 .handle_interrupt = at803x_handle_interrupt, 1331 }, { 1332 /* Qualcomm Atheros AR8031/AR8033 */ 1333 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1334 .name = "Qualcomm Atheros AR8031/AR8033", 1335 .flags = PHY_POLL_CABLE_TEST, 1336 .probe = at803x_probe, 1337 .remove = at803x_remove, 1338 .config_init = at803x_config_init, 1339 .config_aneg = at803x_config_aneg, 1340 .soft_reset = genphy_soft_reset, 1341 .set_wol = at803x_set_wol, 1342 .get_wol = at803x_get_wol, 1343 .suspend = at803x_suspend, 1344 .resume = at803x_resume, 1345 .read_page = at803x_read_page, 1346 .write_page = at803x_write_page, 1347 /* PHY_GBIT_FEATURES */ 1348 .read_status = at803x_read_status, 1349 .config_intr = &at803x_config_intr, 1350 .handle_interrupt = at803x_handle_interrupt, 1351 .get_tunable = at803x_get_tunable, 1352 .set_tunable = at803x_set_tunable, 1353 .cable_test_start = at803x_cable_test_start, 1354 .cable_test_get_status = at803x_cable_test_get_status, 1355 }, { 1356 /* Qualcomm Atheros AR8032 */ 1357 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1358 .name = "Qualcomm Atheros AR8032", 1359 .probe = at803x_probe, 1360 .remove = at803x_remove, 1361 .flags = PHY_POLL_CABLE_TEST, 1362 .config_init = at803x_config_init, 1363 .link_change_notify = at803x_link_change_notify, 1364 .set_wol = at803x_set_wol, 1365 .get_wol = at803x_get_wol, 1366 .suspend = at803x_suspend, 1367 .resume = at803x_resume, 1368 /* PHY_BASIC_FEATURES */ 1369 .config_intr = at803x_config_intr, 1370 .handle_interrupt = at803x_handle_interrupt, 1371 .cable_test_start = at803x_cable_test_start, 1372 .cable_test_get_status = at803x_cable_test_get_status, 1373 }, { 1374 /* ATHEROS AR9331 */ 1375 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1376 .name = "Qualcomm Atheros AR9331 built-in PHY", 1377 .suspend = at803x_suspend, 1378 .resume = at803x_resume, 1379 .flags = PHY_POLL_CABLE_TEST, 1380 /* PHY_BASIC_FEATURES */ 1381 .config_intr = &at803x_config_intr, 1382 .handle_interrupt = at803x_handle_interrupt, 1383 .cable_test_start = at803x_cable_test_start, 1384 .cable_test_get_status = at803x_cable_test_get_status, 1385 .read_status = at803x_read_status, 1386 .soft_reset = genphy_soft_reset, 1387 .config_aneg = at803x_config_aneg, 1388 }, { 1389 /* QCA8337 */ 1390 .phy_id = QCA8337_PHY_ID, 1391 .phy_id_mask = QCA8K_PHY_ID_MASK, 1392 .name = "QCA PHY 8337", 1393 /* PHY_GBIT_FEATURES */ 1394 .probe = at803x_probe, 1395 .flags = PHY_IS_INTERNAL, 1396 .config_init = qca83xx_config_init, 1397 .soft_reset = genphy_soft_reset, 1398 .get_sset_count = at803x_get_sset_count, 1399 .get_strings = at803x_get_strings, 1400 .get_stats = at803x_get_stats, 1401 }, }; 1402 1403 module_phy_driver(at803x_driver); 1404 1405 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1406 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1407 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1408 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1409 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1410 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1411 { } 1412 }; 1413 1414 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1415