1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/bitfield.h> 17 #include <linux/regulator/of_regulator.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/of.h> 21 #include <linux/phylink.h> 22 #include <linux/sfp.h> 23 #include <dt-bindings/net/qca-ar803x.h> 24 25 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 26 #define AT803X_SFC_ASSERT_CRS BIT(11) 27 #define AT803X_SFC_FORCE_LINK BIT(10) 28 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 29 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 30 #define AT803X_SFC_MANUAL_MDIX 0x1 31 #define AT803X_SFC_MANUAL_MDI 0x0 32 #define AT803X_SFC_SQE_TEST BIT(2) 33 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 34 #define AT803X_SFC_DISABLE_JABBER BIT(0) 35 36 #define AT803X_SPECIFIC_STATUS 0x11 37 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 38 #define AT803X_SS_SPEED_1000 2 39 #define AT803X_SS_SPEED_100 1 40 #define AT803X_SS_SPEED_10 0 41 #define AT803X_SS_DUPLEX BIT(13) 42 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 43 #define AT803X_SS_MDIX BIT(6) 44 45 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 46 #define QCA808X_SS_SPEED_2500 4 47 48 #define AT803X_INTR_ENABLE 0x12 49 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 50 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 51 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 52 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 53 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 54 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 55 #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 56 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 57 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 58 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 59 #define AT803X_INTR_ENABLE_WOL BIT(0) 60 61 #define AT803X_INTR_STATUS 0x13 62 63 #define AT803X_SMART_SPEED 0x14 64 #define AT803X_SMART_SPEED_ENABLE BIT(5) 65 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 66 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 67 #define AT803X_CDT 0x16 68 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 69 #define AT803X_CDT_ENABLE_TEST BIT(0) 70 #define AT803X_CDT_STATUS 0x1c 71 #define AT803X_CDT_STATUS_STAT_NORMAL 0 72 #define AT803X_CDT_STATUS_STAT_SHORT 1 73 #define AT803X_CDT_STATUS_STAT_OPEN 2 74 #define AT803X_CDT_STATUS_STAT_FAIL 3 75 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 76 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 77 #define AT803X_LED_CONTROL 0x18 78 79 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 80 #define AT803X_WOL_EN BIT(5) 81 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 82 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 83 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 84 #define AT803X_REG_CHIP_CONFIG 0x1f 85 #define AT803X_BT_BX_REG_SEL 0x8000 86 87 #define AT803X_DEBUG_ADDR 0x1D 88 #define AT803X_DEBUG_DATA 0x1E 89 90 #define AT803X_MODE_CFG_MASK 0x0F 91 #define AT803X_MODE_CFG_BASET_RGMII 0x00 92 #define AT803X_MODE_CFG_BASET_SGMII 0x01 93 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 94 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 95 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 96 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 97 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 98 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 99 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 100 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 101 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 102 103 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 104 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 105 106 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 107 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 108 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 109 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 110 111 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 112 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 113 114 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 115 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 116 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 117 #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) 118 119 #define AT803X_DEBUG_REG_3C 0x3C 120 121 #define AT803X_DEBUG_REG_GREEN 0x3D 122 #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 123 124 #define AT803X_DEBUG_REG_1F 0x1F 125 #define AT803X_DEBUG_PLL_ON BIT(2) 126 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 127 128 #define MDIO_AZ_DEBUG 0x800D 129 130 /* AT803x supports either the XTAL input pad, an internal PLL or the 131 * DSP as clock reference for the clock output pad. The XTAL reference 132 * is only used for 25 MHz output, all other frequencies need the PLL. 133 * The DSP as a clock reference is used in synchronous ethernet 134 * applications. 135 * 136 * By default the PLL is only enabled if there is a link. Otherwise 137 * the PHY will go into low power state and disabled the PLL. You can 138 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 139 * enabled. 140 */ 141 #define AT803X_MMD7_CLK25M 0x8016 142 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 143 #define AT803X_CLK_OUT_25MHZ_XTAL 0 144 #define AT803X_CLK_OUT_25MHZ_DSP 1 145 #define AT803X_CLK_OUT_50MHZ_PLL 2 146 #define AT803X_CLK_OUT_50MHZ_DSP 3 147 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 148 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 149 #define AT803X_CLK_OUT_125MHZ_PLL 6 150 #define AT803X_CLK_OUT_125MHZ_DSP 7 151 152 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 153 * but doesn't support choosing between XTAL/PLL and DSP. 154 */ 155 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 156 157 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 158 #define AT803X_CLK_OUT_STRENGTH_FULL 0 159 #define AT803X_CLK_OUT_STRENGTH_HALF 1 160 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 161 162 #define AT803X_DEFAULT_DOWNSHIFT 5 163 #define AT803X_MIN_DOWNSHIFT 2 164 #define AT803X_MAX_DOWNSHIFT 9 165 166 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 167 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 168 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 169 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 170 171 #define ATH9331_PHY_ID 0x004dd041 172 #define ATH8030_PHY_ID 0x004dd076 173 #define ATH8031_PHY_ID 0x004dd074 174 #define ATH8032_PHY_ID 0x004dd023 175 #define ATH8035_PHY_ID 0x004dd072 176 #define AT8030_PHY_ID_MASK 0xffffffef 177 178 #define QCA8081_PHY_ID 0x004dd101 179 180 #define QCA8327_A_PHY_ID 0x004dd033 181 #define QCA8327_B_PHY_ID 0x004dd034 182 #define QCA8337_PHY_ID 0x004dd036 183 #define QCA9561_PHY_ID 0x004dd042 184 #define QCA8K_PHY_ID_MASK 0xffffffff 185 186 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 187 188 #define AT803X_PAGE_FIBER 0 189 #define AT803X_PAGE_COPPER 1 190 191 /* don't turn off internal PLL */ 192 #define AT803X_KEEP_PLL_ENABLED BIT(0) 193 #define AT803X_DISABLE_SMARTEEE BIT(1) 194 195 /* disable hibernation mode */ 196 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 197 198 /* ADC threshold */ 199 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 200 #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 201 #define QCA808X_ADC_THRESHOLD_80MV 0 202 #define QCA808X_ADC_THRESHOLD_100MV 0xf0 203 #define QCA808X_ADC_THRESHOLD_200MV 0x0f 204 #define QCA808X_ADC_THRESHOLD_300MV 0xff 205 206 /* CLD control */ 207 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 208 #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 209 #define QCA808X_8023AZ_AFE_EN 0x90 210 211 /* AZ control */ 212 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 213 #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 214 215 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 216 #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 217 218 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 219 #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 220 221 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 222 #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 223 224 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 225 #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 226 227 #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 228 #define QCA808X_TOP_OPTION1_DATA 0x0 229 230 #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 231 #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 232 #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 233 #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 234 #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 235 #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 236 #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 237 #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 238 #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 239 #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 240 #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 241 #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 242 243 /* master/slave seed config */ 244 #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 245 #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 246 #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 247 #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 248 249 /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 250 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 251 */ 252 #define QCA808X_DBG_AN_TEST 0xb 253 #define QCA808X_HIBERNATION_EN BIT(15) 254 255 #define QCA808X_CDT_ENABLE_TEST BIT(15) 256 #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 257 #define QCA808X_CDT_LENGTH_UNIT BIT(10) 258 259 #define QCA808X_MMD3_CDT_STATUS 0x8064 260 #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 261 #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 262 #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 263 #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 264 #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 265 266 #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 267 #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 268 #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 269 #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 270 #define QCA808X_CDT_STATUS_STAT_FAIL 0 271 #define QCA808X_CDT_STATUS_STAT_NORMAL 1 272 #define QCA808X_CDT_STATUS_STAT_OPEN 2 273 #define QCA808X_CDT_STATUS_STAT_SHORT 3 274 275 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 276 MODULE_AUTHOR("Matus Ujhelyi"); 277 MODULE_LICENSE("GPL"); 278 279 enum stat_access_type { 280 PHY, 281 MMD 282 }; 283 284 struct at803x_hw_stat { 285 const char *string; 286 u8 reg; 287 u32 mask; 288 enum stat_access_type access_type; 289 }; 290 291 static struct at803x_hw_stat at803x_hw_stats[] = { 292 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 293 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 294 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 295 }; 296 297 struct at803x_priv { 298 int flags; 299 u16 clk_25m_reg; 300 u16 clk_25m_mask; 301 u8 smarteee_lpi_tw_1g; 302 u8 smarteee_lpi_tw_100m; 303 bool is_fiber; 304 bool is_1000basex; 305 struct regulator_dev *vddio_rdev; 306 struct regulator_dev *vddh_rdev; 307 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 308 }; 309 310 struct at803x_context { 311 u16 bmcr; 312 u16 advertise; 313 u16 control1000; 314 u16 int_enable; 315 u16 smart_speed; 316 u16 led_control; 317 }; 318 319 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 320 { 321 int ret; 322 323 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 324 if (ret < 0) 325 return ret; 326 327 return phy_write(phydev, AT803X_DEBUG_DATA, data); 328 } 329 330 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 331 { 332 int ret; 333 334 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 335 if (ret < 0) 336 return ret; 337 338 return phy_read(phydev, AT803X_DEBUG_DATA); 339 } 340 341 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 342 u16 clear, u16 set) 343 { 344 u16 val; 345 int ret; 346 347 ret = at803x_debug_reg_read(phydev, reg); 348 if (ret < 0) 349 return ret; 350 351 val = ret & 0xffff; 352 val &= ~clear; 353 val |= set; 354 355 return phy_write(phydev, AT803X_DEBUG_DATA, val); 356 } 357 358 static int at803x_write_page(struct phy_device *phydev, int page) 359 { 360 int mask; 361 int set; 362 363 if (page == AT803X_PAGE_COPPER) { 364 set = AT803X_BT_BX_REG_SEL; 365 mask = 0; 366 } else { 367 set = 0; 368 mask = AT803X_BT_BX_REG_SEL; 369 } 370 371 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 372 } 373 374 static int at803x_read_page(struct phy_device *phydev) 375 { 376 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 377 378 if (ccr < 0) 379 return ccr; 380 381 if (ccr & AT803X_BT_BX_REG_SEL) 382 return AT803X_PAGE_COPPER; 383 384 return AT803X_PAGE_FIBER; 385 } 386 387 static int at803x_enable_rx_delay(struct phy_device *phydev) 388 { 389 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 390 AT803X_DEBUG_RX_CLK_DLY_EN); 391 } 392 393 static int at803x_enable_tx_delay(struct phy_device *phydev) 394 { 395 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 396 AT803X_DEBUG_TX_CLK_DLY_EN); 397 } 398 399 static int at803x_disable_rx_delay(struct phy_device *phydev) 400 { 401 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 402 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 403 } 404 405 static int at803x_disable_tx_delay(struct phy_device *phydev) 406 { 407 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 408 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 409 } 410 411 /* save relevant PHY registers to private copy */ 412 static void at803x_context_save(struct phy_device *phydev, 413 struct at803x_context *context) 414 { 415 context->bmcr = phy_read(phydev, MII_BMCR); 416 context->advertise = phy_read(phydev, MII_ADVERTISE); 417 context->control1000 = phy_read(phydev, MII_CTRL1000); 418 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 419 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 420 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 421 } 422 423 /* restore relevant PHY registers from private copy */ 424 static void at803x_context_restore(struct phy_device *phydev, 425 const struct at803x_context *context) 426 { 427 phy_write(phydev, MII_BMCR, context->bmcr); 428 phy_write(phydev, MII_ADVERTISE, context->advertise); 429 phy_write(phydev, MII_CTRL1000, context->control1000); 430 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 431 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 432 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 433 } 434 435 static int at803x_set_wol(struct phy_device *phydev, 436 struct ethtool_wolinfo *wol) 437 { 438 int ret, irq_enabled; 439 440 if (wol->wolopts & WAKE_MAGIC) { 441 struct net_device *ndev = phydev->attached_dev; 442 const u8 *mac; 443 unsigned int i; 444 static const unsigned int offsets[] = { 445 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 446 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 447 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 448 }; 449 450 if (!ndev) 451 return -ENODEV; 452 453 mac = (const u8 *) ndev->dev_addr; 454 455 if (!is_valid_ether_addr(mac)) 456 return -EINVAL; 457 458 for (i = 0; i < 3; i++) 459 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 460 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 461 462 /* Enable WOL function for 1588 */ 463 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 464 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 465 AT803X_PHY_MMD3_WOL_CTRL, 466 0, AT803X_WOL_EN); 467 if (ret) 468 return ret; 469 } 470 /* Enable WOL interrupt */ 471 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 472 if (ret) 473 return ret; 474 } else { 475 /* Disable WoL function for 1588 */ 476 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 477 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 478 AT803X_PHY_MMD3_WOL_CTRL, 479 AT803X_WOL_EN, 0); 480 if (ret) 481 return ret; 482 } 483 /* Disable WOL interrupt */ 484 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 485 if (ret) 486 return ret; 487 } 488 489 /* Clear WOL status */ 490 ret = phy_read(phydev, AT803X_INTR_STATUS); 491 if (ret < 0) 492 return ret; 493 494 /* Check if there are other interrupts except for WOL triggered when PHY is 495 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 496 * be passed up to the interrupt PIN. 497 */ 498 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 499 if (irq_enabled < 0) 500 return irq_enabled; 501 502 irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 503 if (ret & irq_enabled && !phy_polling_mode(phydev)) 504 phy_trigger_machine(phydev); 505 506 return 0; 507 } 508 509 static void at803x_get_wol(struct phy_device *phydev, 510 struct ethtool_wolinfo *wol) 511 { 512 int value; 513 514 wol->supported = WAKE_MAGIC; 515 wol->wolopts = 0; 516 517 value = phy_read(phydev, AT803X_INTR_ENABLE); 518 if (value < 0) 519 return; 520 521 if (value & AT803X_INTR_ENABLE_WOL) 522 wol->wolopts |= WAKE_MAGIC; 523 } 524 525 static int at803x_get_sset_count(struct phy_device *phydev) 526 { 527 return ARRAY_SIZE(at803x_hw_stats); 528 } 529 530 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 531 { 532 int i; 533 534 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 535 strscpy(data + i * ETH_GSTRING_LEN, 536 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 537 } 538 } 539 540 static u64 at803x_get_stat(struct phy_device *phydev, int i) 541 { 542 struct at803x_hw_stat stat = at803x_hw_stats[i]; 543 struct at803x_priv *priv = phydev->priv; 544 int val; 545 u64 ret; 546 547 if (stat.access_type == MMD) 548 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 549 else 550 val = phy_read(phydev, stat.reg); 551 552 if (val < 0) { 553 ret = U64_MAX; 554 } else { 555 val = val & stat.mask; 556 priv->stats[i] += val; 557 ret = priv->stats[i]; 558 } 559 560 return ret; 561 } 562 563 static void at803x_get_stats(struct phy_device *phydev, 564 struct ethtool_stats *stats, u64 *data) 565 { 566 int i; 567 568 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 569 data[i] = at803x_get_stat(phydev, i); 570 } 571 572 static int at803x_suspend(struct phy_device *phydev) 573 { 574 int value; 575 int wol_enabled; 576 577 value = phy_read(phydev, AT803X_INTR_ENABLE); 578 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 579 580 if (wol_enabled) 581 value = BMCR_ISOLATE; 582 else 583 value = BMCR_PDOWN; 584 585 phy_modify(phydev, MII_BMCR, 0, value); 586 587 return 0; 588 } 589 590 static int at803x_resume(struct phy_device *phydev) 591 { 592 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 593 } 594 595 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 596 unsigned int selector) 597 { 598 struct phy_device *phydev = rdev_get_drvdata(rdev); 599 600 if (selector) 601 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 602 0, AT803X_DEBUG_RGMII_1V8); 603 else 604 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 605 AT803X_DEBUG_RGMII_1V8, 0); 606 } 607 608 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 609 { 610 struct phy_device *phydev = rdev_get_drvdata(rdev); 611 int val; 612 613 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 614 if (val < 0) 615 return val; 616 617 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 618 } 619 620 static const struct regulator_ops vddio_regulator_ops = { 621 .list_voltage = regulator_list_voltage_table, 622 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 623 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 624 }; 625 626 static const unsigned int vddio_voltage_table[] = { 627 1500000, 628 1800000, 629 }; 630 631 static const struct regulator_desc vddio_desc = { 632 .name = "vddio", 633 .of_match = of_match_ptr("vddio-regulator"), 634 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 635 .volt_table = vddio_voltage_table, 636 .ops = &vddio_regulator_ops, 637 .type = REGULATOR_VOLTAGE, 638 .owner = THIS_MODULE, 639 }; 640 641 static const struct regulator_ops vddh_regulator_ops = { 642 }; 643 644 static const struct regulator_desc vddh_desc = { 645 .name = "vddh", 646 .of_match = of_match_ptr("vddh-regulator"), 647 .n_voltages = 1, 648 .fixed_uV = 2500000, 649 .ops = &vddh_regulator_ops, 650 .type = REGULATOR_VOLTAGE, 651 .owner = THIS_MODULE, 652 }; 653 654 static int at8031_register_regulators(struct phy_device *phydev) 655 { 656 struct at803x_priv *priv = phydev->priv; 657 struct device *dev = &phydev->mdio.dev; 658 struct regulator_config config = { }; 659 660 config.dev = dev; 661 config.driver_data = phydev; 662 663 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 664 if (IS_ERR(priv->vddio_rdev)) { 665 phydev_err(phydev, "failed to register VDDIO regulator\n"); 666 return PTR_ERR(priv->vddio_rdev); 667 } 668 669 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 670 if (IS_ERR(priv->vddh_rdev)) { 671 phydev_err(phydev, "failed to register VDDH regulator\n"); 672 return PTR_ERR(priv->vddh_rdev); 673 } 674 675 return 0; 676 } 677 678 static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 679 { 680 struct phy_device *phydev = upstream; 681 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 682 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 683 DECLARE_PHY_INTERFACE_MASK(interfaces); 684 phy_interface_t iface; 685 686 linkmode_zero(phy_support); 687 phylink_set(phy_support, 1000baseX_Full); 688 phylink_set(phy_support, 1000baseT_Full); 689 phylink_set(phy_support, Autoneg); 690 phylink_set(phy_support, Pause); 691 phylink_set(phy_support, Asym_Pause); 692 693 linkmode_zero(sfp_support); 694 sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); 695 /* Some modules support 10G modes as well as others we support. 696 * Mask out non-supported modes so the correct interface is picked. 697 */ 698 linkmode_and(sfp_support, phy_support, sfp_support); 699 700 if (linkmode_empty(sfp_support)) { 701 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 702 return -EINVAL; 703 } 704 705 iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 706 707 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 708 * interface for use with SFP modules. 709 * However, some copper modules detected as having a preferred SGMII 710 * interface do default to and function in 1000Base-X mode, so just 711 * print a warning and allow such modules, as they may have some chance 712 * of working. 713 */ 714 if (iface == PHY_INTERFACE_MODE_SGMII) 715 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 716 else if (iface != PHY_INTERFACE_MODE_1000BASEX) 717 return -EINVAL; 718 719 return 0; 720 } 721 722 static const struct sfp_upstream_ops at803x_sfp_ops = { 723 .attach = phy_sfp_attach, 724 .detach = phy_sfp_detach, 725 .module_insert = at803x_sfp_insert, 726 }; 727 728 static int at803x_parse_dt(struct phy_device *phydev) 729 { 730 struct device_node *node = phydev->mdio.dev.of_node; 731 struct at803x_priv *priv = phydev->priv; 732 u32 freq, strength, tw; 733 unsigned int sel; 734 int ret; 735 736 if (!IS_ENABLED(CONFIG_OF_MDIO)) 737 return 0; 738 739 if (of_property_read_bool(node, "qca,disable-smarteee")) 740 priv->flags |= AT803X_DISABLE_SMARTEEE; 741 742 if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 743 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 744 745 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 746 if (!tw || tw > 255) { 747 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 748 return -EINVAL; 749 } 750 priv->smarteee_lpi_tw_1g = tw; 751 } 752 753 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 754 if (!tw || tw > 255) { 755 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 756 return -EINVAL; 757 } 758 priv->smarteee_lpi_tw_100m = tw; 759 } 760 761 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 762 if (!ret) { 763 switch (freq) { 764 case 25000000: 765 sel = AT803X_CLK_OUT_25MHZ_XTAL; 766 break; 767 case 50000000: 768 sel = AT803X_CLK_OUT_50MHZ_PLL; 769 break; 770 case 62500000: 771 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 772 break; 773 case 125000000: 774 sel = AT803X_CLK_OUT_125MHZ_PLL; 775 break; 776 default: 777 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 778 return -EINVAL; 779 } 780 781 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 782 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 783 784 /* Fixup for the AR8030/AR8035. This chip has another mask and 785 * doesn't support the DSP reference. Eg. the lowest bit of the 786 * mask. The upper two bits select the same frequencies. Mask 787 * the lowest bit here. 788 * 789 * Warning: 790 * There was no datasheet for the AR8030 available so this is 791 * just a guess. But the AR8035 is listed as pin compatible 792 * to the AR8030 so there might be a good chance it works on 793 * the AR8030 too. 794 */ 795 if (phydev->drv->phy_id == ATH8030_PHY_ID || 796 phydev->drv->phy_id == ATH8035_PHY_ID) { 797 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 798 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 799 } 800 } 801 802 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 803 if (!ret) { 804 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 805 switch (strength) { 806 case AR803X_STRENGTH_FULL: 807 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 808 break; 809 case AR803X_STRENGTH_HALF: 810 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 811 break; 812 case AR803X_STRENGTH_QUARTER: 813 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 814 break; 815 default: 816 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 817 return -EINVAL; 818 } 819 } 820 821 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 822 * options. 823 */ 824 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 825 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 826 priv->flags |= AT803X_KEEP_PLL_ENABLED; 827 828 ret = at8031_register_regulators(phydev); 829 if (ret < 0) 830 return ret; 831 832 ret = devm_regulator_get_enable_optional(&phydev->mdio.dev, 833 "vddio"); 834 if (ret) { 835 phydev_err(phydev, "failed to get VDDIO regulator\n"); 836 return ret; 837 } 838 839 /* Only AR8031/8033 support 1000Base-X for SFP modules */ 840 ret = phy_sfp_probe(phydev, &at803x_sfp_ops); 841 if (ret < 0) 842 return ret; 843 } 844 845 return 0; 846 } 847 848 static int at803x_probe(struct phy_device *phydev) 849 { 850 struct device *dev = &phydev->mdio.dev; 851 struct at803x_priv *priv; 852 int ret; 853 854 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 855 if (!priv) 856 return -ENOMEM; 857 858 phydev->priv = priv; 859 860 ret = at803x_parse_dt(phydev); 861 if (ret) 862 return ret; 863 864 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 865 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 866 int mode_cfg; 867 868 if (ccr < 0) 869 return ccr; 870 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 871 872 switch (mode_cfg) { 873 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 874 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 875 priv->is_1000basex = true; 876 fallthrough; 877 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 878 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 879 priv->is_fiber = true; 880 break; 881 } 882 883 /* Disable WoL in 1588 register which is enabled 884 * by default 885 */ 886 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, 887 AT803X_PHY_MMD3_WOL_CTRL, 888 AT803X_WOL_EN, 0); 889 if (ret) 890 return ret; 891 } 892 893 return 0; 894 } 895 896 static int at803x_get_features(struct phy_device *phydev) 897 { 898 struct at803x_priv *priv = phydev->priv; 899 int err; 900 901 err = genphy_read_abilities(phydev); 902 if (err) 903 return err; 904 905 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 906 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); 907 if (err < 0) 908 return err; 909 910 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 911 err & MDIO_PMA_NG_EXTABLE_2_5GBT); 912 } 913 914 if (phydev->drv->phy_id != ATH8031_PHY_ID) 915 return 0; 916 917 /* AR8031/AR8033 have different status registers 918 * for copper and fiber operation. However, the 919 * extended status register is the same for both 920 * operation modes. 921 * 922 * As a result of that, ESTATUS_1000_XFULL is set 923 * to 1 even when operating in copper TP mode. 924 * 925 * Remove this mode from the supported link modes 926 * when not operating in 1000BaseX mode. 927 */ 928 if (!priv->is_1000basex) 929 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 930 phydev->supported); 931 932 return 0; 933 } 934 935 static int at803x_smarteee_config(struct phy_device *phydev) 936 { 937 struct at803x_priv *priv = phydev->priv; 938 u16 mask = 0, val = 0; 939 int ret; 940 941 if (priv->flags & AT803X_DISABLE_SMARTEEE) 942 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 943 AT803X_MMD3_SMARTEEE_CTL3, 944 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 945 946 if (priv->smarteee_lpi_tw_1g) { 947 mask |= 0xff00; 948 val |= priv->smarteee_lpi_tw_1g << 8; 949 } 950 if (priv->smarteee_lpi_tw_100m) { 951 mask |= 0x00ff; 952 val |= priv->smarteee_lpi_tw_100m; 953 } 954 if (!mask) 955 return 0; 956 957 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 958 mask, val); 959 if (ret) 960 return ret; 961 962 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 963 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 964 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 965 } 966 967 static int at803x_clk_out_config(struct phy_device *phydev) 968 { 969 struct at803x_priv *priv = phydev->priv; 970 971 if (!priv->clk_25m_mask) 972 return 0; 973 974 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 975 priv->clk_25m_mask, priv->clk_25m_reg); 976 } 977 978 static int at8031_pll_config(struct phy_device *phydev) 979 { 980 struct at803x_priv *priv = phydev->priv; 981 982 /* The default after hardware reset is PLL OFF. After a soft reset, the 983 * values are retained. 984 */ 985 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 986 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 987 0, AT803X_DEBUG_PLL_ON); 988 else 989 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 990 AT803X_DEBUG_PLL_ON, 0); 991 } 992 993 static int at803x_hibernation_mode_config(struct phy_device *phydev) 994 { 995 struct at803x_priv *priv = phydev->priv; 996 997 /* The default after hardware reset is hibernation mode enabled. After 998 * software reset, the value is retained. 999 */ 1000 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) 1001 return 0; 1002 1003 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1004 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 1005 } 1006 1007 static int at803x_config_init(struct phy_device *phydev) 1008 { 1009 struct at803x_priv *priv = phydev->priv; 1010 int ret; 1011 1012 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 1013 /* Some bootloaders leave the fiber page selected. 1014 * Switch to the appropriate page (fiber or copper), as otherwise we 1015 * read the PHY capabilities from the wrong page. 1016 */ 1017 phy_lock_mdio_bus(phydev); 1018 ret = at803x_write_page(phydev, 1019 priv->is_fiber ? AT803X_PAGE_FIBER : 1020 AT803X_PAGE_COPPER); 1021 phy_unlock_mdio_bus(phydev); 1022 if (ret) 1023 return ret; 1024 1025 ret = at8031_pll_config(phydev); 1026 if (ret < 0) 1027 return ret; 1028 } 1029 1030 /* The RX and TX delay default is: 1031 * after HW reset: RX delay enabled and TX delay disabled 1032 * after SW reset: RX delay enabled, while TX delay retains the 1033 * value before reset. 1034 */ 1035 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1036 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1037 ret = at803x_enable_rx_delay(phydev); 1038 else 1039 ret = at803x_disable_rx_delay(phydev); 1040 if (ret < 0) 1041 return ret; 1042 1043 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1044 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1045 ret = at803x_enable_tx_delay(phydev); 1046 else 1047 ret = at803x_disable_tx_delay(phydev); 1048 if (ret < 0) 1049 return ret; 1050 1051 ret = at803x_smarteee_config(phydev); 1052 if (ret < 0) 1053 return ret; 1054 1055 ret = at803x_clk_out_config(phydev); 1056 if (ret < 0) 1057 return ret; 1058 1059 ret = at803x_hibernation_mode_config(phydev); 1060 if (ret < 0) 1061 return ret; 1062 1063 /* Ar803x extended next page bit is enabled by default. Cisco 1064 * multigig switches read this bit and attempt to negotiate 10Gbps 1065 * rates even if the next page bit is disabled. This is incorrect 1066 * behaviour but we still need to accommodate it. XNP is only needed 1067 * for 10Gbps support, so disable XNP. 1068 */ 1069 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 1070 } 1071 1072 static int at803x_ack_interrupt(struct phy_device *phydev) 1073 { 1074 int err; 1075 1076 err = phy_read(phydev, AT803X_INTR_STATUS); 1077 1078 return (err < 0) ? err : 0; 1079 } 1080 1081 static int at803x_config_intr(struct phy_device *phydev) 1082 { 1083 struct at803x_priv *priv = phydev->priv; 1084 int err; 1085 int value; 1086 1087 value = phy_read(phydev, AT803X_INTR_ENABLE); 1088 1089 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1090 /* Clear any pending interrupts */ 1091 err = at803x_ack_interrupt(phydev); 1092 if (err) 1093 return err; 1094 1095 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 1096 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 1097 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 1098 value |= AT803X_INTR_ENABLE_LINK_FAIL; 1099 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 1100 if (priv->is_fiber) { 1101 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 1102 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 1103 } 1104 1105 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 1106 } else { 1107 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 1108 if (err) 1109 return err; 1110 1111 /* Clear any pending interrupts */ 1112 err = at803x_ack_interrupt(phydev); 1113 } 1114 1115 return err; 1116 } 1117 1118 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 1119 { 1120 int irq_status, int_enabled; 1121 1122 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 1123 if (irq_status < 0) { 1124 phy_error(phydev); 1125 return IRQ_NONE; 1126 } 1127 1128 /* Read the current enabled interrupts */ 1129 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 1130 if (int_enabled < 0) { 1131 phy_error(phydev); 1132 return IRQ_NONE; 1133 } 1134 1135 /* See if this was one of our enabled interrupts */ 1136 if (!(irq_status & int_enabled)) 1137 return IRQ_NONE; 1138 1139 phy_trigger_machine(phydev); 1140 1141 return IRQ_HANDLED; 1142 } 1143 1144 static void at803x_link_change_notify(struct phy_device *phydev) 1145 { 1146 /* 1147 * Conduct a hardware reset for AT8030 every time a link loss is 1148 * signalled. This is necessary to circumvent a hardware bug that 1149 * occurs when the cable is unplugged while TX packets are pending 1150 * in the FIFO. In such cases, the FIFO enters an error mode it 1151 * cannot recover from by software. 1152 */ 1153 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 1154 struct at803x_context context; 1155 1156 at803x_context_save(phydev, &context); 1157 1158 phy_device_reset(phydev, 1); 1159 msleep(1); 1160 phy_device_reset(phydev, 0); 1161 msleep(1); 1162 1163 at803x_context_restore(phydev, &context); 1164 1165 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 1166 } 1167 } 1168 1169 static int at803x_read_specific_status(struct phy_device *phydev) 1170 { 1171 int ss; 1172 1173 /* Read the AT8035 PHY-Specific Status register, which indicates the 1174 * speed and duplex that the PHY is actually using, irrespective of 1175 * whether we are in autoneg mode or not. 1176 */ 1177 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 1178 if (ss < 0) 1179 return ss; 1180 1181 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 1182 int sfc, speed; 1183 1184 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 1185 if (sfc < 0) 1186 return sfc; 1187 1188 /* qca8081 takes the different bits for speed value from at803x */ 1189 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1190 speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 1191 else 1192 speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 1193 1194 switch (speed) { 1195 case AT803X_SS_SPEED_10: 1196 phydev->speed = SPEED_10; 1197 break; 1198 case AT803X_SS_SPEED_100: 1199 phydev->speed = SPEED_100; 1200 break; 1201 case AT803X_SS_SPEED_1000: 1202 phydev->speed = SPEED_1000; 1203 break; 1204 case QCA808X_SS_SPEED_2500: 1205 phydev->speed = SPEED_2500; 1206 break; 1207 } 1208 if (ss & AT803X_SS_DUPLEX) 1209 phydev->duplex = DUPLEX_FULL; 1210 else 1211 phydev->duplex = DUPLEX_HALF; 1212 1213 if (ss & AT803X_SS_MDIX) 1214 phydev->mdix = ETH_TP_MDI_X; 1215 else 1216 phydev->mdix = ETH_TP_MDI; 1217 1218 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 1219 case AT803X_SFC_MANUAL_MDI: 1220 phydev->mdix_ctrl = ETH_TP_MDI; 1221 break; 1222 case AT803X_SFC_MANUAL_MDIX: 1223 phydev->mdix_ctrl = ETH_TP_MDI_X; 1224 break; 1225 case AT803X_SFC_AUTOMATIC_CROSSOVER: 1226 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1227 break; 1228 } 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int at803x_read_status(struct phy_device *phydev) 1235 { 1236 struct at803x_priv *priv = phydev->priv; 1237 int err, old_link = phydev->link; 1238 1239 if (priv->is_1000basex) 1240 return genphy_c37_read_status(phydev); 1241 1242 /* Update the link, but return if there was an error */ 1243 err = genphy_update_link(phydev); 1244 if (err) 1245 return err; 1246 1247 /* why bother the PHY if nothing can have changed */ 1248 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 1249 return 0; 1250 1251 phydev->speed = SPEED_UNKNOWN; 1252 phydev->duplex = DUPLEX_UNKNOWN; 1253 phydev->pause = 0; 1254 phydev->asym_pause = 0; 1255 1256 err = genphy_read_lpa(phydev); 1257 if (err < 0) 1258 return err; 1259 1260 err = at803x_read_specific_status(phydev); 1261 if (err < 0) 1262 return err; 1263 1264 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1265 phy_resolve_aneg_pause(phydev); 1266 1267 return 0; 1268 } 1269 1270 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 1271 { 1272 u16 val; 1273 1274 switch (ctrl) { 1275 case ETH_TP_MDI: 1276 val = AT803X_SFC_MANUAL_MDI; 1277 break; 1278 case ETH_TP_MDI_X: 1279 val = AT803X_SFC_MANUAL_MDIX; 1280 break; 1281 case ETH_TP_MDI_AUTO: 1282 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 1283 break; 1284 default: 1285 return 0; 1286 } 1287 1288 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 1289 AT803X_SFC_MDI_CROSSOVER_MODE_M, 1290 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1291 } 1292 1293 static int at803x_config_aneg(struct phy_device *phydev) 1294 { 1295 struct at803x_priv *priv = phydev->priv; 1296 int ret; 1297 1298 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1299 if (ret < 0) 1300 return ret; 1301 1302 /* Changes of the midx bits are disruptive to the normal operation; 1303 * therefore any changes to these registers must be followed by a 1304 * software reset to take effect. 1305 */ 1306 if (ret == 1) { 1307 ret = genphy_soft_reset(phydev); 1308 if (ret < 0) 1309 return ret; 1310 } 1311 1312 if (priv->is_1000basex) 1313 return genphy_c37_config_aneg(phydev); 1314 1315 /* Do not restart auto-negotiation by setting ret to 0 defautly, 1316 * when calling __genphy_config_aneg later. 1317 */ 1318 ret = 0; 1319 1320 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1321 int phy_ctrl = 0; 1322 1323 /* The reg MII_BMCR also needs to be configured for force mode, the 1324 * genphy_config_aneg is also needed. 1325 */ 1326 if (phydev->autoneg == AUTONEG_DISABLE) 1327 genphy_c45_pma_setup_forced(phydev); 1328 1329 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1330 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1331 1332 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1333 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1334 if (ret < 0) 1335 return ret; 1336 } 1337 1338 return __genphy_config_aneg(phydev, ret); 1339 } 1340 1341 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1342 { 1343 int val; 1344 1345 val = phy_read(phydev, AT803X_SMART_SPEED); 1346 if (val < 0) 1347 return val; 1348 1349 if (val & AT803X_SMART_SPEED_ENABLE) 1350 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1351 else 1352 *d = DOWNSHIFT_DEV_DISABLE; 1353 1354 return 0; 1355 } 1356 1357 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1358 { 1359 u16 mask, set; 1360 int ret; 1361 1362 switch (cnt) { 1363 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1364 cnt = AT803X_DEFAULT_DOWNSHIFT; 1365 fallthrough; 1366 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1367 set = AT803X_SMART_SPEED_ENABLE | 1368 AT803X_SMART_SPEED_BYPASS_TIMER | 1369 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1370 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1371 break; 1372 case DOWNSHIFT_DEV_DISABLE: 1373 set = 0; 1374 mask = AT803X_SMART_SPEED_ENABLE | 1375 AT803X_SMART_SPEED_BYPASS_TIMER; 1376 break; 1377 default: 1378 return -EINVAL; 1379 } 1380 1381 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1382 1383 /* After changing the smart speed settings, we need to perform a 1384 * software reset, use phy_init_hw() to make sure we set the 1385 * reapply any values which might got lost during software reset. 1386 */ 1387 if (ret == 1) 1388 ret = phy_init_hw(phydev); 1389 1390 return ret; 1391 } 1392 1393 static int at803x_get_tunable(struct phy_device *phydev, 1394 struct ethtool_tunable *tuna, void *data) 1395 { 1396 switch (tuna->id) { 1397 case ETHTOOL_PHY_DOWNSHIFT: 1398 return at803x_get_downshift(phydev, data); 1399 default: 1400 return -EOPNOTSUPP; 1401 } 1402 } 1403 1404 static int at803x_set_tunable(struct phy_device *phydev, 1405 struct ethtool_tunable *tuna, const void *data) 1406 { 1407 switch (tuna->id) { 1408 case ETHTOOL_PHY_DOWNSHIFT: 1409 return at803x_set_downshift(phydev, *(const u8 *)data); 1410 default: 1411 return -EOPNOTSUPP; 1412 } 1413 } 1414 1415 static int at803x_cable_test_result_trans(u16 status) 1416 { 1417 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1418 case AT803X_CDT_STATUS_STAT_NORMAL: 1419 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1420 case AT803X_CDT_STATUS_STAT_SHORT: 1421 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1422 case AT803X_CDT_STATUS_STAT_OPEN: 1423 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1424 case AT803X_CDT_STATUS_STAT_FAIL: 1425 default: 1426 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1427 } 1428 } 1429 1430 static bool at803x_cdt_test_failed(u16 status) 1431 { 1432 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1433 AT803X_CDT_STATUS_STAT_FAIL; 1434 } 1435 1436 static bool at803x_cdt_fault_length_valid(u16 status) 1437 { 1438 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1439 case AT803X_CDT_STATUS_STAT_OPEN: 1440 case AT803X_CDT_STATUS_STAT_SHORT: 1441 return true; 1442 } 1443 return false; 1444 } 1445 1446 static int at803x_cdt_fault_length(u16 status) 1447 { 1448 int dt; 1449 1450 /* According to the datasheet the distance to the fault is 1451 * DELTA_TIME * 0.824 meters. 1452 * 1453 * The author suspect the correct formula is: 1454 * 1455 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1456 * 1457 * where c is the speed of light, VF is the velocity factor of 1458 * the twisted pair cable, 125MHz the counter frequency and 1459 * we need to divide by 2 because the hardware will measure the 1460 * round trip time to the fault and back to the PHY. 1461 * 1462 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1463 * datasheet. 1464 */ 1465 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1466 1467 return (dt * 824) / 10; 1468 } 1469 1470 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1471 { 1472 u16 cdt; 1473 1474 /* qca8081 takes the different bit 15 to enable CDT test */ 1475 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1476 cdt = QCA808X_CDT_ENABLE_TEST | 1477 QCA808X_CDT_LENGTH_UNIT | 1478 QCA808X_CDT_INTER_CHECK_DIS; 1479 else 1480 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1481 AT803X_CDT_ENABLE_TEST; 1482 1483 return phy_write(phydev, AT803X_CDT, cdt); 1484 } 1485 1486 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1487 { 1488 int val, ret; 1489 u16 cdt_en; 1490 1491 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1492 cdt_en = QCA808X_CDT_ENABLE_TEST; 1493 else 1494 cdt_en = AT803X_CDT_ENABLE_TEST; 1495 1496 /* One test run takes about 25ms */ 1497 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1498 !(val & cdt_en), 1499 30000, 100000, true); 1500 1501 return ret < 0 ? ret : 0; 1502 } 1503 1504 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1505 { 1506 static const int ethtool_pair[] = { 1507 ETHTOOL_A_CABLE_PAIR_A, 1508 ETHTOOL_A_CABLE_PAIR_B, 1509 ETHTOOL_A_CABLE_PAIR_C, 1510 ETHTOOL_A_CABLE_PAIR_D, 1511 }; 1512 int ret, val; 1513 1514 ret = at803x_cdt_start(phydev, pair); 1515 if (ret) 1516 return ret; 1517 1518 ret = at803x_cdt_wait_for_completion(phydev); 1519 if (ret) 1520 return ret; 1521 1522 val = phy_read(phydev, AT803X_CDT_STATUS); 1523 if (val < 0) 1524 return val; 1525 1526 if (at803x_cdt_test_failed(val)) 1527 return 0; 1528 1529 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1530 at803x_cable_test_result_trans(val)); 1531 1532 if (at803x_cdt_fault_length_valid(val)) 1533 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1534 at803x_cdt_fault_length(val)); 1535 1536 return 1; 1537 } 1538 1539 static int at803x_cable_test_get_status(struct phy_device *phydev, 1540 bool *finished) 1541 { 1542 unsigned long pair_mask; 1543 int retries = 20; 1544 int pair, ret; 1545 1546 if (phydev->phy_id == ATH9331_PHY_ID || 1547 phydev->phy_id == ATH8032_PHY_ID || 1548 phydev->phy_id == QCA9561_PHY_ID) 1549 pair_mask = 0x3; 1550 else 1551 pair_mask = 0xf; 1552 1553 *finished = false; 1554 1555 /* According to the datasheet the CDT can be performed when 1556 * there is no link partner or when the link partner is 1557 * auto-negotiating. Starting the test will restart the AN 1558 * automatically. It seems that doing this repeatedly we will 1559 * get a slot where our link partner won't disturb our 1560 * measurement. 1561 */ 1562 while (pair_mask && retries--) { 1563 for_each_set_bit(pair, &pair_mask, 4) { 1564 ret = at803x_cable_test_one_pair(phydev, pair); 1565 if (ret < 0) 1566 return ret; 1567 if (ret) 1568 clear_bit(pair, &pair_mask); 1569 } 1570 if (pair_mask) 1571 msleep(250); 1572 } 1573 1574 *finished = true; 1575 1576 return 0; 1577 } 1578 1579 static int at803x_cable_test_start(struct phy_device *phydev) 1580 { 1581 /* Enable auto-negotiation, but advertise no capabilities, no link 1582 * will be established. A restart of the auto-negotiation is not 1583 * required, because the cable test will automatically break the link. 1584 */ 1585 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1586 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1587 if (phydev->phy_id != ATH9331_PHY_ID && 1588 phydev->phy_id != ATH8032_PHY_ID && 1589 phydev->phy_id != QCA9561_PHY_ID) 1590 phy_write(phydev, MII_CTRL1000, 0); 1591 1592 /* we do all the (time consuming) work later */ 1593 return 0; 1594 } 1595 1596 static int qca83xx_config_init(struct phy_device *phydev) 1597 { 1598 u8 switch_revision; 1599 1600 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1601 1602 switch (switch_revision) { 1603 case 1: 1604 /* For 100M waveform */ 1605 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1606 /* Turn on Gigabit clock */ 1607 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1608 break; 1609 1610 case 2: 1611 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1612 fallthrough; 1613 case 4: 1614 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1615 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 1616 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1617 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1618 break; 1619 } 1620 1621 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 1622 * Disable on init and enable only with 100m speed following 1623 * qca original source code. 1624 */ 1625 if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 1626 phydev->drv->phy_id == QCA8327_B_PHY_ID) 1627 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1628 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1629 1630 /* Following original QCA sourcecode set port to prefer master */ 1631 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 1632 1633 return 0; 1634 } 1635 1636 static void qca83xx_link_change_notify(struct phy_device *phydev) 1637 { 1638 /* QCA8337 doesn't require DAC Amplitude adjustement */ 1639 if (phydev->drv->phy_id == QCA8337_PHY_ID) 1640 return; 1641 1642 /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 1643 if (phydev->state == PHY_RUNNING) { 1644 if (phydev->speed == SPEED_100) 1645 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1646 QCA8327_DEBUG_MANU_CTRL_EN, 1647 QCA8327_DEBUG_MANU_CTRL_EN); 1648 } else { 1649 /* Reset DAC Amplitude adjustment */ 1650 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1651 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1652 } 1653 } 1654 1655 static int qca83xx_resume(struct phy_device *phydev) 1656 { 1657 int ret, val; 1658 1659 /* Skip reset if not suspended */ 1660 if (!phydev->suspended) 1661 return 0; 1662 1663 /* Reinit the port, reset values set by suspend */ 1664 qca83xx_config_init(phydev); 1665 1666 /* Reset the port on port resume */ 1667 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1668 1669 /* On resume from suspend the switch execute a reset and 1670 * restart auto-negotiation. Wait for reset to complete. 1671 */ 1672 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1673 50000, 600000, true); 1674 if (ret) 1675 return ret; 1676 1677 msleep(1); 1678 1679 return 0; 1680 } 1681 1682 static int qca83xx_suspend(struct phy_device *phydev) 1683 { 1684 u16 mask = 0; 1685 1686 /* Only QCA8337 support actual suspend. 1687 * QCA8327 cause port unreliability when phy suspend 1688 * is set. 1689 */ 1690 if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1691 genphy_suspend(phydev); 1692 } else { 1693 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1694 phy_modify(phydev, MII_BMCR, mask, 0); 1695 } 1696 1697 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1698 AT803X_DEBUG_GATE_CLK_IN1000, 0); 1699 1700 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1701 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1702 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1703 1704 return 0; 1705 } 1706 1707 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 1708 { 1709 int ret; 1710 1711 /* Enable fast retrain */ 1712 ret = genphy_c45_fast_retrain(phydev, true); 1713 if (ret) 1714 return ret; 1715 1716 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 1717 QCA808X_TOP_OPTION1_DATA); 1718 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 1719 QCA808X_MSE_THRESHOLD_20DB_VALUE); 1720 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 1721 QCA808X_MSE_THRESHOLD_17DB_VALUE); 1722 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 1723 QCA808X_MSE_THRESHOLD_27DB_VALUE); 1724 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 1725 QCA808X_MSE_THRESHOLD_28DB_VALUE); 1726 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 1727 QCA808X_MMD3_DEBUG_1_VALUE); 1728 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 1729 QCA808X_MMD3_DEBUG_4_VALUE); 1730 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 1731 QCA808X_MMD3_DEBUG_5_VALUE); 1732 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 1733 QCA808X_MMD3_DEBUG_3_VALUE); 1734 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 1735 QCA808X_MMD3_DEBUG_6_VALUE); 1736 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 1737 QCA808X_MMD3_DEBUG_2_VALUE); 1738 1739 return 0; 1740 } 1741 1742 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) 1743 { 1744 u16 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE); 1745 1746 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1747 QCA808X_MASTER_SLAVE_SEED_CFG, 1748 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); 1749 } 1750 1751 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 1752 { 1753 u16 seed_enable = 0; 1754 1755 if (enable) 1756 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; 1757 1758 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1759 QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); 1760 } 1761 1762 static int qca808x_config_init(struct phy_device *phydev) 1763 { 1764 int ret; 1765 1766 /* Active adc&vga on 802.3az for the link 1000M and 100M */ 1767 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 1768 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 1769 if (ret) 1770 return ret; 1771 1772 /* Adjust the threshold on 802.3az for the link 1000M */ 1773 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 1774 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 1775 if (ret) 1776 return ret; 1777 1778 /* Config the fast retrain for the link 2500M */ 1779 ret = qca808x_phy_fast_retrain_config(phydev); 1780 if (ret) 1781 return ret; 1782 1783 /* Configure lower ramdom seed to make phy linked as slave mode */ 1784 ret = qca808x_phy_ms_random_seed_set(phydev); 1785 if (ret) 1786 return ret; 1787 1788 /* Enable seed */ 1789 ret = qca808x_phy_ms_seed_enable(phydev, true); 1790 if (ret) 1791 return ret; 1792 1793 /* Configure adc threshold as 100mv for the link 10M */ 1794 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 1795 QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 1796 } 1797 1798 static int qca808x_read_status(struct phy_device *phydev) 1799 { 1800 int ret; 1801 1802 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1803 if (ret < 0) 1804 return ret; 1805 1806 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 1807 ret & MDIO_AN_10GBT_STAT_LP2_5G); 1808 1809 ret = genphy_read_status(phydev); 1810 if (ret) 1811 return ret; 1812 1813 ret = at803x_read_specific_status(phydev); 1814 if (ret < 0) 1815 return ret; 1816 1817 if (phydev->link) { 1818 if (phydev->speed == SPEED_2500) 1819 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1820 else 1821 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1822 } else { 1823 /* generate seed as a lower random value to make PHY linked as SLAVE easily, 1824 * except for master/slave configuration fault detected. 1825 * the reason for not putting this code into the function link_change_notify is 1826 * the corner case where the link partner is also the qca8081 PHY and the seed 1827 * value is configured as the same value, the link can't be up and no link change 1828 * occurs. 1829 */ 1830 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { 1831 qca808x_phy_ms_seed_enable(phydev, false); 1832 } else { 1833 qca808x_phy_ms_random_seed_set(phydev); 1834 qca808x_phy_ms_seed_enable(phydev, true); 1835 } 1836 } 1837 1838 return 0; 1839 } 1840 1841 static int qca808x_soft_reset(struct phy_device *phydev) 1842 { 1843 int ret; 1844 1845 ret = genphy_soft_reset(phydev); 1846 if (ret < 0) 1847 return ret; 1848 1849 return qca808x_phy_ms_seed_enable(phydev, true); 1850 } 1851 1852 static bool qca808x_cdt_fault_length_valid(int cdt_code) 1853 { 1854 switch (cdt_code) { 1855 case QCA808X_CDT_STATUS_STAT_SHORT: 1856 case QCA808X_CDT_STATUS_STAT_OPEN: 1857 return true; 1858 default: 1859 return false; 1860 } 1861 } 1862 1863 static int qca808x_cable_test_result_trans(int cdt_code) 1864 { 1865 switch (cdt_code) { 1866 case QCA808X_CDT_STATUS_STAT_NORMAL: 1867 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1868 case QCA808X_CDT_STATUS_STAT_SHORT: 1869 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1870 case QCA808X_CDT_STATUS_STAT_OPEN: 1871 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1872 case QCA808X_CDT_STATUS_STAT_FAIL: 1873 default: 1874 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1875 } 1876 } 1877 1878 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 1879 { 1880 int val; 1881 u32 cdt_length_reg = 0; 1882 1883 switch (pair) { 1884 case ETHTOOL_A_CABLE_PAIR_A: 1885 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 1886 break; 1887 case ETHTOOL_A_CABLE_PAIR_B: 1888 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 1889 break; 1890 case ETHTOOL_A_CABLE_PAIR_C: 1891 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 1892 break; 1893 case ETHTOOL_A_CABLE_PAIR_D: 1894 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 1895 break; 1896 default: 1897 return -EINVAL; 1898 } 1899 1900 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 1901 if (val < 0) 1902 return val; 1903 1904 return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 1905 } 1906 1907 static int qca808x_cable_test_start(struct phy_device *phydev) 1908 { 1909 int ret; 1910 1911 /* perform CDT with the following configs: 1912 * 1. disable hibernation. 1913 * 2. force PHY working in MDI mode. 1914 * 3. for PHY working in 1000BaseT. 1915 * 4. configure the threshold. 1916 */ 1917 1918 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 1919 if (ret < 0) 1920 return ret; 1921 1922 ret = at803x_config_mdix(phydev, ETH_TP_MDI); 1923 if (ret < 0) 1924 return ret; 1925 1926 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 1927 phydev->duplex = DUPLEX_FULL; 1928 phydev->speed = SPEED_1000; 1929 ret = genphy_c45_pma_setup_forced(phydev); 1930 if (ret < 0) 1931 return ret; 1932 1933 ret = genphy_setup_forced(phydev); 1934 if (ret < 0) 1935 return ret; 1936 1937 /* configure the thresholds for open, short, pair ok test */ 1938 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 1939 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 1940 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 1941 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 1942 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 1943 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 1944 1945 return 0; 1946 } 1947 1948 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 1949 { 1950 int ret, val; 1951 int pair_a, pair_b, pair_c, pair_d; 1952 1953 *finished = false; 1954 1955 ret = at803x_cdt_start(phydev, 0); 1956 if (ret) 1957 return ret; 1958 1959 ret = at803x_cdt_wait_for_completion(phydev); 1960 if (ret) 1961 return ret; 1962 1963 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 1964 if (val < 0) 1965 return val; 1966 1967 pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 1968 pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 1969 pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 1970 pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 1971 1972 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1973 qca808x_cable_test_result_trans(pair_a)); 1974 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 1975 qca808x_cable_test_result_trans(pair_b)); 1976 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 1977 qca808x_cable_test_result_trans(pair_c)); 1978 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 1979 qca808x_cable_test_result_trans(pair_d)); 1980 1981 if (qca808x_cdt_fault_length_valid(pair_a)) 1982 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 1983 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 1984 if (qca808x_cdt_fault_length_valid(pair_b)) 1985 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 1986 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 1987 if (qca808x_cdt_fault_length_valid(pair_c)) 1988 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 1989 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 1990 if (qca808x_cdt_fault_length_valid(pair_d)) 1991 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 1992 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 1993 1994 *finished = true; 1995 1996 return 0; 1997 } 1998 1999 static struct phy_driver at803x_driver[] = { 2000 { 2001 /* Qualcomm Atheros AR8035 */ 2002 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 2003 .name = "Qualcomm Atheros AR8035", 2004 .flags = PHY_POLL_CABLE_TEST, 2005 .probe = at803x_probe, 2006 .config_aneg = at803x_config_aneg, 2007 .config_init = at803x_config_init, 2008 .soft_reset = genphy_soft_reset, 2009 .set_wol = at803x_set_wol, 2010 .get_wol = at803x_get_wol, 2011 .suspend = at803x_suspend, 2012 .resume = at803x_resume, 2013 /* PHY_GBIT_FEATURES */ 2014 .read_status = at803x_read_status, 2015 .config_intr = at803x_config_intr, 2016 .handle_interrupt = at803x_handle_interrupt, 2017 .get_tunable = at803x_get_tunable, 2018 .set_tunable = at803x_set_tunable, 2019 .cable_test_start = at803x_cable_test_start, 2020 .cable_test_get_status = at803x_cable_test_get_status, 2021 }, { 2022 /* Qualcomm Atheros AR8030 */ 2023 .phy_id = ATH8030_PHY_ID, 2024 .name = "Qualcomm Atheros AR8030", 2025 .phy_id_mask = AT8030_PHY_ID_MASK, 2026 .probe = at803x_probe, 2027 .config_init = at803x_config_init, 2028 .link_change_notify = at803x_link_change_notify, 2029 .set_wol = at803x_set_wol, 2030 .get_wol = at803x_get_wol, 2031 .suspend = at803x_suspend, 2032 .resume = at803x_resume, 2033 /* PHY_BASIC_FEATURES */ 2034 .config_intr = at803x_config_intr, 2035 .handle_interrupt = at803x_handle_interrupt, 2036 }, { 2037 /* Qualcomm Atheros AR8031/AR8033 */ 2038 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 2039 .name = "Qualcomm Atheros AR8031/AR8033", 2040 .flags = PHY_POLL_CABLE_TEST, 2041 .probe = at803x_probe, 2042 .config_init = at803x_config_init, 2043 .config_aneg = at803x_config_aneg, 2044 .soft_reset = genphy_soft_reset, 2045 .set_wol = at803x_set_wol, 2046 .get_wol = at803x_get_wol, 2047 .suspend = at803x_suspend, 2048 .resume = at803x_resume, 2049 .read_page = at803x_read_page, 2050 .write_page = at803x_write_page, 2051 .get_features = at803x_get_features, 2052 .read_status = at803x_read_status, 2053 .config_intr = &at803x_config_intr, 2054 .handle_interrupt = at803x_handle_interrupt, 2055 .get_tunable = at803x_get_tunable, 2056 .set_tunable = at803x_set_tunable, 2057 .cable_test_start = at803x_cable_test_start, 2058 .cable_test_get_status = at803x_cable_test_get_status, 2059 }, { 2060 /* Qualcomm Atheros AR8032 */ 2061 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 2062 .name = "Qualcomm Atheros AR8032", 2063 .probe = at803x_probe, 2064 .flags = PHY_POLL_CABLE_TEST, 2065 .config_init = at803x_config_init, 2066 .link_change_notify = at803x_link_change_notify, 2067 .suspend = at803x_suspend, 2068 .resume = at803x_resume, 2069 /* PHY_BASIC_FEATURES */ 2070 .config_intr = at803x_config_intr, 2071 .handle_interrupt = at803x_handle_interrupt, 2072 .cable_test_start = at803x_cable_test_start, 2073 .cable_test_get_status = at803x_cable_test_get_status, 2074 }, { 2075 /* ATHEROS AR9331 */ 2076 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 2077 .name = "Qualcomm Atheros AR9331 built-in PHY", 2078 .probe = at803x_probe, 2079 .suspend = at803x_suspend, 2080 .resume = at803x_resume, 2081 .flags = PHY_POLL_CABLE_TEST, 2082 /* PHY_BASIC_FEATURES */ 2083 .config_intr = &at803x_config_intr, 2084 .handle_interrupt = at803x_handle_interrupt, 2085 .cable_test_start = at803x_cable_test_start, 2086 .cable_test_get_status = at803x_cable_test_get_status, 2087 .read_status = at803x_read_status, 2088 .soft_reset = genphy_soft_reset, 2089 .config_aneg = at803x_config_aneg, 2090 }, { 2091 /* Qualcomm Atheros QCA9561 */ 2092 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 2093 .name = "Qualcomm Atheros QCA9561 built-in PHY", 2094 .probe = at803x_probe, 2095 .suspend = at803x_suspend, 2096 .resume = at803x_resume, 2097 .flags = PHY_POLL_CABLE_TEST, 2098 /* PHY_BASIC_FEATURES */ 2099 .config_intr = &at803x_config_intr, 2100 .handle_interrupt = at803x_handle_interrupt, 2101 .cable_test_start = at803x_cable_test_start, 2102 .cable_test_get_status = at803x_cable_test_get_status, 2103 .read_status = at803x_read_status, 2104 .soft_reset = genphy_soft_reset, 2105 .config_aneg = at803x_config_aneg, 2106 }, { 2107 /* QCA8337 */ 2108 .phy_id = QCA8337_PHY_ID, 2109 .phy_id_mask = QCA8K_PHY_ID_MASK, 2110 .name = "Qualcomm Atheros 8337 internal PHY", 2111 /* PHY_GBIT_FEATURES */ 2112 .link_change_notify = qca83xx_link_change_notify, 2113 .probe = at803x_probe, 2114 .flags = PHY_IS_INTERNAL, 2115 .config_init = qca83xx_config_init, 2116 .soft_reset = genphy_soft_reset, 2117 .get_sset_count = at803x_get_sset_count, 2118 .get_strings = at803x_get_strings, 2119 .get_stats = at803x_get_stats, 2120 .suspend = qca83xx_suspend, 2121 .resume = qca83xx_resume, 2122 }, { 2123 /* QCA8327-A from switch QCA8327-AL1A */ 2124 .phy_id = QCA8327_A_PHY_ID, 2125 .phy_id_mask = QCA8K_PHY_ID_MASK, 2126 .name = "Qualcomm Atheros 8327-A internal PHY", 2127 /* PHY_GBIT_FEATURES */ 2128 .link_change_notify = qca83xx_link_change_notify, 2129 .probe = at803x_probe, 2130 .flags = PHY_IS_INTERNAL, 2131 .config_init = qca83xx_config_init, 2132 .soft_reset = genphy_soft_reset, 2133 .get_sset_count = at803x_get_sset_count, 2134 .get_strings = at803x_get_strings, 2135 .get_stats = at803x_get_stats, 2136 .suspend = qca83xx_suspend, 2137 .resume = qca83xx_resume, 2138 }, { 2139 /* QCA8327-B from switch QCA8327-BL1A */ 2140 .phy_id = QCA8327_B_PHY_ID, 2141 .phy_id_mask = QCA8K_PHY_ID_MASK, 2142 .name = "Qualcomm Atheros 8327-B internal PHY", 2143 /* PHY_GBIT_FEATURES */ 2144 .link_change_notify = qca83xx_link_change_notify, 2145 .probe = at803x_probe, 2146 .flags = PHY_IS_INTERNAL, 2147 .config_init = qca83xx_config_init, 2148 .soft_reset = genphy_soft_reset, 2149 .get_sset_count = at803x_get_sset_count, 2150 .get_strings = at803x_get_strings, 2151 .get_stats = at803x_get_stats, 2152 .suspend = qca83xx_suspend, 2153 .resume = qca83xx_resume, 2154 }, { 2155 /* Qualcomm QCA8081 */ 2156 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2157 .name = "Qualcomm QCA8081", 2158 .flags = PHY_POLL_CABLE_TEST, 2159 .probe = at803x_probe, 2160 .config_intr = at803x_config_intr, 2161 .handle_interrupt = at803x_handle_interrupt, 2162 .get_tunable = at803x_get_tunable, 2163 .set_tunable = at803x_set_tunable, 2164 .set_wol = at803x_set_wol, 2165 .get_wol = at803x_get_wol, 2166 .get_features = at803x_get_features, 2167 .config_aneg = at803x_config_aneg, 2168 .suspend = genphy_suspend, 2169 .resume = genphy_resume, 2170 .read_status = qca808x_read_status, 2171 .config_init = qca808x_config_init, 2172 .soft_reset = qca808x_soft_reset, 2173 .cable_test_start = qca808x_cable_test_start, 2174 .cable_test_get_status = qca808x_cable_test_get_status, 2175 }, }; 2176 2177 module_phy_driver(at803x_driver); 2178 2179 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 2180 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 2181 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 2182 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 2183 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 2184 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 2185 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2186 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2187 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2188 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2189 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 2190 { } 2191 }; 2192 2193 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2194