1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <dt-bindings/net/qca-ar803x.h> 23 24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 25 #define AT803X_SFC_ASSERT_CRS BIT(11) 26 #define AT803X_SFC_FORCE_LINK BIT(10) 27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 29 #define AT803X_SFC_MANUAL_MDIX 0x1 30 #define AT803X_SFC_MANUAL_MDI 0x0 31 #define AT803X_SFC_SQE_TEST BIT(2) 32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 33 #define AT803X_SFC_DISABLE_JABBER BIT(0) 34 35 #define AT803X_SPECIFIC_STATUS 0x11 36 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 37 #define AT803X_SS_SPEED_1000 2 38 #define AT803X_SS_SPEED_100 1 39 #define AT803X_SS_SPEED_10 0 40 #define AT803X_SS_DUPLEX BIT(13) 41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 42 #define AT803X_SS_MDIX BIT(6) 43 44 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 45 #define QCA808X_SS_SPEED_2500 4 46 47 #define AT803X_INTR_ENABLE 0x12 48 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 49 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 50 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 51 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 52 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 53 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 54 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 55 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 56 #define AT803X_INTR_ENABLE_WOL BIT(0) 57 58 #define AT803X_INTR_STATUS 0x13 59 60 #define AT803X_SMART_SPEED 0x14 61 #define AT803X_SMART_SPEED_ENABLE BIT(5) 62 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 63 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 64 #define AT803X_CDT 0x16 65 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 66 #define AT803X_CDT_ENABLE_TEST BIT(0) 67 #define AT803X_CDT_STATUS 0x1c 68 #define AT803X_CDT_STATUS_STAT_NORMAL 0 69 #define AT803X_CDT_STATUS_STAT_SHORT 1 70 #define AT803X_CDT_STATUS_STAT_OPEN 2 71 #define AT803X_CDT_STATUS_STAT_FAIL 3 72 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 73 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 74 #define AT803X_LED_CONTROL 0x18 75 76 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 77 #define AT803X_WOL_EN BIT(5) 78 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 79 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 80 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 81 #define AT803X_REG_CHIP_CONFIG 0x1f 82 #define AT803X_BT_BX_REG_SEL 0x8000 83 84 #define AT803X_DEBUG_ADDR 0x1D 85 #define AT803X_DEBUG_DATA 0x1E 86 87 #define AT803X_MODE_CFG_MASK 0x0F 88 #define AT803X_MODE_CFG_SGMII 0x01 89 90 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 91 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 92 93 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 94 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 95 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 96 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 97 98 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 99 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 100 101 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 102 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 103 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 104 105 #define AT803X_DEBUG_REG_3C 0x3C 106 107 #define AT803X_DEBUG_REG_GREEN 0x3D 108 #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 109 110 #define AT803X_DEBUG_REG_1F 0x1F 111 #define AT803X_DEBUG_PLL_ON BIT(2) 112 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 113 114 #define MDIO_AZ_DEBUG 0x800D 115 116 /* AT803x supports either the XTAL input pad, an internal PLL or the 117 * DSP as clock reference for the clock output pad. The XTAL reference 118 * is only used for 25 MHz output, all other frequencies need the PLL. 119 * The DSP as a clock reference is used in synchronous ethernet 120 * applications. 121 * 122 * By default the PLL is only enabled if there is a link. Otherwise 123 * the PHY will go into low power state and disabled the PLL. You can 124 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 125 * enabled. 126 */ 127 #define AT803X_MMD7_CLK25M 0x8016 128 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 129 #define AT803X_CLK_OUT_25MHZ_XTAL 0 130 #define AT803X_CLK_OUT_25MHZ_DSP 1 131 #define AT803X_CLK_OUT_50MHZ_PLL 2 132 #define AT803X_CLK_OUT_50MHZ_DSP 3 133 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 134 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 135 #define AT803X_CLK_OUT_125MHZ_PLL 6 136 #define AT803X_CLK_OUT_125MHZ_DSP 7 137 138 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 139 * but doesn't support choosing between XTAL/PLL and DSP. 140 */ 141 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 142 143 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 144 #define AT803X_CLK_OUT_STRENGTH_FULL 0 145 #define AT803X_CLK_OUT_STRENGTH_HALF 1 146 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 147 148 #define AT803X_DEFAULT_DOWNSHIFT 5 149 #define AT803X_MIN_DOWNSHIFT 2 150 #define AT803X_MAX_DOWNSHIFT 9 151 152 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 153 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 154 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 155 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 156 157 #define ATH9331_PHY_ID 0x004dd041 158 #define ATH8030_PHY_ID 0x004dd076 159 #define ATH8031_PHY_ID 0x004dd074 160 #define ATH8032_PHY_ID 0x004dd023 161 #define ATH8035_PHY_ID 0x004dd072 162 #define AT8030_PHY_ID_MASK 0xffffffef 163 164 #define QCA8081_PHY_ID 0x004dd101 165 166 #define QCA8327_A_PHY_ID 0x004dd033 167 #define QCA8327_B_PHY_ID 0x004dd034 168 #define QCA8337_PHY_ID 0x004dd036 169 #define QCA9561_PHY_ID 0x004dd042 170 #define QCA8K_PHY_ID_MASK 0xffffffff 171 172 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 173 174 #define AT803X_PAGE_FIBER 0 175 #define AT803X_PAGE_COPPER 1 176 177 /* don't turn off internal PLL */ 178 #define AT803X_KEEP_PLL_ENABLED BIT(0) 179 #define AT803X_DISABLE_SMARTEEE BIT(1) 180 181 /* ADC threshold */ 182 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 183 #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 184 #define QCA808X_ADC_THRESHOLD_80MV 0 185 #define QCA808X_ADC_THRESHOLD_100MV 0xf0 186 #define QCA808X_ADC_THRESHOLD_200MV 0x0f 187 #define QCA808X_ADC_THRESHOLD_300MV 0xff 188 189 /* CLD control */ 190 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 191 #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 192 #define QCA808X_8023AZ_AFE_EN 0x90 193 194 /* AZ control */ 195 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 196 #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 197 198 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 199 #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 200 201 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 202 #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 203 204 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 205 #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 206 207 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 208 #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 209 210 #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 211 #define QCA808X_TOP_OPTION1_DATA 0x0 212 213 #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 214 #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 215 #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 216 #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 217 #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 218 #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 219 #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 220 #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 221 #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 222 #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 223 #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 224 #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 225 226 /* master/slave seed config */ 227 #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 228 #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 229 #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 230 #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 231 232 /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 233 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 234 */ 235 #define QCA808X_DBG_AN_TEST 0xb 236 #define QCA808X_HIBERNATION_EN BIT(15) 237 238 #define QCA808X_CDT_ENABLE_TEST BIT(15) 239 #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 240 #define QCA808X_CDT_LENGTH_UNIT BIT(10) 241 242 #define QCA808X_MMD3_CDT_STATUS 0x8064 243 #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 244 #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 245 #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 246 #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 247 #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 248 249 #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 250 #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 251 #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 252 #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 253 #define QCA808X_CDT_STATUS_STAT_FAIL 0 254 #define QCA808X_CDT_STATUS_STAT_NORMAL 1 255 #define QCA808X_CDT_STATUS_STAT_OPEN 2 256 #define QCA808X_CDT_STATUS_STAT_SHORT 3 257 258 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 259 MODULE_AUTHOR("Matus Ujhelyi"); 260 MODULE_LICENSE("GPL"); 261 262 enum stat_access_type { 263 PHY, 264 MMD 265 }; 266 267 struct at803x_hw_stat { 268 const char *string; 269 u8 reg; 270 u32 mask; 271 enum stat_access_type access_type; 272 }; 273 274 static struct at803x_hw_stat at803x_hw_stats[] = { 275 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 276 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 277 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 278 }; 279 280 struct at803x_priv { 281 int flags; 282 u16 clk_25m_reg; 283 u16 clk_25m_mask; 284 u8 smarteee_lpi_tw_1g; 285 u8 smarteee_lpi_tw_100m; 286 struct regulator_dev *vddio_rdev; 287 struct regulator_dev *vddh_rdev; 288 struct regulator *vddio; 289 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 290 }; 291 292 struct at803x_context { 293 u16 bmcr; 294 u16 advertise; 295 u16 control1000; 296 u16 int_enable; 297 u16 smart_speed; 298 u16 led_control; 299 }; 300 301 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 302 { 303 int ret; 304 305 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 306 if (ret < 0) 307 return ret; 308 309 return phy_write(phydev, AT803X_DEBUG_DATA, data); 310 } 311 312 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 313 { 314 int ret; 315 316 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 317 if (ret < 0) 318 return ret; 319 320 return phy_read(phydev, AT803X_DEBUG_DATA); 321 } 322 323 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 324 u16 clear, u16 set) 325 { 326 u16 val; 327 int ret; 328 329 ret = at803x_debug_reg_read(phydev, reg); 330 if (ret < 0) 331 return ret; 332 333 val = ret & 0xffff; 334 val &= ~clear; 335 val |= set; 336 337 return phy_write(phydev, AT803X_DEBUG_DATA, val); 338 } 339 340 static int at803x_write_page(struct phy_device *phydev, int page) 341 { 342 int mask; 343 int set; 344 345 if (page == AT803X_PAGE_COPPER) { 346 set = AT803X_BT_BX_REG_SEL; 347 mask = 0; 348 } else { 349 set = 0; 350 mask = AT803X_BT_BX_REG_SEL; 351 } 352 353 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 354 } 355 356 static int at803x_read_page(struct phy_device *phydev) 357 { 358 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 359 360 if (ccr < 0) 361 return ccr; 362 363 if (ccr & AT803X_BT_BX_REG_SEL) 364 return AT803X_PAGE_COPPER; 365 366 return AT803X_PAGE_FIBER; 367 } 368 369 static int at803x_enable_rx_delay(struct phy_device *phydev) 370 { 371 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 372 AT803X_DEBUG_RX_CLK_DLY_EN); 373 } 374 375 static int at803x_enable_tx_delay(struct phy_device *phydev) 376 { 377 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 378 AT803X_DEBUG_TX_CLK_DLY_EN); 379 } 380 381 static int at803x_disable_rx_delay(struct phy_device *phydev) 382 { 383 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 384 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 385 } 386 387 static int at803x_disable_tx_delay(struct phy_device *phydev) 388 { 389 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 390 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 391 } 392 393 /* save relevant PHY registers to private copy */ 394 static void at803x_context_save(struct phy_device *phydev, 395 struct at803x_context *context) 396 { 397 context->bmcr = phy_read(phydev, MII_BMCR); 398 context->advertise = phy_read(phydev, MII_ADVERTISE); 399 context->control1000 = phy_read(phydev, MII_CTRL1000); 400 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 401 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 402 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 403 } 404 405 /* restore relevant PHY registers from private copy */ 406 static void at803x_context_restore(struct phy_device *phydev, 407 const struct at803x_context *context) 408 { 409 phy_write(phydev, MII_BMCR, context->bmcr); 410 phy_write(phydev, MII_ADVERTISE, context->advertise); 411 phy_write(phydev, MII_CTRL1000, context->control1000); 412 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 413 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 414 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 415 } 416 417 static int at803x_set_wol(struct phy_device *phydev, 418 struct ethtool_wolinfo *wol) 419 { 420 struct net_device *ndev = phydev->attached_dev; 421 const u8 *mac; 422 int ret, irq_enabled; 423 unsigned int i; 424 static const unsigned int offsets[] = { 425 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 426 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 427 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 428 }; 429 430 if (!ndev) 431 return -ENODEV; 432 433 if (wol->wolopts & WAKE_MAGIC) { 434 mac = (const u8 *) ndev->dev_addr; 435 436 if (!is_valid_ether_addr(mac)) 437 return -EINVAL; 438 439 for (i = 0; i < 3; i++) 440 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 441 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 442 443 /* Enable WOL function */ 444 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 445 0, AT803X_WOL_EN); 446 if (ret) 447 return ret; 448 /* Enable WOL interrupt */ 449 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 450 if (ret) 451 return ret; 452 } else { 453 /* Disable WoL function */ 454 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 455 AT803X_WOL_EN, 0); 456 if (ret) 457 return ret; 458 /* Disable WOL interrupt */ 459 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 460 if (ret) 461 return ret; 462 } 463 464 /* Clear WOL status */ 465 ret = phy_read(phydev, AT803X_INTR_STATUS); 466 if (ret < 0) 467 return ret; 468 469 /* Check if there are other interrupts except for WOL triggered when PHY is 470 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 471 * be passed up to the interrupt PIN. 472 */ 473 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 474 if (irq_enabled < 0) 475 return irq_enabled; 476 477 irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 478 if (ret & irq_enabled && !phy_polling_mode(phydev)) 479 phy_trigger_machine(phydev); 480 481 return 0; 482 } 483 484 static void at803x_get_wol(struct phy_device *phydev, 485 struct ethtool_wolinfo *wol) 486 { 487 int value; 488 489 wol->supported = WAKE_MAGIC; 490 wol->wolopts = 0; 491 492 value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 493 if (value < 0) 494 return; 495 496 if (value & AT803X_WOL_EN) 497 wol->wolopts |= WAKE_MAGIC; 498 } 499 500 static int at803x_get_sset_count(struct phy_device *phydev) 501 { 502 return ARRAY_SIZE(at803x_hw_stats); 503 } 504 505 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 506 { 507 int i; 508 509 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 510 strscpy(data + i * ETH_GSTRING_LEN, 511 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 512 } 513 } 514 515 static u64 at803x_get_stat(struct phy_device *phydev, int i) 516 { 517 struct at803x_hw_stat stat = at803x_hw_stats[i]; 518 struct at803x_priv *priv = phydev->priv; 519 int val; 520 u64 ret; 521 522 if (stat.access_type == MMD) 523 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 524 else 525 val = phy_read(phydev, stat.reg); 526 527 if (val < 0) { 528 ret = U64_MAX; 529 } else { 530 val = val & stat.mask; 531 priv->stats[i] += val; 532 ret = priv->stats[i]; 533 } 534 535 return ret; 536 } 537 538 static void at803x_get_stats(struct phy_device *phydev, 539 struct ethtool_stats *stats, u64 *data) 540 { 541 int i; 542 543 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 544 data[i] = at803x_get_stat(phydev, i); 545 } 546 547 static int at803x_suspend(struct phy_device *phydev) 548 { 549 int value; 550 int wol_enabled; 551 552 value = phy_read(phydev, AT803X_INTR_ENABLE); 553 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 554 555 if (wol_enabled) 556 value = BMCR_ISOLATE; 557 else 558 value = BMCR_PDOWN; 559 560 phy_modify(phydev, MII_BMCR, 0, value); 561 562 return 0; 563 } 564 565 static int at803x_resume(struct phy_device *phydev) 566 { 567 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 568 } 569 570 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 571 unsigned int selector) 572 { 573 struct phy_device *phydev = rdev_get_drvdata(rdev); 574 575 if (selector) 576 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 577 0, AT803X_DEBUG_RGMII_1V8); 578 else 579 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 580 AT803X_DEBUG_RGMII_1V8, 0); 581 } 582 583 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 584 { 585 struct phy_device *phydev = rdev_get_drvdata(rdev); 586 int val; 587 588 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 589 if (val < 0) 590 return val; 591 592 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 593 } 594 595 static const struct regulator_ops vddio_regulator_ops = { 596 .list_voltage = regulator_list_voltage_table, 597 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 598 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 599 }; 600 601 static const unsigned int vddio_voltage_table[] = { 602 1500000, 603 1800000, 604 }; 605 606 static const struct regulator_desc vddio_desc = { 607 .name = "vddio", 608 .of_match = of_match_ptr("vddio-regulator"), 609 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 610 .volt_table = vddio_voltage_table, 611 .ops = &vddio_regulator_ops, 612 .type = REGULATOR_VOLTAGE, 613 .owner = THIS_MODULE, 614 }; 615 616 static const struct regulator_ops vddh_regulator_ops = { 617 }; 618 619 static const struct regulator_desc vddh_desc = { 620 .name = "vddh", 621 .of_match = of_match_ptr("vddh-regulator"), 622 .n_voltages = 1, 623 .fixed_uV = 2500000, 624 .ops = &vddh_regulator_ops, 625 .type = REGULATOR_VOLTAGE, 626 .owner = THIS_MODULE, 627 }; 628 629 static int at8031_register_regulators(struct phy_device *phydev) 630 { 631 struct at803x_priv *priv = phydev->priv; 632 struct device *dev = &phydev->mdio.dev; 633 struct regulator_config config = { }; 634 635 config.dev = dev; 636 config.driver_data = phydev; 637 638 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 639 if (IS_ERR(priv->vddio_rdev)) { 640 phydev_err(phydev, "failed to register VDDIO regulator\n"); 641 return PTR_ERR(priv->vddio_rdev); 642 } 643 644 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 645 if (IS_ERR(priv->vddh_rdev)) { 646 phydev_err(phydev, "failed to register VDDH regulator\n"); 647 return PTR_ERR(priv->vddh_rdev); 648 } 649 650 return 0; 651 } 652 653 static int at803x_parse_dt(struct phy_device *phydev) 654 { 655 struct device_node *node = phydev->mdio.dev.of_node; 656 struct at803x_priv *priv = phydev->priv; 657 u32 freq, strength, tw; 658 unsigned int sel; 659 int ret; 660 661 if (!IS_ENABLED(CONFIG_OF_MDIO)) 662 return 0; 663 664 if (of_property_read_bool(node, "qca,disable-smarteee")) 665 priv->flags |= AT803X_DISABLE_SMARTEEE; 666 667 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 668 if (!tw || tw > 255) { 669 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 670 return -EINVAL; 671 } 672 priv->smarteee_lpi_tw_1g = tw; 673 } 674 675 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 676 if (!tw || tw > 255) { 677 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 678 return -EINVAL; 679 } 680 priv->smarteee_lpi_tw_100m = tw; 681 } 682 683 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 684 if (!ret) { 685 switch (freq) { 686 case 25000000: 687 sel = AT803X_CLK_OUT_25MHZ_XTAL; 688 break; 689 case 50000000: 690 sel = AT803X_CLK_OUT_50MHZ_PLL; 691 break; 692 case 62500000: 693 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 694 break; 695 case 125000000: 696 sel = AT803X_CLK_OUT_125MHZ_PLL; 697 break; 698 default: 699 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 700 return -EINVAL; 701 } 702 703 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 704 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 705 706 /* Fixup for the AR8030/AR8035. This chip has another mask and 707 * doesn't support the DSP reference. Eg. the lowest bit of the 708 * mask. The upper two bits select the same frequencies. Mask 709 * the lowest bit here. 710 * 711 * Warning: 712 * There was no datasheet for the AR8030 available so this is 713 * just a guess. But the AR8035 is listed as pin compatible 714 * to the AR8030 so there might be a good chance it works on 715 * the AR8030 too. 716 */ 717 if (phydev->drv->phy_id == ATH8030_PHY_ID || 718 phydev->drv->phy_id == ATH8035_PHY_ID) { 719 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 720 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 721 } 722 } 723 724 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 725 if (!ret) { 726 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 727 switch (strength) { 728 case AR803X_STRENGTH_FULL: 729 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 730 break; 731 case AR803X_STRENGTH_HALF: 732 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 733 break; 734 case AR803X_STRENGTH_QUARTER: 735 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 736 break; 737 default: 738 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 739 return -EINVAL; 740 } 741 } 742 743 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 744 * options. 745 */ 746 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 747 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 748 priv->flags |= AT803X_KEEP_PLL_ENABLED; 749 750 ret = at8031_register_regulators(phydev); 751 if (ret < 0) 752 return ret; 753 754 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 755 "vddio"); 756 if (IS_ERR(priv->vddio)) { 757 phydev_err(phydev, "failed to get VDDIO regulator\n"); 758 return PTR_ERR(priv->vddio); 759 } 760 } 761 762 return 0; 763 } 764 765 static int at803x_probe(struct phy_device *phydev) 766 { 767 struct device *dev = &phydev->mdio.dev; 768 struct at803x_priv *priv; 769 int ret; 770 771 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 772 if (!priv) 773 return -ENOMEM; 774 775 phydev->priv = priv; 776 777 ret = at803x_parse_dt(phydev); 778 if (ret) 779 return ret; 780 781 if (priv->vddio) { 782 ret = regulator_enable(priv->vddio); 783 if (ret < 0) 784 return ret; 785 } 786 787 /* Some bootloaders leave the fiber page selected. 788 * Switch to the copper page, as otherwise we read 789 * the PHY capabilities from the fiber side. 790 */ 791 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 792 phy_lock_mdio_bus(phydev); 793 ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); 794 phy_unlock_mdio_bus(phydev); 795 if (ret) 796 goto err; 797 } 798 799 return 0; 800 801 err: 802 if (priv->vddio) 803 regulator_disable(priv->vddio); 804 805 return ret; 806 } 807 808 static void at803x_remove(struct phy_device *phydev) 809 { 810 struct at803x_priv *priv = phydev->priv; 811 812 if (priv->vddio) 813 regulator_disable(priv->vddio); 814 } 815 816 static int at803x_get_features(struct phy_device *phydev) 817 { 818 int err; 819 820 err = genphy_read_abilities(phydev); 821 if (err) 822 return err; 823 824 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 825 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); 826 if (err < 0) 827 return err; 828 829 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 830 err & MDIO_PMA_NG_EXTABLE_2_5GBT); 831 } 832 833 if (phydev->drv->phy_id != ATH8031_PHY_ID) 834 return 0; 835 836 /* AR8031/AR8033 have different status registers 837 * for copper and fiber operation. However, the 838 * extended status register is the same for both 839 * operation modes. 840 * 841 * As a result of that, ESTATUS_1000_XFULL is set 842 * to 1 even when operating in copper TP mode. 843 * 844 * Remove this mode from the supported link modes, 845 * as this driver currently only supports copper 846 * operation. 847 */ 848 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 849 phydev->supported); 850 return 0; 851 } 852 853 static int at803x_smarteee_config(struct phy_device *phydev) 854 { 855 struct at803x_priv *priv = phydev->priv; 856 u16 mask = 0, val = 0; 857 int ret; 858 859 if (priv->flags & AT803X_DISABLE_SMARTEEE) 860 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 861 AT803X_MMD3_SMARTEEE_CTL3, 862 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 863 864 if (priv->smarteee_lpi_tw_1g) { 865 mask |= 0xff00; 866 val |= priv->smarteee_lpi_tw_1g << 8; 867 } 868 if (priv->smarteee_lpi_tw_100m) { 869 mask |= 0x00ff; 870 val |= priv->smarteee_lpi_tw_100m; 871 } 872 if (!mask) 873 return 0; 874 875 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 876 mask, val); 877 if (ret) 878 return ret; 879 880 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 881 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 882 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 883 } 884 885 static int at803x_clk_out_config(struct phy_device *phydev) 886 { 887 struct at803x_priv *priv = phydev->priv; 888 889 if (!priv->clk_25m_mask) 890 return 0; 891 892 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 893 priv->clk_25m_mask, priv->clk_25m_reg); 894 } 895 896 static int at8031_pll_config(struct phy_device *phydev) 897 { 898 struct at803x_priv *priv = phydev->priv; 899 900 /* The default after hardware reset is PLL OFF. After a soft reset, the 901 * values are retained. 902 */ 903 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 904 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 905 0, AT803X_DEBUG_PLL_ON); 906 else 907 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 908 AT803X_DEBUG_PLL_ON, 0); 909 } 910 911 static int at803x_config_init(struct phy_device *phydev) 912 { 913 int ret; 914 915 /* The RX and TX delay default is: 916 * after HW reset: RX delay enabled and TX delay disabled 917 * after SW reset: RX delay enabled, while TX delay retains the 918 * value before reset. 919 */ 920 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 921 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 922 ret = at803x_enable_rx_delay(phydev); 923 else 924 ret = at803x_disable_rx_delay(phydev); 925 if (ret < 0) 926 return ret; 927 928 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 929 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 930 ret = at803x_enable_tx_delay(phydev); 931 else 932 ret = at803x_disable_tx_delay(phydev); 933 if (ret < 0) 934 return ret; 935 936 ret = at803x_smarteee_config(phydev); 937 if (ret < 0) 938 return ret; 939 940 ret = at803x_clk_out_config(phydev); 941 if (ret < 0) 942 return ret; 943 944 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 945 ret = at8031_pll_config(phydev); 946 if (ret < 0) 947 return ret; 948 } 949 950 /* Ar803x extended next page bit is enabled by default. Cisco 951 * multigig switches read this bit and attempt to negotiate 10Gbps 952 * rates even if the next page bit is disabled. This is incorrect 953 * behaviour but we still need to accommodate it. XNP is only needed 954 * for 10Gbps support, so disable XNP. 955 */ 956 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 957 } 958 959 static int at803x_ack_interrupt(struct phy_device *phydev) 960 { 961 int err; 962 963 err = phy_read(phydev, AT803X_INTR_STATUS); 964 965 return (err < 0) ? err : 0; 966 } 967 968 static int at803x_config_intr(struct phy_device *phydev) 969 { 970 int err; 971 int value; 972 973 value = phy_read(phydev, AT803X_INTR_ENABLE); 974 975 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 976 /* Clear any pending interrupts */ 977 err = at803x_ack_interrupt(phydev); 978 if (err) 979 return err; 980 981 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 982 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 983 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 984 value |= AT803X_INTR_ENABLE_LINK_FAIL; 985 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 986 987 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 988 } else { 989 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 990 if (err) 991 return err; 992 993 /* Clear any pending interrupts */ 994 err = at803x_ack_interrupt(phydev); 995 } 996 997 return err; 998 } 999 1000 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 1001 { 1002 int irq_status, int_enabled; 1003 1004 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 1005 if (irq_status < 0) { 1006 phy_error(phydev); 1007 return IRQ_NONE; 1008 } 1009 1010 /* Read the current enabled interrupts */ 1011 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 1012 if (int_enabled < 0) { 1013 phy_error(phydev); 1014 return IRQ_NONE; 1015 } 1016 1017 /* See if this was one of our enabled interrupts */ 1018 if (!(irq_status & int_enabled)) 1019 return IRQ_NONE; 1020 1021 phy_trigger_machine(phydev); 1022 1023 return IRQ_HANDLED; 1024 } 1025 1026 static void at803x_link_change_notify(struct phy_device *phydev) 1027 { 1028 /* 1029 * Conduct a hardware reset for AT8030 every time a link loss is 1030 * signalled. This is necessary to circumvent a hardware bug that 1031 * occurs when the cable is unplugged while TX packets are pending 1032 * in the FIFO. In such cases, the FIFO enters an error mode it 1033 * cannot recover from by software. 1034 */ 1035 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 1036 struct at803x_context context; 1037 1038 at803x_context_save(phydev, &context); 1039 1040 phy_device_reset(phydev, 1); 1041 msleep(1); 1042 phy_device_reset(phydev, 0); 1043 msleep(1); 1044 1045 at803x_context_restore(phydev, &context); 1046 1047 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 1048 } 1049 } 1050 1051 static int at803x_read_specific_status(struct phy_device *phydev) 1052 { 1053 int ss; 1054 1055 /* Read the AT8035 PHY-Specific Status register, which indicates the 1056 * speed and duplex that the PHY is actually using, irrespective of 1057 * whether we are in autoneg mode or not. 1058 */ 1059 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 1060 if (ss < 0) 1061 return ss; 1062 1063 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 1064 int sfc, speed; 1065 1066 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 1067 if (sfc < 0) 1068 return sfc; 1069 1070 /* qca8081 takes the different bits for speed value from at803x */ 1071 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1072 speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 1073 else 1074 speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 1075 1076 switch (speed) { 1077 case AT803X_SS_SPEED_10: 1078 phydev->speed = SPEED_10; 1079 break; 1080 case AT803X_SS_SPEED_100: 1081 phydev->speed = SPEED_100; 1082 break; 1083 case AT803X_SS_SPEED_1000: 1084 phydev->speed = SPEED_1000; 1085 break; 1086 case QCA808X_SS_SPEED_2500: 1087 phydev->speed = SPEED_2500; 1088 break; 1089 } 1090 if (ss & AT803X_SS_DUPLEX) 1091 phydev->duplex = DUPLEX_FULL; 1092 else 1093 phydev->duplex = DUPLEX_HALF; 1094 1095 if (ss & AT803X_SS_MDIX) 1096 phydev->mdix = ETH_TP_MDI_X; 1097 else 1098 phydev->mdix = ETH_TP_MDI; 1099 1100 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 1101 case AT803X_SFC_MANUAL_MDI: 1102 phydev->mdix_ctrl = ETH_TP_MDI; 1103 break; 1104 case AT803X_SFC_MANUAL_MDIX: 1105 phydev->mdix_ctrl = ETH_TP_MDI_X; 1106 break; 1107 case AT803X_SFC_AUTOMATIC_CROSSOVER: 1108 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1109 break; 1110 } 1111 } 1112 1113 return 0; 1114 } 1115 1116 static int at803x_read_status(struct phy_device *phydev) 1117 { 1118 int err, old_link = phydev->link; 1119 1120 /* Update the link, but return if there was an error */ 1121 err = genphy_update_link(phydev); 1122 if (err) 1123 return err; 1124 1125 /* why bother the PHY if nothing can have changed */ 1126 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 1127 return 0; 1128 1129 phydev->speed = SPEED_UNKNOWN; 1130 phydev->duplex = DUPLEX_UNKNOWN; 1131 phydev->pause = 0; 1132 phydev->asym_pause = 0; 1133 1134 err = genphy_read_lpa(phydev); 1135 if (err < 0) 1136 return err; 1137 1138 err = at803x_read_specific_status(phydev); 1139 if (err < 0) 1140 return err; 1141 1142 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1143 phy_resolve_aneg_pause(phydev); 1144 1145 return 0; 1146 } 1147 1148 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 1149 { 1150 u16 val; 1151 1152 switch (ctrl) { 1153 case ETH_TP_MDI: 1154 val = AT803X_SFC_MANUAL_MDI; 1155 break; 1156 case ETH_TP_MDI_X: 1157 val = AT803X_SFC_MANUAL_MDIX; 1158 break; 1159 case ETH_TP_MDI_AUTO: 1160 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 1161 break; 1162 default: 1163 return 0; 1164 } 1165 1166 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 1167 AT803X_SFC_MDI_CROSSOVER_MODE_M, 1168 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1169 } 1170 1171 static int at803x_config_aneg(struct phy_device *phydev) 1172 { 1173 int ret; 1174 1175 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1176 if (ret < 0) 1177 return ret; 1178 1179 /* Changes of the midx bits are disruptive to the normal operation; 1180 * therefore any changes to these registers must be followed by a 1181 * software reset to take effect. 1182 */ 1183 if (ret == 1) { 1184 ret = genphy_soft_reset(phydev); 1185 if (ret < 0) 1186 return ret; 1187 } 1188 1189 /* Do not restart auto-negotiation by setting ret to 0 defautly, 1190 * when calling __genphy_config_aneg later. 1191 */ 1192 ret = 0; 1193 1194 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1195 int phy_ctrl = 0; 1196 1197 /* The reg MII_BMCR also needs to be configured for force mode, the 1198 * genphy_config_aneg is also needed. 1199 */ 1200 if (phydev->autoneg == AUTONEG_DISABLE) 1201 genphy_c45_pma_setup_forced(phydev); 1202 1203 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1204 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1205 1206 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1207 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1208 if (ret < 0) 1209 return ret; 1210 } 1211 1212 return __genphy_config_aneg(phydev, ret); 1213 } 1214 1215 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1216 { 1217 int val; 1218 1219 val = phy_read(phydev, AT803X_SMART_SPEED); 1220 if (val < 0) 1221 return val; 1222 1223 if (val & AT803X_SMART_SPEED_ENABLE) 1224 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1225 else 1226 *d = DOWNSHIFT_DEV_DISABLE; 1227 1228 return 0; 1229 } 1230 1231 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1232 { 1233 u16 mask, set; 1234 int ret; 1235 1236 switch (cnt) { 1237 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1238 cnt = AT803X_DEFAULT_DOWNSHIFT; 1239 fallthrough; 1240 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1241 set = AT803X_SMART_SPEED_ENABLE | 1242 AT803X_SMART_SPEED_BYPASS_TIMER | 1243 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1244 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1245 break; 1246 case DOWNSHIFT_DEV_DISABLE: 1247 set = 0; 1248 mask = AT803X_SMART_SPEED_ENABLE | 1249 AT803X_SMART_SPEED_BYPASS_TIMER; 1250 break; 1251 default: 1252 return -EINVAL; 1253 } 1254 1255 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1256 1257 /* After changing the smart speed settings, we need to perform a 1258 * software reset, use phy_init_hw() to make sure we set the 1259 * reapply any values which might got lost during software reset. 1260 */ 1261 if (ret == 1) 1262 ret = phy_init_hw(phydev); 1263 1264 return ret; 1265 } 1266 1267 static int at803x_get_tunable(struct phy_device *phydev, 1268 struct ethtool_tunable *tuna, void *data) 1269 { 1270 switch (tuna->id) { 1271 case ETHTOOL_PHY_DOWNSHIFT: 1272 return at803x_get_downshift(phydev, data); 1273 default: 1274 return -EOPNOTSUPP; 1275 } 1276 } 1277 1278 static int at803x_set_tunable(struct phy_device *phydev, 1279 struct ethtool_tunable *tuna, const void *data) 1280 { 1281 switch (tuna->id) { 1282 case ETHTOOL_PHY_DOWNSHIFT: 1283 return at803x_set_downshift(phydev, *(const u8 *)data); 1284 default: 1285 return -EOPNOTSUPP; 1286 } 1287 } 1288 1289 static int at803x_cable_test_result_trans(u16 status) 1290 { 1291 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1292 case AT803X_CDT_STATUS_STAT_NORMAL: 1293 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1294 case AT803X_CDT_STATUS_STAT_SHORT: 1295 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1296 case AT803X_CDT_STATUS_STAT_OPEN: 1297 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1298 case AT803X_CDT_STATUS_STAT_FAIL: 1299 default: 1300 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1301 } 1302 } 1303 1304 static bool at803x_cdt_test_failed(u16 status) 1305 { 1306 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1307 AT803X_CDT_STATUS_STAT_FAIL; 1308 } 1309 1310 static bool at803x_cdt_fault_length_valid(u16 status) 1311 { 1312 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1313 case AT803X_CDT_STATUS_STAT_OPEN: 1314 case AT803X_CDT_STATUS_STAT_SHORT: 1315 return true; 1316 } 1317 return false; 1318 } 1319 1320 static int at803x_cdt_fault_length(u16 status) 1321 { 1322 int dt; 1323 1324 /* According to the datasheet the distance to the fault is 1325 * DELTA_TIME * 0.824 meters. 1326 * 1327 * The author suspect the correct formula is: 1328 * 1329 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1330 * 1331 * where c is the speed of light, VF is the velocity factor of 1332 * the twisted pair cable, 125MHz the counter frequency and 1333 * we need to divide by 2 because the hardware will measure the 1334 * round trip time to the fault and back to the PHY. 1335 * 1336 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1337 * datasheet. 1338 */ 1339 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1340 1341 return (dt * 824) / 10; 1342 } 1343 1344 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1345 { 1346 u16 cdt; 1347 1348 /* qca8081 takes the different bit 15 to enable CDT test */ 1349 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1350 cdt = QCA808X_CDT_ENABLE_TEST | 1351 QCA808X_CDT_LENGTH_UNIT | 1352 QCA808X_CDT_INTER_CHECK_DIS; 1353 else 1354 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1355 AT803X_CDT_ENABLE_TEST; 1356 1357 return phy_write(phydev, AT803X_CDT, cdt); 1358 } 1359 1360 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1361 { 1362 int val, ret; 1363 u16 cdt_en; 1364 1365 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1366 cdt_en = QCA808X_CDT_ENABLE_TEST; 1367 else 1368 cdt_en = AT803X_CDT_ENABLE_TEST; 1369 1370 /* One test run takes about 25ms */ 1371 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1372 !(val & cdt_en), 1373 30000, 100000, true); 1374 1375 return ret < 0 ? ret : 0; 1376 } 1377 1378 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1379 { 1380 static const int ethtool_pair[] = { 1381 ETHTOOL_A_CABLE_PAIR_A, 1382 ETHTOOL_A_CABLE_PAIR_B, 1383 ETHTOOL_A_CABLE_PAIR_C, 1384 ETHTOOL_A_CABLE_PAIR_D, 1385 }; 1386 int ret, val; 1387 1388 ret = at803x_cdt_start(phydev, pair); 1389 if (ret) 1390 return ret; 1391 1392 ret = at803x_cdt_wait_for_completion(phydev); 1393 if (ret) 1394 return ret; 1395 1396 val = phy_read(phydev, AT803X_CDT_STATUS); 1397 if (val < 0) 1398 return val; 1399 1400 if (at803x_cdt_test_failed(val)) 1401 return 0; 1402 1403 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1404 at803x_cable_test_result_trans(val)); 1405 1406 if (at803x_cdt_fault_length_valid(val)) 1407 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1408 at803x_cdt_fault_length(val)); 1409 1410 return 1; 1411 } 1412 1413 static int at803x_cable_test_get_status(struct phy_device *phydev, 1414 bool *finished) 1415 { 1416 unsigned long pair_mask; 1417 int retries = 20; 1418 int pair, ret; 1419 1420 if (phydev->phy_id == ATH9331_PHY_ID || 1421 phydev->phy_id == ATH8032_PHY_ID || 1422 phydev->phy_id == QCA9561_PHY_ID) 1423 pair_mask = 0x3; 1424 else 1425 pair_mask = 0xf; 1426 1427 *finished = false; 1428 1429 /* According to the datasheet the CDT can be performed when 1430 * there is no link partner or when the link partner is 1431 * auto-negotiating. Starting the test will restart the AN 1432 * automatically. It seems that doing this repeatedly we will 1433 * get a slot where our link partner won't disturb our 1434 * measurement. 1435 */ 1436 while (pair_mask && retries--) { 1437 for_each_set_bit(pair, &pair_mask, 4) { 1438 ret = at803x_cable_test_one_pair(phydev, pair); 1439 if (ret < 0) 1440 return ret; 1441 if (ret) 1442 clear_bit(pair, &pair_mask); 1443 } 1444 if (pair_mask) 1445 msleep(250); 1446 } 1447 1448 *finished = true; 1449 1450 return 0; 1451 } 1452 1453 static int at803x_cable_test_start(struct phy_device *phydev) 1454 { 1455 /* Enable auto-negotiation, but advertise no capabilities, no link 1456 * will be established. A restart of the auto-negotiation is not 1457 * required, because the cable test will automatically break the link. 1458 */ 1459 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1460 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1461 if (phydev->phy_id != ATH9331_PHY_ID && 1462 phydev->phy_id != ATH8032_PHY_ID && 1463 phydev->phy_id != QCA9561_PHY_ID) 1464 phy_write(phydev, MII_CTRL1000, 0); 1465 1466 /* we do all the (time consuming) work later */ 1467 return 0; 1468 } 1469 1470 static int qca83xx_config_init(struct phy_device *phydev) 1471 { 1472 u8 switch_revision; 1473 1474 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1475 1476 switch (switch_revision) { 1477 case 1: 1478 /* For 100M waveform */ 1479 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1480 /* Turn on Gigabit clock */ 1481 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1482 break; 1483 1484 case 2: 1485 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1486 fallthrough; 1487 case 4: 1488 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1489 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 1490 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1491 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1492 break; 1493 } 1494 1495 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 1496 * Disable on init and enable only with 100m speed following 1497 * qca original source code. 1498 */ 1499 if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 1500 phydev->drv->phy_id == QCA8327_B_PHY_ID) 1501 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1502 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1503 1504 /* Following original QCA sourcecode set port to prefer master */ 1505 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 1506 1507 return 0; 1508 } 1509 1510 static void qca83xx_link_change_notify(struct phy_device *phydev) 1511 { 1512 /* QCA8337 doesn't require DAC Amplitude adjustement */ 1513 if (phydev->drv->phy_id == QCA8337_PHY_ID) 1514 return; 1515 1516 /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 1517 if (phydev->state == PHY_RUNNING) { 1518 if (phydev->speed == SPEED_100) 1519 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1520 QCA8327_DEBUG_MANU_CTRL_EN, 1521 QCA8327_DEBUG_MANU_CTRL_EN); 1522 } else { 1523 /* Reset DAC Amplitude adjustment */ 1524 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1525 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1526 } 1527 } 1528 1529 static int qca83xx_resume(struct phy_device *phydev) 1530 { 1531 int ret, val; 1532 1533 /* Skip reset if not suspended */ 1534 if (!phydev->suspended) 1535 return 0; 1536 1537 /* Reinit the port, reset values set by suspend */ 1538 qca83xx_config_init(phydev); 1539 1540 /* Reset the port on port resume */ 1541 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1542 1543 /* On resume from suspend the switch execute a reset and 1544 * restart auto-negotiation. Wait for reset to complete. 1545 */ 1546 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1547 50000, 600000, true); 1548 if (ret) 1549 return ret; 1550 1551 msleep(1); 1552 1553 return 0; 1554 } 1555 1556 static int qca83xx_suspend(struct phy_device *phydev) 1557 { 1558 u16 mask = 0; 1559 1560 /* Only QCA8337 support actual suspend. 1561 * QCA8327 cause port unreliability when phy suspend 1562 * is set. 1563 */ 1564 if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1565 genphy_suspend(phydev); 1566 } else { 1567 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1568 phy_modify(phydev, MII_BMCR, mask, 0); 1569 } 1570 1571 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1572 AT803X_DEBUG_GATE_CLK_IN1000, 0); 1573 1574 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1575 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1576 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1577 1578 return 0; 1579 } 1580 1581 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 1582 { 1583 int ret; 1584 1585 /* Enable fast retrain */ 1586 ret = genphy_c45_fast_retrain(phydev, true); 1587 if (ret) 1588 return ret; 1589 1590 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 1591 QCA808X_TOP_OPTION1_DATA); 1592 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 1593 QCA808X_MSE_THRESHOLD_20DB_VALUE); 1594 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 1595 QCA808X_MSE_THRESHOLD_17DB_VALUE); 1596 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 1597 QCA808X_MSE_THRESHOLD_27DB_VALUE); 1598 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 1599 QCA808X_MSE_THRESHOLD_28DB_VALUE); 1600 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 1601 QCA808X_MMD3_DEBUG_1_VALUE); 1602 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 1603 QCA808X_MMD3_DEBUG_4_VALUE); 1604 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 1605 QCA808X_MMD3_DEBUG_5_VALUE); 1606 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 1607 QCA808X_MMD3_DEBUG_3_VALUE); 1608 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 1609 QCA808X_MMD3_DEBUG_6_VALUE); 1610 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 1611 QCA808X_MMD3_DEBUG_2_VALUE); 1612 1613 return 0; 1614 } 1615 1616 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) 1617 { 1618 u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE); 1619 1620 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1621 QCA808X_MASTER_SLAVE_SEED_CFG, 1622 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); 1623 } 1624 1625 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 1626 { 1627 u16 seed_enable = 0; 1628 1629 if (enable) 1630 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; 1631 1632 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1633 QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); 1634 } 1635 1636 static int qca808x_config_init(struct phy_device *phydev) 1637 { 1638 int ret; 1639 1640 /* Active adc&vga on 802.3az for the link 1000M and 100M */ 1641 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 1642 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 1643 if (ret) 1644 return ret; 1645 1646 /* Adjust the threshold on 802.3az for the link 1000M */ 1647 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 1648 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 1649 if (ret) 1650 return ret; 1651 1652 /* Config the fast retrain for the link 2500M */ 1653 ret = qca808x_phy_fast_retrain_config(phydev); 1654 if (ret) 1655 return ret; 1656 1657 /* Configure lower ramdom seed to make phy linked as slave mode */ 1658 ret = qca808x_phy_ms_random_seed_set(phydev); 1659 if (ret) 1660 return ret; 1661 1662 /* Enable seed */ 1663 ret = qca808x_phy_ms_seed_enable(phydev, true); 1664 if (ret) 1665 return ret; 1666 1667 /* Configure adc threshold as 100mv for the link 10M */ 1668 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 1669 QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 1670 } 1671 1672 static int qca808x_read_status(struct phy_device *phydev) 1673 { 1674 int ret; 1675 1676 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1677 if (ret < 0) 1678 return ret; 1679 1680 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 1681 ret & MDIO_AN_10GBT_STAT_LP2_5G); 1682 1683 ret = genphy_read_status(phydev); 1684 if (ret) 1685 return ret; 1686 1687 ret = at803x_read_specific_status(phydev); 1688 if (ret < 0) 1689 return ret; 1690 1691 if (phydev->link) { 1692 if (phydev->speed == SPEED_2500) 1693 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1694 else 1695 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1696 } else { 1697 /* generate seed as a lower random value to make PHY linked as SLAVE easily, 1698 * except for master/slave configuration fault detected. 1699 * the reason for not putting this code into the function link_change_notify is 1700 * the corner case where the link partner is also the qca8081 PHY and the seed 1701 * value is configured as the same value, the link can't be up and no link change 1702 * occurs. 1703 */ 1704 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { 1705 qca808x_phy_ms_seed_enable(phydev, false); 1706 } else { 1707 qca808x_phy_ms_random_seed_set(phydev); 1708 qca808x_phy_ms_seed_enable(phydev, true); 1709 } 1710 } 1711 1712 return 0; 1713 } 1714 1715 static int qca808x_soft_reset(struct phy_device *phydev) 1716 { 1717 int ret; 1718 1719 ret = genphy_soft_reset(phydev); 1720 if (ret < 0) 1721 return ret; 1722 1723 return qca808x_phy_ms_seed_enable(phydev, true); 1724 } 1725 1726 static bool qca808x_cdt_fault_length_valid(int cdt_code) 1727 { 1728 switch (cdt_code) { 1729 case QCA808X_CDT_STATUS_STAT_SHORT: 1730 case QCA808X_CDT_STATUS_STAT_OPEN: 1731 return true; 1732 default: 1733 return false; 1734 } 1735 } 1736 1737 static int qca808x_cable_test_result_trans(int cdt_code) 1738 { 1739 switch (cdt_code) { 1740 case QCA808X_CDT_STATUS_STAT_NORMAL: 1741 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1742 case QCA808X_CDT_STATUS_STAT_SHORT: 1743 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1744 case QCA808X_CDT_STATUS_STAT_OPEN: 1745 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1746 case QCA808X_CDT_STATUS_STAT_FAIL: 1747 default: 1748 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1749 } 1750 } 1751 1752 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 1753 { 1754 int val; 1755 u32 cdt_length_reg = 0; 1756 1757 switch (pair) { 1758 case ETHTOOL_A_CABLE_PAIR_A: 1759 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 1760 break; 1761 case ETHTOOL_A_CABLE_PAIR_B: 1762 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 1763 break; 1764 case ETHTOOL_A_CABLE_PAIR_C: 1765 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 1766 break; 1767 case ETHTOOL_A_CABLE_PAIR_D: 1768 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 1769 break; 1770 default: 1771 return -EINVAL; 1772 } 1773 1774 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 1775 if (val < 0) 1776 return val; 1777 1778 return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 1779 } 1780 1781 static int qca808x_cable_test_start(struct phy_device *phydev) 1782 { 1783 int ret; 1784 1785 /* perform CDT with the following configs: 1786 * 1. disable hibernation. 1787 * 2. force PHY working in MDI mode. 1788 * 3. for PHY working in 1000BaseT. 1789 * 4. configure the threshold. 1790 */ 1791 1792 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 1793 if (ret < 0) 1794 return ret; 1795 1796 ret = at803x_config_mdix(phydev, ETH_TP_MDI); 1797 if (ret < 0) 1798 return ret; 1799 1800 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 1801 phydev->duplex = DUPLEX_FULL; 1802 phydev->speed = SPEED_1000; 1803 ret = genphy_c45_pma_setup_forced(phydev); 1804 if (ret < 0) 1805 return ret; 1806 1807 ret = genphy_setup_forced(phydev); 1808 if (ret < 0) 1809 return ret; 1810 1811 /* configure the thresholds for open, short, pair ok test */ 1812 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 1813 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 1814 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 1815 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 1816 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 1817 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 1818 1819 return 0; 1820 } 1821 1822 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 1823 { 1824 int ret, val; 1825 int pair_a, pair_b, pair_c, pair_d; 1826 1827 *finished = false; 1828 1829 ret = at803x_cdt_start(phydev, 0); 1830 if (ret) 1831 return ret; 1832 1833 ret = at803x_cdt_wait_for_completion(phydev); 1834 if (ret) 1835 return ret; 1836 1837 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 1838 if (val < 0) 1839 return val; 1840 1841 pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 1842 pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 1843 pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 1844 pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 1845 1846 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1847 qca808x_cable_test_result_trans(pair_a)); 1848 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 1849 qca808x_cable_test_result_trans(pair_b)); 1850 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 1851 qca808x_cable_test_result_trans(pair_c)); 1852 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 1853 qca808x_cable_test_result_trans(pair_d)); 1854 1855 if (qca808x_cdt_fault_length_valid(pair_a)) 1856 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 1857 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 1858 if (qca808x_cdt_fault_length_valid(pair_b)) 1859 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 1860 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 1861 if (qca808x_cdt_fault_length_valid(pair_c)) 1862 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 1863 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 1864 if (qca808x_cdt_fault_length_valid(pair_d)) 1865 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 1866 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 1867 1868 *finished = true; 1869 1870 return 0; 1871 } 1872 1873 static struct phy_driver at803x_driver[] = { 1874 { 1875 /* Qualcomm Atheros AR8035 */ 1876 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1877 .name = "Qualcomm Atheros AR8035", 1878 .flags = PHY_POLL_CABLE_TEST, 1879 .probe = at803x_probe, 1880 .remove = at803x_remove, 1881 .config_aneg = at803x_config_aneg, 1882 .config_init = at803x_config_init, 1883 .soft_reset = genphy_soft_reset, 1884 .set_wol = at803x_set_wol, 1885 .get_wol = at803x_get_wol, 1886 .suspend = at803x_suspend, 1887 .resume = at803x_resume, 1888 /* PHY_GBIT_FEATURES */ 1889 .read_status = at803x_read_status, 1890 .config_intr = at803x_config_intr, 1891 .handle_interrupt = at803x_handle_interrupt, 1892 .get_tunable = at803x_get_tunable, 1893 .set_tunable = at803x_set_tunable, 1894 .cable_test_start = at803x_cable_test_start, 1895 .cable_test_get_status = at803x_cable_test_get_status, 1896 }, { 1897 /* Qualcomm Atheros AR8030 */ 1898 .phy_id = ATH8030_PHY_ID, 1899 .name = "Qualcomm Atheros AR8030", 1900 .phy_id_mask = AT8030_PHY_ID_MASK, 1901 .probe = at803x_probe, 1902 .remove = at803x_remove, 1903 .config_init = at803x_config_init, 1904 .link_change_notify = at803x_link_change_notify, 1905 .set_wol = at803x_set_wol, 1906 .get_wol = at803x_get_wol, 1907 .suspend = at803x_suspend, 1908 .resume = at803x_resume, 1909 /* PHY_BASIC_FEATURES */ 1910 .config_intr = at803x_config_intr, 1911 .handle_interrupt = at803x_handle_interrupt, 1912 }, { 1913 /* Qualcomm Atheros AR8031/AR8033 */ 1914 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1915 .name = "Qualcomm Atheros AR8031/AR8033", 1916 .flags = PHY_POLL_CABLE_TEST, 1917 .probe = at803x_probe, 1918 .remove = at803x_remove, 1919 .config_init = at803x_config_init, 1920 .config_aneg = at803x_config_aneg, 1921 .soft_reset = genphy_soft_reset, 1922 .set_wol = at803x_set_wol, 1923 .get_wol = at803x_get_wol, 1924 .suspend = at803x_suspend, 1925 .resume = at803x_resume, 1926 .read_page = at803x_read_page, 1927 .write_page = at803x_write_page, 1928 .get_features = at803x_get_features, 1929 .read_status = at803x_read_status, 1930 .config_intr = &at803x_config_intr, 1931 .handle_interrupt = at803x_handle_interrupt, 1932 .get_tunable = at803x_get_tunable, 1933 .set_tunable = at803x_set_tunable, 1934 .cable_test_start = at803x_cable_test_start, 1935 .cable_test_get_status = at803x_cable_test_get_status, 1936 }, { 1937 /* Qualcomm Atheros AR8032 */ 1938 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1939 .name = "Qualcomm Atheros AR8032", 1940 .probe = at803x_probe, 1941 .remove = at803x_remove, 1942 .flags = PHY_POLL_CABLE_TEST, 1943 .config_init = at803x_config_init, 1944 .link_change_notify = at803x_link_change_notify, 1945 .set_wol = at803x_set_wol, 1946 .get_wol = at803x_get_wol, 1947 .suspend = at803x_suspend, 1948 .resume = at803x_resume, 1949 /* PHY_BASIC_FEATURES */ 1950 .config_intr = at803x_config_intr, 1951 .handle_interrupt = at803x_handle_interrupt, 1952 .cable_test_start = at803x_cable_test_start, 1953 .cable_test_get_status = at803x_cable_test_get_status, 1954 }, { 1955 /* ATHEROS AR9331 */ 1956 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1957 .name = "Qualcomm Atheros AR9331 built-in PHY", 1958 .suspend = at803x_suspend, 1959 .resume = at803x_resume, 1960 .flags = PHY_POLL_CABLE_TEST, 1961 /* PHY_BASIC_FEATURES */ 1962 .config_intr = &at803x_config_intr, 1963 .handle_interrupt = at803x_handle_interrupt, 1964 .cable_test_start = at803x_cable_test_start, 1965 .cable_test_get_status = at803x_cable_test_get_status, 1966 .read_status = at803x_read_status, 1967 .soft_reset = genphy_soft_reset, 1968 .config_aneg = at803x_config_aneg, 1969 }, { 1970 /* Qualcomm Atheros QCA9561 */ 1971 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 1972 .name = "Qualcomm Atheros QCA9561 built-in PHY", 1973 .suspend = at803x_suspend, 1974 .resume = at803x_resume, 1975 .flags = PHY_POLL_CABLE_TEST, 1976 /* PHY_BASIC_FEATURES */ 1977 .config_intr = &at803x_config_intr, 1978 .handle_interrupt = at803x_handle_interrupt, 1979 .cable_test_start = at803x_cable_test_start, 1980 .cable_test_get_status = at803x_cable_test_get_status, 1981 .read_status = at803x_read_status, 1982 .soft_reset = genphy_soft_reset, 1983 .config_aneg = at803x_config_aneg, 1984 }, { 1985 /* QCA8337 */ 1986 .phy_id = QCA8337_PHY_ID, 1987 .phy_id_mask = QCA8K_PHY_ID_MASK, 1988 .name = "Qualcomm Atheros 8337 internal PHY", 1989 /* PHY_GBIT_FEATURES */ 1990 .link_change_notify = qca83xx_link_change_notify, 1991 .probe = at803x_probe, 1992 .flags = PHY_IS_INTERNAL, 1993 .config_init = qca83xx_config_init, 1994 .soft_reset = genphy_soft_reset, 1995 .get_sset_count = at803x_get_sset_count, 1996 .get_strings = at803x_get_strings, 1997 .get_stats = at803x_get_stats, 1998 .suspend = qca83xx_suspend, 1999 .resume = qca83xx_resume, 2000 }, { 2001 /* QCA8327-A from switch QCA8327-AL1A */ 2002 .phy_id = QCA8327_A_PHY_ID, 2003 .phy_id_mask = QCA8K_PHY_ID_MASK, 2004 .name = "Qualcomm Atheros 8327-A internal PHY", 2005 /* PHY_GBIT_FEATURES */ 2006 .link_change_notify = qca83xx_link_change_notify, 2007 .probe = at803x_probe, 2008 .flags = PHY_IS_INTERNAL, 2009 .config_init = qca83xx_config_init, 2010 .soft_reset = genphy_soft_reset, 2011 .get_sset_count = at803x_get_sset_count, 2012 .get_strings = at803x_get_strings, 2013 .get_stats = at803x_get_stats, 2014 .suspend = qca83xx_suspend, 2015 .resume = qca83xx_resume, 2016 }, { 2017 /* QCA8327-B from switch QCA8327-BL1A */ 2018 .phy_id = QCA8327_B_PHY_ID, 2019 .phy_id_mask = QCA8K_PHY_ID_MASK, 2020 .name = "Qualcomm Atheros 8327-B internal PHY", 2021 /* PHY_GBIT_FEATURES */ 2022 .link_change_notify = qca83xx_link_change_notify, 2023 .probe = at803x_probe, 2024 .flags = PHY_IS_INTERNAL, 2025 .config_init = qca83xx_config_init, 2026 .soft_reset = genphy_soft_reset, 2027 .get_sset_count = at803x_get_sset_count, 2028 .get_strings = at803x_get_strings, 2029 .get_stats = at803x_get_stats, 2030 .suspend = qca83xx_suspend, 2031 .resume = qca83xx_resume, 2032 }, { 2033 /* Qualcomm QCA8081 */ 2034 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2035 .name = "Qualcomm QCA8081", 2036 .flags = PHY_POLL_CABLE_TEST, 2037 .config_intr = at803x_config_intr, 2038 .handle_interrupt = at803x_handle_interrupt, 2039 .get_tunable = at803x_get_tunable, 2040 .set_tunable = at803x_set_tunable, 2041 .set_wol = at803x_set_wol, 2042 .get_wol = at803x_get_wol, 2043 .get_features = at803x_get_features, 2044 .config_aneg = at803x_config_aneg, 2045 .suspend = genphy_suspend, 2046 .resume = genphy_resume, 2047 .read_status = qca808x_read_status, 2048 .config_init = qca808x_config_init, 2049 .soft_reset = qca808x_soft_reset, 2050 .cable_test_start = qca808x_cable_test_start, 2051 .cable_test_get_status = qca808x_cable_test_get_status, 2052 }, }; 2053 2054 module_phy_driver(at803x_driver); 2055 2056 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 2057 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 2058 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 2059 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 2060 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 2061 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 2062 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2063 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2064 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2065 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2066 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 2067 { } 2068 }; 2069 2070 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2071