xref: /openbmc/linux/drivers/net/phy/at803x.c (revision ccb01374)
1 /*
2  * drivers/net/phy/at803x.c
3  *
4  * Driver for Atheros 803x PHY
5  *
6  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13 
14 #include <linux/phy.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/of_gpio.h>
20 #include <linux/gpio/consumer.h>
21 
22 #define AT803X_INTR_ENABLE			0x12
23 #define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
24 #define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
25 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
26 #define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
27 #define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
28 #define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
29 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
30 #define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
31 #define AT803X_INTR_ENABLE_WOL			BIT(0)
32 
33 #define AT803X_INTR_STATUS			0x13
34 
35 #define AT803X_SMART_SPEED			0x14
36 #define AT803X_LED_CONTROL			0x18
37 
38 #define AT803X_DEVICE_ADDR			0x03
39 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
40 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
41 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
42 #define AT803X_MMD_ACCESS_CONTROL		0x0D
43 #define AT803X_MMD_ACCESS_CONTROL_DATA		0x0E
44 #define AT803X_FUNC_DATA			0x4003
45 #define AT803X_REG_CHIP_CONFIG			0x1f
46 #define AT803X_BT_BX_REG_SEL			0x8000
47 
48 #define AT803X_DEBUG_ADDR			0x1D
49 #define AT803X_DEBUG_DATA			0x1E
50 
51 #define AT803X_MODE_CFG_MASK			0x0F
52 #define AT803X_MODE_CFG_SGMII			0x01
53 
54 #define AT803X_PSSR			0x11	/*PHY-Specific Status Register*/
55 #define AT803X_PSSR_MR_AN_COMPLETE	0x0200
56 
57 #define AT803X_DEBUG_REG_0			0x00
58 #define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
59 
60 #define AT803X_DEBUG_REG_5			0x05
61 #define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
62 
63 #define ATH8030_PHY_ID 0x004dd076
64 #define ATH8031_PHY_ID 0x004dd074
65 #define ATH8035_PHY_ID 0x004dd072
66 #define AT803X_PHY_ID_MASK			0xffffffef
67 
68 MODULE_DESCRIPTION("Atheros 803x PHY driver");
69 MODULE_AUTHOR("Matus Ujhelyi");
70 MODULE_LICENSE("GPL");
71 
72 struct at803x_priv {
73 	bool phy_reset:1;
74 };
75 
76 struct at803x_context {
77 	u16 bmcr;
78 	u16 advertise;
79 	u16 control1000;
80 	u16 int_enable;
81 	u16 smart_speed;
82 	u16 led_control;
83 };
84 
85 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
86 {
87 	int ret;
88 
89 	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
90 	if (ret < 0)
91 		return ret;
92 
93 	return phy_read(phydev, AT803X_DEBUG_DATA);
94 }
95 
96 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
97 				 u16 clear, u16 set)
98 {
99 	u16 val;
100 	int ret;
101 
102 	ret = at803x_debug_reg_read(phydev, reg);
103 	if (ret < 0)
104 		return ret;
105 
106 	val = ret & 0xffff;
107 	val &= ~clear;
108 	val |= set;
109 
110 	return phy_write(phydev, AT803X_DEBUG_DATA, val);
111 }
112 
113 static inline int at803x_enable_rx_delay(struct phy_device *phydev)
114 {
115 	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
116 					AT803X_DEBUG_RX_CLK_DLY_EN);
117 }
118 
119 static inline int at803x_enable_tx_delay(struct phy_device *phydev)
120 {
121 	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
122 					AT803X_DEBUG_TX_CLK_DLY_EN);
123 }
124 
125 /* save relevant PHY registers to private copy */
126 static void at803x_context_save(struct phy_device *phydev,
127 				struct at803x_context *context)
128 {
129 	context->bmcr = phy_read(phydev, MII_BMCR);
130 	context->advertise = phy_read(phydev, MII_ADVERTISE);
131 	context->control1000 = phy_read(phydev, MII_CTRL1000);
132 	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
133 	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
134 	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
135 }
136 
137 /* restore relevant PHY registers from private copy */
138 static void at803x_context_restore(struct phy_device *phydev,
139 				   const struct at803x_context *context)
140 {
141 	phy_write(phydev, MII_BMCR, context->bmcr);
142 	phy_write(phydev, MII_ADVERTISE, context->advertise);
143 	phy_write(phydev, MII_CTRL1000, context->control1000);
144 	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
145 	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
146 	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
147 }
148 
149 static int at803x_set_wol(struct phy_device *phydev,
150 			  struct ethtool_wolinfo *wol)
151 {
152 	struct net_device *ndev = phydev->attached_dev;
153 	const u8 *mac;
154 	int ret;
155 	u32 value;
156 	unsigned int i, offsets[] = {
157 		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
158 		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
159 		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
160 	};
161 
162 	if (!ndev)
163 		return -ENODEV;
164 
165 	if (wol->wolopts & WAKE_MAGIC) {
166 		mac = (const u8 *) ndev->dev_addr;
167 
168 		if (!is_valid_ether_addr(mac))
169 			return -EINVAL;
170 
171 		for (i = 0; i < 3; i++) {
172 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
173 				  AT803X_DEVICE_ADDR);
174 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
175 				  offsets[i]);
176 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
177 				  AT803X_FUNC_DATA);
178 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
179 				  mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
180 		}
181 
182 		value = phy_read(phydev, AT803X_INTR_ENABLE);
183 		value |= AT803X_INTR_ENABLE_WOL;
184 		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
185 		if (ret)
186 			return ret;
187 		value = phy_read(phydev, AT803X_INTR_STATUS);
188 	} else {
189 		value = phy_read(phydev, AT803X_INTR_ENABLE);
190 		value &= (~AT803X_INTR_ENABLE_WOL);
191 		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
192 		if (ret)
193 			return ret;
194 		value = phy_read(phydev, AT803X_INTR_STATUS);
195 	}
196 
197 	return ret;
198 }
199 
200 static void at803x_get_wol(struct phy_device *phydev,
201 			   struct ethtool_wolinfo *wol)
202 {
203 	u32 value;
204 
205 	wol->supported = WAKE_MAGIC;
206 	wol->wolopts = 0;
207 
208 	value = phy_read(phydev, AT803X_INTR_ENABLE);
209 	if (value & AT803X_INTR_ENABLE_WOL)
210 		wol->wolopts |= WAKE_MAGIC;
211 }
212 
213 static int at803x_suspend(struct phy_device *phydev)
214 {
215 	int value;
216 	int wol_enabled;
217 
218 	value = phy_read(phydev, AT803X_INTR_ENABLE);
219 	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
220 
221 	if (wol_enabled)
222 		value = BMCR_ISOLATE;
223 	else
224 		value = BMCR_PDOWN;
225 
226 	phy_modify(phydev, MII_BMCR, 0, value);
227 
228 	return 0;
229 }
230 
231 static int at803x_resume(struct phy_device *phydev)
232 {
233 	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
234 }
235 
236 static int at803x_probe(struct phy_device *phydev)
237 {
238 	struct device *dev = &phydev->mdio.dev;
239 	struct at803x_priv *priv;
240 
241 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
242 	if (!priv)
243 		return -ENOMEM;
244 
245 	phydev->priv = priv;
246 
247 	return 0;
248 }
249 
250 static int at803x_config_init(struct phy_device *phydev)
251 {
252 	int ret;
253 
254 	ret = genphy_config_init(phydev);
255 	if (ret < 0)
256 		return ret;
257 
258 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
259 			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
260 		ret = at803x_enable_rx_delay(phydev);
261 		if (ret < 0)
262 			return ret;
263 	}
264 
265 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
266 			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
267 		ret = at803x_enable_tx_delay(phydev);
268 		if (ret < 0)
269 			return ret;
270 	}
271 
272 	return 0;
273 }
274 
275 static int at803x_ack_interrupt(struct phy_device *phydev)
276 {
277 	int err;
278 
279 	err = phy_read(phydev, AT803X_INTR_STATUS);
280 
281 	return (err < 0) ? err : 0;
282 }
283 
284 static int at803x_config_intr(struct phy_device *phydev)
285 {
286 	int err;
287 	int value;
288 
289 	value = phy_read(phydev, AT803X_INTR_ENABLE);
290 
291 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
292 		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
293 		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
294 		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
295 		value |= AT803X_INTR_ENABLE_LINK_FAIL;
296 		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
297 
298 		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
299 	}
300 	else
301 		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
302 
303 	return err;
304 }
305 
306 static void at803x_link_change_notify(struct phy_device *phydev)
307 {
308 	struct at803x_priv *priv = phydev->priv;
309 
310 	/*
311 	 * Conduct a hardware reset for AT8030 every time a link loss is
312 	 * signalled. This is necessary to circumvent a hardware bug that
313 	 * occurs when the cable is unplugged while TX packets are pending
314 	 * in the FIFO. In such cases, the FIFO enters an error mode it
315 	 * cannot recover from by software.
316 	 */
317 	if (phydev->state == PHY_NOLINK) {
318 		if (phydev->mdio.reset && !priv->phy_reset) {
319 			struct at803x_context context;
320 
321 			at803x_context_save(phydev, &context);
322 
323 			phy_device_reset(phydev, 1);
324 			msleep(1);
325 			phy_device_reset(phydev, 0);
326 			msleep(1);
327 
328 			at803x_context_restore(phydev, &context);
329 
330 			phydev_dbg(phydev, "%s(): phy was reset\n",
331 				   __func__);
332 			priv->phy_reset = true;
333 		}
334 	} else {
335 		priv->phy_reset = false;
336 	}
337 }
338 
339 static int at803x_aneg_done(struct phy_device *phydev)
340 {
341 	int ccr;
342 
343 	int aneg_done = genphy_aneg_done(phydev);
344 	if (aneg_done != BMSR_ANEGCOMPLETE)
345 		return aneg_done;
346 
347 	/*
348 	 * in SGMII mode, if copper side autoneg is successful,
349 	 * also check SGMII side autoneg result
350 	 */
351 	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
352 	if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
353 		return aneg_done;
354 
355 	/* switch to SGMII/fiber page */
356 	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
357 
358 	/* check if the SGMII link is OK. */
359 	if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
360 		phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
361 		aneg_done = 0;
362 	}
363 	/* switch back to copper page */
364 	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
365 
366 	return aneg_done;
367 }
368 
369 static struct phy_driver at803x_driver[] = {
370 {
371 	/* ATHEROS 8035 */
372 	.phy_id			= ATH8035_PHY_ID,
373 	.name			= "Atheros 8035 ethernet",
374 	.phy_id_mask		= AT803X_PHY_ID_MASK,
375 	.probe			= at803x_probe,
376 	.config_init		= at803x_config_init,
377 	.set_wol		= at803x_set_wol,
378 	.get_wol		= at803x_get_wol,
379 	.suspend		= at803x_suspend,
380 	.resume			= at803x_resume,
381 	.features		= PHY_GBIT_FEATURES,
382 	.ack_interrupt		= at803x_ack_interrupt,
383 	.config_intr		= at803x_config_intr,
384 }, {
385 	/* ATHEROS 8030 */
386 	.phy_id			= ATH8030_PHY_ID,
387 	.name			= "Atheros 8030 ethernet",
388 	.phy_id_mask		= AT803X_PHY_ID_MASK,
389 	.probe			= at803x_probe,
390 	.config_init		= at803x_config_init,
391 	.link_change_notify	= at803x_link_change_notify,
392 	.set_wol		= at803x_set_wol,
393 	.get_wol		= at803x_get_wol,
394 	.suspend		= at803x_suspend,
395 	.resume			= at803x_resume,
396 	.features		= PHY_BASIC_FEATURES,
397 	.ack_interrupt		= at803x_ack_interrupt,
398 	.config_intr		= at803x_config_intr,
399 }, {
400 	/* ATHEROS 8031 */
401 	.phy_id			= ATH8031_PHY_ID,
402 	.name			= "Atheros 8031 ethernet",
403 	.phy_id_mask		= AT803X_PHY_ID_MASK,
404 	.probe			= at803x_probe,
405 	.config_init		= at803x_config_init,
406 	.set_wol		= at803x_set_wol,
407 	.get_wol		= at803x_get_wol,
408 	.suspend		= at803x_suspend,
409 	.resume			= at803x_resume,
410 	.features		= PHY_GBIT_FEATURES,
411 	.aneg_done		= at803x_aneg_done,
412 	.ack_interrupt		= &at803x_ack_interrupt,
413 	.config_intr		= &at803x_config_intr,
414 } };
415 
416 module_phy_driver(at803x_driver);
417 
418 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
419 	{ ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
420 	{ ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
421 	{ ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
422 	{ }
423 };
424 
425 MODULE_DEVICE_TABLE(mdio, atheros_tbl);
426