1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Atheros 803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of_gpio.h> 16 #include <linux/gpio/consumer.h> 17 18 #define AT803X_INTR_ENABLE 0x12 19 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 20 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 21 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 22 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 23 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 24 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 25 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 26 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 27 #define AT803X_INTR_ENABLE_WOL BIT(0) 28 29 #define AT803X_INTR_STATUS 0x13 30 31 #define AT803X_SMART_SPEED 0x14 32 #define AT803X_LED_CONTROL 0x18 33 34 #define AT803X_DEVICE_ADDR 0x03 35 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 36 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 37 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 38 #define AT803X_REG_CHIP_CONFIG 0x1f 39 #define AT803X_BT_BX_REG_SEL 0x8000 40 41 #define AT803X_DEBUG_ADDR 0x1D 42 #define AT803X_DEBUG_DATA 0x1E 43 44 #define AT803X_MODE_CFG_MASK 0x0F 45 #define AT803X_MODE_CFG_SGMII 0x01 46 47 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 48 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 49 50 #define AT803X_DEBUG_REG_0 0x00 51 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 52 53 #define AT803X_DEBUG_REG_5 0x05 54 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 55 56 #define ATH8030_PHY_ID 0x004dd076 57 #define ATH8031_PHY_ID 0x004dd074 58 #define ATH8035_PHY_ID 0x004dd072 59 #define AT803X_PHY_ID_MASK 0xffffffef 60 61 MODULE_DESCRIPTION("Atheros 803x PHY driver"); 62 MODULE_AUTHOR("Matus Ujhelyi"); 63 MODULE_LICENSE("GPL"); 64 65 struct at803x_priv { 66 bool phy_reset:1; 67 }; 68 69 struct at803x_context { 70 u16 bmcr; 71 u16 advertise; 72 u16 control1000; 73 u16 int_enable; 74 u16 smart_speed; 75 u16 led_control; 76 }; 77 78 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 79 { 80 int ret; 81 82 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 83 if (ret < 0) 84 return ret; 85 86 return phy_read(phydev, AT803X_DEBUG_DATA); 87 } 88 89 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 90 u16 clear, u16 set) 91 { 92 u16 val; 93 int ret; 94 95 ret = at803x_debug_reg_read(phydev, reg); 96 if (ret < 0) 97 return ret; 98 99 val = ret & 0xffff; 100 val &= ~clear; 101 val |= set; 102 103 return phy_write(phydev, AT803X_DEBUG_DATA, val); 104 } 105 106 static int at803x_enable_rx_delay(struct phy_device *phydev) 107 { 108 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 109 AT803X_DEBUG_RX_CLK_DLY_EN); 110 } 111 112 static int at803x_enable_tx_delay(struct phy_device *phydev) 113 { 114 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 115 AT803X_DEBUG_TX_CLK_DLY_EN); 116 } 117 118 static int at803x_disable_rx_delay(struct phy_device *phydev) 119 { 120 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 121 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 122 } 123 124 static int at803x_disable_tx_delay(struct phy_device *phydev) 125 { 126 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 127 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 128 } 129 130 /* save relevant PHY registers to private copy */ 131 static void at803x_context_save(struct phy_device *phydev, 132 struct at803x_context *context) 133 { 134 context->bmcr = phy_read(phydev, MII_BMCR); 135 context->advertise = phy_read(phydev, MII_ADVERTISE); 136 context->control1000 = phy_read(phydev, MII_CTRL1000); 137 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 138 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 139 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 140 } 141 142 /* restore relevant PHY registers from private copy */ 143 static void at803x_context_restore(struct phy_device *phydev, 144 const struct at803x_context *context) 145 { 146 phy_write(phydev, MII_BMCR, context->bmcr); 147 phy_write(phydev, MII_ADVERTISE, context->advertise); 148 phy_write(phydev, MII_CTRL1000, context->control1000); 149 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 150 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 151 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 152 } 153 154 static int at803x_set_wol(struct phy_device *phydev, 155 struct ethtool_wolinfo *wol) 156 { 157 struct net_device *ndev = phydev->attached_dev; 158 const u8 *mac; 159 int ret; 160 u32 value; 161 unsigned int i, offsets[] = { 162 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 163 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 164 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 165 }; 166 167 if (!ndev) 168 return -ENODEV; 169 170 if (wol->wolopts & WAKE_MAGIC) { 171 mac = (const u8 *) ndev->dev_addr; 172 173 if (!is_valid_ether_addr(mac)) 174 return -EINVAL; 175 176 for (i = 0; i < 3; i++) 177 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 178 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 179 180 value = phy_read(phydev, AT803X_INTR_ENABLE); 181 value |= AT803X_INTR_ENABLE_WOL; 182 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 183 if (ret) 184 return ret; 185 value = phy_read(phydev, AT803X_INTR_STATUS); 186 } else { 187 value = phy_read(phydev, AT803X_INTR_ENABLE); 188 value &= (~AT803X_INTR_ENABLE_WOL); 189 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 190 if (ret) 191 return ret; 192 value = phy_read(phydev, AT803X_INTR_STATUS); 193 } 194 195 return ret; 196 } 197 198 static void at803x_get_wol(struct phy_device *phydev, 199 struct ethtool_wolinfo *wol) 200 { 201 u32 value; 202 203 wol->supported = WAKE_MAGIC; 204 wol->wolopts = 0; 205 206 value = phy_read(phydev, AT803X_INTR_ENABLE); 207 if (value & AT803X_INTR_ENABLE_WOL) 208 wol->wolopts |= WAKE_MAGIC; 209 } 210 211 static int at803x_suspend(struct phy_device *phydev) 212 { 213 int value; 214 int wol_enabled; 215 216 value = phy_read(phydev, AT803X_INTR_ENABLE); 217 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 218 219 if (wol_enabled) 220 value = BMCR_ISOLATE; 221 else 222 value = BMCR_PDOWN; 223 224 phy_modify(phydev, MII_BMCR, 0, value); 225 226 return 0; 227 } 228 229 static int at803x_resume(struct phy_device *phydev) 230 { 231 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 232 } 233 234 static int at803x_probe(struct phy_device *phydev) 235 { 236 struct device *dev = &phydev->mdio.dev; 237 struct at803x_priv *priv; 238 239 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 240 if (!priv) 241 return -ENOMEM; 242 243 phydev->priv = priv; 244 245 return 0; 246 } 247 248 static int at803x_config_init(struct phy_device *phydev) 249 { 250 int ret; 251 252 /* The RX and TX delay default is: 253 * after HW reset: RX delay enabled and TX delay disabled 254 * after SW reset: RX delay enabled, while TX delay retains the 255 * value before reset. 256 * 257 * So let's first disable the RX and TX delays in PHY and enable 258 * them based on the mode selected (this also takes care of RGMII 259 * mode where we expect delays to be disabled) 260 */ 261 262 ret = at803x_disable_rx_delay(phydev); 263 if (ret < 0) 264 return ret; 265 ret = at803x_disable_tx_delay(phydev); 266 if (ret < 0) 267 return ret; 268 269 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 270 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 271 /* If RGMII_ID or RGMII_RXID are specified enable RX delay, 272 * otherwise keep it disabled 273 */ 274 ret = at803x_enable_rx_delay(phydev); 275 if (ret < 0) 276 return ret; 277 } 278 279 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 280 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 281 /* If RGMII_ID or RGMII_TXID are specified enable TX delay, 282 * otherwise keep it disabled 283 */ 284 ret = at803x_enable_tx_delay(phydev); 285 } 286 287 return ret; 288 } 289 290 static int at803x_ack_interrupt(struct phy_device *phydev) 291 { 292 int err; 293 294 err = phy_read(phydev, AT803X_INTR_STATUS); 295 296 return (err < 0) ? err : 0; 297 } 298 299 static int at803x_config_intr(struct phy_device *phydev) 300 { 301 int err; 302 int value; 303 304 value = phy_read(phydev, AT803X_INTR_ENABLE); 305 306 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 307 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 308 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 309 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 310 value |= AT803X_INTR_ENABLE_LINK_FAIL; 311 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 312 313 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 314 } 315 else 316 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 317 318 return err; 319 } 320 321 static void at803x_link_change_notify(struct phy_device *phydev) 322 { 323 /* 324 * Conduct a hardware reset for AT8030 every time a link loss is 325 * signalled. This is necessary to circumvent a hardware bug that 326 * occurs when the cable is unplugged while TX packets are pending 327 * in the FIFO. In such cases, the FIFO enters an error mode it 328 * cannot recover from by software. 329 */ 330 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 331 struct at803x_context context; 332 333 at803x_context_save(phydev, &context); 334 335 phy_device_reset(phydev, 1); 336 msleep(1); 337 phy_device_reset(phydev, 0); 338 msleep(1); 339 340 at803x_context_restore(phydev, &context); 341 342 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 343 } 344 } 345 346 static int at803x_aneg_done(struct phy_device *phydev) 347 { 348 int ccr; 349 350 int aneg_done = genphy_aneg_done(phydev); 351 if (aneg_done != BMSR_ANEGCOMPLETE) 352 return aneg_done; 353 354 /* 355 * in SGMII mode, if copper side autoneg is successful, 356 * also check SGMII side autoneg result 357 */ 358 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 359 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII) 360 return aneg_done; 361 362 /* switch to SGMII/fiber page */ 363 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL); 364 365 /* check if the SGMII link is OK. */ 366 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { 367 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); 368 aneg_done = 0; 369 } 370 /* switch back to copper page */ 371 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); 372 373 return aneg_done; 374 } 375 376 static struct phy_driver at803x_driver[] = { 377 { 378 /* ATHEROS 8035 */ 379 .phy_id = ATH8035_PHY_ID, 380 .name = "Atheros 8035 ethernet", 381 .phy_id_mask = AT803X_PHY_ID_MASK, 382 .probe = at803x_probe, 383 .config_init = at803x_config_init, 384 .set_wol = at803x_set_wol, 385 .get_wol = at803x_get_wol, 386 .suspend = at803x_suspend, 387 .resume = at803x_resume, 388 /* PHY_GBIT_FEATURES */ 389 .ack_interrupt = at803x_ack_interrupt, 390 .config_intr = at803x_config_intr, 391 }, { 392 /* ATHEROS 8030 */ 393 .phy_id = ATH8030_PHY_ID, 394 .name = "Atheros 8030 ethernet", 395 .phy_id_mask = AT803X_PHY_ID_MASK, 396 .probe = at803x_probe, 397 .config_init = at803x_config_init, 398 .link_change_notify = at803x_link_change_notify, 399 .set_wol = at803x_set_wol, 400 .get_wol = at803x_get_wol, 401 .suspend = at803x_suspend, 402 .resume = at803x_resume, 403 /* PHY_BASIC_FEATURES */ 404 .ack_interrupt = at803x_ack_interrupt, 405 .config_intr = at803x_config_intr, 406 }, { 407 /* ATHEROS 8031 */ 408 .phy_id = ATH8031_PHY_ID, 409 .name = "Atheros 8031 ethernet", 410 .phy_id_mask = AT803X_PHY_ID_MASK, 411 .probe = at803x_probe, 412 .config_init = at803x_config_init, 413 .set_wol = at803x_set_wol, 414 .get_wol = at803x_get_wol, 415 .suspend = at803x_suspend, 416 .resume = at803x_resume, 417 /* PHY_GBIT_FEATURES */ 418 .aneg_done = at803x_aneg_done, 419 .ack_interrupt = &at803x_ack_interrupt, 420 .config_intr = &at803x_config_intr, 421 } }; 422 423 module_phy_driver(at803x_driver); 424 425 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 426 { ATH8030_PHY_ID, AT803X_PHY_ID_MASK }, 427 { ATH8031_PHY_ID, AT803X_PHY_ID_MASK }, 428 { ATH8035_PHY_ID, AT803X_PHY_ID_MASK }, 429 { } 430 }; 431 432 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 433