xref: /openbmc/linux/drivers/net/phy/at803x.c (revision c16c6655)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * drivers/net/phy/at803x.c
4  *
5  * Driver for Atheros 803x PHY
6  *
7  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8  */
9 
10 #include <linux/phy.h>
11 #include <linux/module.h>
12 #include <linux/string.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/of_gpio.h>
16 #include <linux/gpio/consumer.h>
17 
18 #define AT803X_INTR_ENABLE			0x12
19 #define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
20 #define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
21 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
22 #define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
23 #define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
24 #define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
25 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
26 #define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
27 #define AT803X_INTR_ENABLE_WOL			BIT(0)
28 
29 #define AT803X_INTR_STATUS			0x13
30 
31 #define AT803X_SMART_SPEED			0x14
32 #define AT803X_LED_CONTROL			0x18
33 
34 #define AT803X_DEVICE_ADDR			0x03
35 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
36 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
37 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
38 #define AT803X_REG_CHIP_CONFIG			0x1f
39 #define AT803X_BT_BX_REG_SEL			0x8000
40 
41 #define AT803X_DEBUG_ADDR			0x1D
42 #define AT803X_DEBUG_DATA			0x1E
43 
44 #define AT803X_MODE_CFG_MASK			0x0F
45 #define AT803X_MODE_CFG_SGMII			0x01
46 
47 #define AT803X_PSSR			0x11	/*PHY-Specific Status Register*/
48 #define AT803X_PSSR_MR_AN_COMPLETE	0x0200
49 
50 #define AT803X_DEBUG_REG_0			0x00
51 #define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
52 
53 #define AT803X_DEBUG_REG_5			0x05
54 #define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
55 
56 #define ATH8030_PHY_ID 0x004dd076
57 #define ATH8031_PHY_ID 0x004dd074
58 #define ATH8035_PHY_ID 0x004dd072
59 #define AT803X_PHY_ID_MASK			0xffffffef
60 
61 MODULE_DESCRIPTION("Atheros 803x PHY driver");
62 MODULE_AUTHOR("Matus Ujhelyi");
63 MODULE_LICENSE("GPL");
64 
65 struct at803x_priv {
66 	bool phy_reset:1;
67 };
68 
69 struct at803x_context {
70 	u16 bmcr;
71 	u16 advertise;
72 	u16 control1000;
73 	u16 int_enable;
74 	u16 smart_speed;
75 	u16 led_control;
76 };
77 
78 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
79 {
80 	int ret;
81 
82 	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
83 	if (ret < 0)
84 		return ret;
85 
86 	return phy_read(phydev, AT803X_DEBUG_DATA);
87 }
88 
89 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
90 				 u16 clear, u16 set)
91 {
92 	u16 val;
93 	int ret;
94 
95 	ret = at803x_debug_reg_read(phydev, reg);
96 	if (ret < 0)
97 		return ret;
98 
99 	val = ret & 0xffff;
100 	val &= ~clear;
101 	val |= set;
102 
103 	return phy_write(phydev, AT803X_DEBUG_DATA, val);
104 }
105 
106 static int at803x_enable_rx_delay(struct phy_device *phydev)
107 {
108 	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
109 				     AT803X_DEBUG_RX_CLK_DLY_EN);
110 }
111 
112 static int at803x_enable_tx_delay(struct phy_device *phydev)
113 {
114 	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
115 				     AT803X_DEBUG_TX_CLK_DLY_EN);
116 }
117 
118 static int at803x_disable_rx_delay(struct phy_device *phydev)
119 {
120 	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
121 				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
122 }
123 
124 static int at803x_disable_tx_delay(struct phy_device *phydev)
125 {
126 	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
127 				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
128 }
129 
130 /* save relevant PHY registers to private copy */
131 static void at803x_context_save(struct phy_device *phydev,
132 				struct at803x_context *context)
133 {
134 	context->bmcr = phy_read(phydev, MII_BMCR);
135 	context->advertise = phy_read(phydev, MII_ADVERTISE);
136 	context->control1000 = phy_read(phydev, MII_CTRL1000);
137 	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
138 	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
139 	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
140 }
141 
142 /* restore relevant PHY registers from private copy */
143 static void at803x_context_restore(struct phy_device *phydev,
144 				   const struct at803x_context *context)
145 {
146 	phy_write(phydev, MII_BMCR, context->bmcr);
147 	phy_write(phydev, MII_ADVERTISE, context->advertise);
148 	phy_write(phydev, MII_CTRL1000, context->control1000);
149 	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
150 	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
151 	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
152 }
153 
154 static int at803x_set_wol(struct phy_device *phydev,
155 			  struct ethtool_wolinfo *wol)
156 {
157 	struct net_device *ndev = phydev->attached_dev;
158 	const u8 *mac;
159 	int ret;
160 	u32 value;
161 	unsigned int i, offsets[] = {
162 		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
163 		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
164 		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
165 	};
166 
167 	if (!ndev)
168 		return -ENODEV;
169 
170 	if (wol->wolopts & WAKE_MAGIC) {
171 		mac = (const u8 *) ndev->dev_addr;
172 
173 		if (!is_valid_ether_addr(mac))
174 			return -EINVAL;
175 
176 		for (i = 0; i < 3; i++)
177 			phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
178 				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
179 
180 		value = phy_read(phydev, AT803X_INTR_ENABLE);
181 		value |= AT803X_INTR_ENABLE_WOL;
182 		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
183 		if (ret)
184 			return ret;
185 		value = phy_read(phydev, AT803X_INTR_STATUS);
186 	} else {
187 		value = phy_read(phydev, AT803X_INTR_ENABLE);
188 		value &= (~AT803X_INTR_ENABLE_WOL);
189 		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
190 		if (ret)
191 			return ret;
192 		value = phy_read(phydev, AT803X_INTR_STATUS);
193 	}
194 
195 	return ret;
196 }
197 
198 static void at803x_get_wol(struct phy_device *phydev,
199 			   struct ethtool_wolinfo *wol)
200 {
201 	u32 value;
202 
203 	wol->supported = WAKE_MAGIC;
204 	wol->wolopts = 0;
205 
206 	value = phy_read(phydev, AT803X_INTR_ENABLE);
207 	if (value & AT803X_INTR_ENABLE_WOL)
208 		wol->wolopts |= WAKE_MAGIC;
209 }
210 
211 static int at803x_suspend(struct phy_device *phydev)
212 {
213 	int value;
214 	int wol_enabled;
215 
216 	value = phy_read(phydev, AT803X_INTR_ENABLE);
217 	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
218 
219 	if (wol_enabled)
220 		value = BMCR_ISOLATE;
221 	else
222 		value = BMCR_PDOWN;
223 
224 	phy_modify(phydev, MII_BMCR, 0, value);
225 
226 	return 0;
227 }
228 
229 static int at803x_resume(struct phy_device *phydev)
230 {
231 	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
232 }
233 
234 static int at803x_probe(struct phy_device *phydev)
235 {
236 	struct device *dev = &phydev->mdio.dev;
237 	struct at803x_priv *priv;
238 
239 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
240 	if (!priv)
241 		return -ENOMEM;
242 
243 	phydev->priv = priv;
244 
245 	return 0;
246 }
247 
248 static int at803x_config_init(struct phy_device *phydev)
249 {
250 	int ret;
251 
252 	ret = genphy_config_init(phydev);
253 	if (ret < 0)
254 		return ret;
255 
256 	/* The RX and TX delay default is:
257 	 *   after HW reset: RX delay enabled and TX delay disabled
258 	 *   after SW reset: RX delay enabled, while TX delay retains the
259 	 *   value before reset.
260 	 */
261 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
262 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
263 		ret = at803x_enable_rx_delay(phydev);
264 	else
265 		ret = at803x_disable_rx_delay(phydev);
266 	if (ret < 0)
267 		return ret;
268 
269 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
270 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
271 		ret = at803x_enable_tx_delay(phydev);
272 	else
273 		ret = at803x_disable_tx_delay(phydev);
274 
275 	return ret;
276 }
277 
278 static int at803x_ack_interrupt(struct phy_device *phydev)
279 {
280 	int err;
281 
282 	err = phy_read(phydev, AT803X_INTR_STATUS);
283 
284 	return (err < 0) ? err : 0;
285 }
286 
287 static int at803x_config_intr(struct phy_device *phydev)
288 {
289 	int err;
290 	int value;
291 
292 	value = phy_read(phydev, AT803X_INTR_ENABLE);
293 
294 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
295 		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
296 		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
297 		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
298 		value |= AT803X_INTR_ENABLE_LINK_FAIL;
299 		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
300 
301 		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
302 	}
303 	else
304 		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
305 
306 	return err;
307 }
308 
309 static void at803x_link_change_notify(struct phy_device *phydev)
310 {
311 	/*
312 	 * Conduct a hardware reset for AT8030 every time a link loss is
313 	 * signalled. This is necessary to circumvent a hardware bug that
314 	 * occurs when the cable is unplugged while TX packets are pending
315 	 * in the FIFO. In such cases, the FIFO enters an error mode it
316 	 * cannot recover from by software.
317 	 */
318 	if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
319 		struct at803x_context context;
320 
321 		at803x_context_save(phydev, &context);
322 
323 		phy_device_reset(phydev, 1);
324 		msleep(1);
325 		phy_device_reset(phydev, 0);
326 		msleep(1);
327 
328 		at803x_context_restore(phydev, &context);
329 
330 		phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
331 	}
332 }
333 
334 static int at803x_aneg_done(struct phy_device *phydev)
335 {
336 	int ccr;
337 
338 	int aneg_done = genphy_aneg_done(phydev);
339 	if (aneg_done != BMSR_ANEGCOMPLETE)
340 		return aneg_done;
341 
342 	/*
343 	 * in SGMII mode, if copper side autoneg is successful,
344 	 * also check SGMII side autoneg result
345 	 */
346 	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
347 	if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
348 		return aneg_done;
349 
350 	/* switch to SGMII/fiber page */
351 	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
352 
353 	/* check if the SGMII link is OK. */
354 	if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
355 		phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
356 		aneg_done = 0;
357 	}
358 	/* switch back to copper page */
359 	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
360 
361 	return aneg_done;
362 }
363 
364 static struct phy_driver at803x_driver[] = {
365 {
366 	/* ATHEROS 8035 */
367 	.phy_id			= ATH8035_PHY_ID,
368 	.name			= "Atheros 8035 ethernet",
369 	.phy_id_mask		= AT803X_PHY_ID_MASK,
370 	.probe			= at803x_probe,
371 	.config_init		= at803x_config_init,
372 	.set_wol		= at803x_set_wol,
373 	.get_wol		= at803x_get_wol,
374 	.suspend		= at803x_suspend,
375 	.resume			= at803x_resume,
376 	/* PHY_GBIT_FEATURES */
377 	.ack_interrupt		= at803x_ack_interrupt,
378 	.config_intr		= at803x_config_intr,
379 }, {
380 	/* ATHEROS 8030 */
381 	.phy_id			= ATH8030_PHY_ID,
382 	.name			= "Atheros 8030 ethernet",
383 	.phy_id_mask		= AT803X_PHY_ID_MASK,
384 	.probe			= at803x_probe,
385 	.config_init		= at803x_config_init,
386 	.link_change_notify	= at803x_link_change_notify,
387 	.set_wol		= at803x_set_wol,
388 	.get_wol		= at803x_get_wol,
389 	.suspend		= at803x_suspend,
390 	.resume			= at803x_resume,
391 	/* PHY_BASIC_FEATURES */
392 	.ack_interrupt		= at803x_ack_interrupt,
393 	.config_intr		= at803x_config_intr,
394 }, {
395 	/* ATHEROS 8031 */
396 	.phy_id			= ATH8031_PHY_ID,
397 	.name			= "Atheros 8031 ethernet",
398 	.phy_id_mask		= AT803X_PHY_ID_MASK,
399 	.probe			= at803x_probe,
400 	.config_init		= at803x_config_init,
401 	.set_wol		= at803x_set_wol,
402 	.get_wol		= at803x_get_wol,
403 	.suspend		= at803x_suspend,
404 	.resume			= at803x_resume,
405 	/* PHY_GBIT_FEATURES */
406 	.aneg_done		= at803x_aneg_done,
407 	.ack_interrupt		= &at803x_ack_interrupt,
408 	.config_intr		= &at803x_config_intr,
409 } };
410 
411 module_phy_driver(at803x_driver);
412 
413 static struct mdio_device_id __maybe_unused atheros_tbl[] = {
414 	{ ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
415 	{ ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
416 	{ ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
417 	{ }
418 };
419 
420 MODULE_DEVICE_TABLE(mdio, atheros_tbl);
421