1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <dt-bindings/net/qca-ar803x.h> 23 24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 25 #define AT803X_SFC_ASSERT_CRS BIT(11) 26 #define AT803X_SFC_FORCE_LINK BIT(10) 27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 29 #define AT803X_SFC_MANUAL_MDIX 0x1 30 #define AT803X_SFC_MANUAL_MDI 0x0 31 #define AT803X_SFC_SQE_TEST BIT(2) 32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 33 #define AT803X_SFC_DISABLE_JABBER BIT(0) 34 35 #define AT803X_SPECIFIC_STATUS 0x11 36 #define AT803X_SS_SPEED_MASK (3 << 14) 37 #define AT803X_SS_SPEED_1000 (2 << 14) 38 #define AT803X_SS_SPEED_100 (1 << 14) 39 #define AT803X_SS_SPEED_10 (0 << 14) 40 #define AT803X_SS_DUPLEX BIT(13) 41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 42 #define AT803X_SS_MDIX BIT(6) 43 44 #define AT803X_INTR_ENABLE 0x12 45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 53 #define AT803X_INTR_ENABLE_WOL BIT(0) 54 55 #define AT803X_INTR_STATUS 0x13 56 57 #define AT803X_SMART_SPEED 0x14 58 #define AT803X_SMART_SPEED_ENABLE BIT(5) 59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 61 #define AT803X_CDT 0x16 62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 63 #define AT803X_CDT_ENABLE_TEST BIT(0) 64 #define AT803X_CDT_STATUS 0x1c 65 #define AT803X_CDT_STATUS_STAT_NORMAL 0 66 #define AT803X_CDT_STATUS_STAT_SHORT 1 67 #define AT803X_CDT_STATUS_STAT_OPEN 2 68 #define AT803X_CDT_STATUS_STAT_FAIL 3 69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 71 #define AT803X_LED_CONTROL 0x18 72 73 #define AT803X_DEVICE_ADDR 0x03 74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 77 #define AT803X_REG_CHIP_CONFIG 0x1f 78 #define AT803X_BT_BX_REG_SEL 0x8000 79 80 #define AT803X_DEBUG_ADDR 0x1D 81 #define AT803X_DEBUG_DATA 0x1E 82 83 #define AT803X_MODE_CFG_MASK 0x0F 84 #define AT803X_MODE_CFG_SGMII 0x01 85 86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 88 89 #define AT803X_DEBUG_REG_0 0x00 90 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 91 92 #define AT803X_DEBUG_REG_5 0x05 93 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 94 95 #define AT803X_DEBUG_REG_1F 0x1F 96 #define AT803X_DEBUG_PLL_ON BIT(2) 97 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 98 99 /* AT803x supports either the XTAL input pad, an internal PLL or the 100 * DSP as clock reference for the clock output pad. The XTAL reference 101 * is only used for 25 MHz output, all other frequencies need the PLL. 102 * The DSP as a clock reference is used in synchronous ethernet 103 * applications. 104 * 105 * By default the PLL is only enabled if there is a link. Otherwise 106 * the PHY will go into low power state and disabled the PLL. You can 107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 108 * enabled. 109 */ 110 #define AT803X_MMD7_CLK25M 0x8016 111 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 112 #define AT803X_CLK_OUT_25MHZ_XTAL 0 113 #define AT803X_CLK_OUT_25MHZ_DSP 1 114 #define AT803X_CLK_OUT_50MHZ_PLL 2 115 #define AT803X_CLK_OUT_50MHZ_DSP 3 116 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 117 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 118 #define AT803X_CLK_OUT_125MHZ_PLL 6 119 #define AT803X_CLK_OUT_125MHZ_DSP 7 120 121 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 122 * but doesn't support choosing between XTAL/PLL and DSP. 123 */ 124 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 125 126 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 127 #define AT803X_CLK_OUT_STRENGTH_FULL 0 128 #define AT803X_CLK_OUT_STRENGTH_HALF 1 129 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 130 131 #define AT803X_DEFAULT_DOWNSHIFT 5 132 #define AT803X_MIN_DOWNSHIFT 2 133 #define AT803X_MAX_DOWNSHIFT 9 134 135 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 136 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 137 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 138 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 139 140 #define ATH9331_PHY_ID 0x004dd041 141 #define ATH8030_PHY_ID 0x004dd076 142 #define ATH8031_PHY_ID 0x004dd074 143 #define ATH8032_PHY_ID 0x004dd023 144 #define ATH8035_PHY_ID 0x004dd072 145 #define AT8030_PHY_ID_MASK 0xffffffef 146 147 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 148 MODULE_AUTHOR("Matus Ujhelyi"); 149 MODULE_LICENSE("GPL"); 150 151 struct at803x_priv { 152 int flags; 153 #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ 154 #define AT803X_DISABLE_SMARTEEE BIT(1) 155 u16 clk_25m_reg; 156 u16 clk_25m_mask; 157 u8 smarteee_lpi_tw_1g; 158 u8 smarteee_lpi_tw_100m; 159 struct regulator_dev *vddio_rdev; 160 struct regulator_dev *vddh_rdev; 161 struct regulator *vddio; 162 }; 163 164 struct at803x_context { 165 u16 bmcr; 166 u16 advertise; 167 u16 control1000; 168 u16 int_enable; 169 u16 smart_speed; 170 u16 led_control; 171 }; 172 173 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 174 { 175 int ret; 176 177 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 178 if (ret < 0) 179 return ret; 180 181 return phy_read(phydev, AT803X_DEBUG_DATA); 182 } 183 184 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 185 u16 clear, u16 set) 186 { 187 u16 val; 188 int ret; 189 190 ret = at803x_debug_reg_read(phydev, reg); 191 if (ret < 0) 192 return ret; 193 194 val = ret & 0xffff; 195 val &= ~clear; 196 val |= set; 197 198 return phy_write(phydev, AT803X_DEBUG_DATA, val); 199 } 200 201 static int at803x_enable_rx_delay(struct phy_device *phydev) 202 { 203 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 204 AT803X_DEBUG_RX_CLK_DLY_EN); 205 } 206 207 static int at803x_enable_tx_delay(struct phy_device *phydev) 208 { 209 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 210 AT803X_DEBUG_TX_CLK_DLY_EN); 211 } 212 213 static int at803x_disable_rx_delay(struct phy_device *phydev) 214 { 215 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 216 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 217 } 218 219 static int at803x_disable_tx_delay(struct phy_device *phydev) 220 { 221 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 222 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 223 } 224 225 /* save relevant PHY registers to private copy */ 226 static void at803x_context_save(struct phy_device *phydev, 227 struct at803x_context *context) 228 { 229 context->bmcr = phy_read(phydev, MII_BMCR); 230 context->advertise = phy_read(phydev, MII_ADVERTISE); 231 context->control1000 = phy_read(phydev, MII_CTRL1000); 232 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 233 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 234 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 235 } 236 237 /* restore relevant PHY registers from private copy */ 238 static void at803x_context_restore(struct phy_device *phydev, 239 const struct at803x_context *context) 240 { 241 phy_write(phydev, MII_BMCR, context->bmcr); 242 phy_write(phydev, MII_ADVERTISE, context->advertise); 243 phy_write(phydev, MII_CTRL1000, context->control1000); 244 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 245 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 246 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 247 } 248 249 static int at803x_set_wol(struct phy_device *phydev, 250 struct ethtool_wolinfo *wol) 251 { 252 struct net_device *ndev = phydev->attached_dev; 253 const u8 *mac; 254 int ret; 255 u32 value; 256 unsigned int i, offsets[] = { 257 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 258 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 259 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 260 }; 261 262 if (!ndev) 263 return -ENODEV; 264 265 if (wol->wolopts & WAKE_MAGIC) { 266 mac = (const u8 *) ndev->dev_addr; 267 268 if (!is_valid_ether_addr(mac)) 269 return -EINVAL; 270 271 for (i = 0; i < 3; i++) 272 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 273 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 274 275 value = phy_read(phydev, AT803X_INTR_ENABLE); 276 value |= AT803X_INTR_ENABLE_WOL; 277 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 278 if (ret) 279 return ret; 280 value = phy_read(phydev, AT803X_INTR_STATUS); 281 } else { 282 value = phy_read(phydev, AT803X_INTR_ENABLE); 283 value &= (~AT803X_INTR_ENABLE_WOL); 284 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 285 if (ret) 286 return ret; 287 value = phy_read(phydev, AT803X_INTR_STATUS); 288 } 289 290 return ret; 291 } 292 293 static void at803x_get_wol(struct phy_device *phydev, 294 struct ethtool_wolinfo *wol) 295 { 296 u32 value; 297 298 wol->supported = WAKE_MAGIC; 299 wol->wolopts = 0; 300 301 value = phy_read(phydev, AT803X_INTR_ENABLE); 302 if (value & AT803X_INTR_ENABLE_WOL) 303 wol->wolopts |= WAKE_MAGIC; 304 } 305 306 static int at803x_suspend(struct phy_device *phydev) 307 { 308 int value; 309 int wol_enabled; 310 311 value = phy_read(phydev, AT803X_INTR_ENABLE); 312 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 313 314 if (wol_enabled) 315 value = BMCR_ISOLATE; 316 else 317 value = BMCR_PDOWN; 318 319 phy_modify(phydev, MII_BMCR, 0, value); 320 321 return 0; 322 } 323 324 static int at803x_resume(struct phy_device *phydev) 325 { 326 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 327 } 328 329 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 330 unsigned int selector) 331 { 332 struct phy_device *phydev = rdev_get_drvdata(rdev); 333 334 if (selector) 335 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 336 0, AT803X_DEBUG_RGMII_1V8); 337 else 338 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 339 AT803X_DEBUG_RGMII_1V8, 0); 340 } 341 342 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 343 { 344 struct phy_device *phydev = rdev_get_drvdata(rdev); 345 int val; 346 347 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 348 if (val < 0) 349 return val; 350 351 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 352 } 353 354 static const struct regulator_ops vddio_regulator_ops = { 355 .list_voltage = regulator_list_voltage_table, 356 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 357 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 358 }; 359 360 static const unsigned int vddio_voltage_table[] = { 361 1500000, 362 1800000, 363 }; 364 365 static const struct regulator_desc vddio_desc = { 366 .name = "vddio", 367 .of_match = of_match_ptr("vddio-regulator"), 368 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 369 .volt_table = vddio_voltage_table, 370 .ops = &vddio_regulator_ops, 371 .type = REGULATOR_VOLTAGE, 372 .owner = THIS_MODULE, 373 }; 374 375 static const struct regulator_ops vddh_regulator_ops = { 376 }; 377 378 static const struct regulator_desc vddh_desc = { 379 .name = "vddh", 380 .of_match = of_match_ptr("vddh-regulator"), 381 .n_voltages = 1, 382 .fixed_uV = 2500000, 383 .ops = &vddh_regulator_ops, 384 .type = REGULATOR_VOLTAGE, 385 .owner = THIS_MODULE, 386 }; 387 388 static int at8031_register_regulators(struct phy_device *phydev) 389 { 390 struct at803x_priv *priv = phydev->priv; 391 struct device *dev = &phydev->mdio.dev; 392 struct regulator_config config = { }; 393 394 config.dev = dev; 395 config.driver_data = phydev; 396 397 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 398 if (IS_ERR(priv->vddio_rdev)) { 399 phydev_err(phydev, "failed to register VDDIO regulator\n"); 400 return PTR_ERR(priv->vddio_rdev); 401 } 402 403 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 404 if (IS_ERR(priv->vddh_rdev)) { 405 phydev_err(phydev, "failed to register VDDH regulator\n"); 406 return PTR_ERR(priv->vddh_rdev); 407 } 408 409 return 0; 410 } 411 412 static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) 413 { 414 return (phydev->phy_id & phydev->drv->phy_id_mask) 415 == (phy_id & phydev->drv->phy_id_mask); 416 } 417 418 static int at803x_parse_dt(struct phy_device *phydev) 419 { 420 struct device_node *node = phydev->mdio.dev.of_node; 421 struct at803x_priv *priv = phydev->priv; 422 u32 freq, strength, tw; 423 unsigned int sel; 424 int ret; 425 426 if (!IS_ENABLED(CONFIG_OF_MDIO)) 427 return 0; 428 429 if (of_property_read_bool(node, "qca,disable-smarteee")) 430 priv->flags |= AT803X_DISABLE_SMARTEEE; 431 432 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 433 if (!tw || tw > 255) { 434 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 435 return -EINVAL; 436 } 437 priv->smarteee_lpi_tw_1g = tw; 438 } 439 440 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 441 if (!tw || tw > 255) { 442 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 443 return -EINVAL; 444 } 445 priv->smarteee_lpi_tw_100m = tw; 446 } 447 448 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 449 if (!ret) { 450 switch (freq) { 451 case 25000000: 452 sel = AT803X_CLK_OUT_25MHZ_XTAL; 453 break; 454 case 50000000: 455 sel = AT803X_CLK_OUT_50MHZ_PLL; 456 break; 457 case 62500000: 458 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 459 break; 460 case 125000000: 461 sel = AT803X_CLK_OUT_125MHZ_PLL; 462 break; 463 default: 464 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 465 return -EINVAL; 466 } 467 468 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 469 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 470 471 /* Fixup for the AR8030/AR8035. This chip has another mask and 472 * doesn't support the DSP reference. Eg. the lowest bit of the 473 * mask. The upper two bits select the same frequencies. Mask 474 * the lowest bit here. 475 * 476 * Warning: 477 * There was no datasheet for the AR8030 available so this is 478 * just a guess. But the AR8035 is listed as pin compatible 479 * to the AR8030 so there might be a good chance it works on 480 * the AR8030 too. 481 */ 482 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || 483 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { 484 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 485 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 486 } 487 } 488 489 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 490 if (!ret) { 491 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 492 switch (strength) { 493 case AR803X_STRENGTH_FULL: 494 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 495 break; 496 case AR803X_STRENGTH_HALF: 497 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 498 break; 499 case AR803X_STRENGTH_QUARTER: 500 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 501 break; 502 default: 503 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 504 return -EINVAL; 505 } 506 } 507 508 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 509 * options. 510 */ 511 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 512 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 513 priv->flags |= AT803X_KEEP_PLL_ENABLED; 514 515 ret = at8031_register_regulators(phydev); 516 if (ret < 0) 517 return ret; 518 519 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 520 "vddio"); 521 if (IS_ERR(priv->vddio)) { 522 phydev_err(phydev, "failed to get VDDIO regulator\n"); 523 return PTR_ERR(priv->vddio); 524 } 525 526 ret = regulator_enable(priv->vddio); 527 if (ret < 0) 528 return ret; 529 } 530 531 return 0; 532 } 533 534 static int at803x_probe(struct phy_device *phydev) 535 { 536 struct device *dev = &phydev->mdio.dev; 537 struct at803x_priv *priv; 538 539 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 540 if (!priv) 541 return -ENOMEM; 542 543 phydev->priv = priv; 544 545 return at803x_parse_dt(phydev); 546 } 547 548 static void at803x_remove(struct phy_device *phydev) 549 { 550 struct at803x_priv *priv = phydev->priv; 551 552 if (priv->vddio) 553 regulator_disable(priv->vddio); 554 } 555 556 static int at803x_smarteee_config(struct phy_device *phydev) 557 { 558 struct at803x_priv *priv = phydev->priv; 559 u16 mask = 0, val = 0; 560 int ret; 561 562 if (priv->flags & AT803X_DISABLE_SMARTEEE) 563 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 564 AT803X_MMD3_SMARTEEE_CTL3, 565 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 566 567 if (priv->smarteee_lpi_tw_1g) { 568 mask |= 0xff00; 569 val |= priv->smarteee_lpi_tw_1g << 8; 570 } 571 if (priv->smarteee_lpi_tw_100m) { 572 mask |= 0x00ff; 573 val |= priv->smarteee_lpi_tw_100m; 574 } 575 if (!mask) 576 return 0; 577 578 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 579 mask, val); 580 if (ret) 581 return ret; 582 583 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 584 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 585 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 586 } 587 588 static int at803x_clk_out_config(struct phy_device *phydev) 589 { 590 struct at803x_priv *priv = phydev->priv; 591 592 if (!priv->clk_25m_mask) 593 return 0; 594 595 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 596 priv->clk_25m_mask, priv->clk_25m_reg); 597 } 598 599 static int at8031_pll_config(struct phy_device *phydev) 600 { 601 struct at803x_priv *priv = phydev->priv; 602 603 /* The default after hardware reset is PLL OFF. After a soft reset, the 604 * values are retained. 605 */ 606 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 607 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 608 0, AT803X_DEBUG_PLL_ON); 609 else 610 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 611 AT803X_DEBUG_PLL_ON, 0); 612 } 613 614 static int at803x_config_init(struct phy_device *phydev) 615 { 616 int ret; 617 618 /* The RX and TX delay default is: 619 * after HW reset: RX delay enabled and TX delay disabled 620 * after SW reset: RX delay enabled, while TX delay retains the 621 * value before reset. 622 */ 623 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 624 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 625 ret = at803x_enable_rx_delay(phydev); 626 else 627 ret = at803x_disable_rx_delay(phydev); 628 if (ret < 0) 629 return ret; 630 631 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 632 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 633 ret = at803x_enable_tx_delay(phydev); 634 else 635 ret = at803x_disable_tx_delay(phydev); 636 if (ret < 0) 637 return ret; 638 639 ret = at803x_smarteee_config(phydev); 640 if (ret < 0) 641 return ret; 642 643 ret = at803x_clk_out_config(phydev); 644 if (ret < 0) 645 return ret; 646 647 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 648 ret = at8031_pll_config(phydev); 649 if (ret < 0) 650 return ret; 651 } 652 653 /* Ar803x extended next page bit is enabled by default. Cisco 654 * multigig switches read this bit and attempt to negotiate 10Gbps 655 * rates even if the next page bit is disabled. This is incorrect 656 * behaviour but we still need to accommodate it. XNP is only needed 657 * for 10Gbps support, so disable XNP. 658 */ 659 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 660 } 661 662 static int at803x_ack_interrupt(struct phy_device *phydev) 663 { 664 int err; 665 666 err = phy_read(phydev, AT803X_INTR_STATUS); 667 668 return (err < 0) ? err : 0; 669 } 670 671 static int at803x_config_intr(struct phy_device *phydev) 672 { 673 int err; 674 int value; 675 676 value = phy_read(phydev, AT803X_INTR_ENABLE); 677 678 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 679 /* Clear any pending interrupts */ 680 err = at803x_ack_interrupt(phydev); 681 if (err) 682 return err; 683 684 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 685 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 686 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 687 value |= AT803X_INTR_ENABLE_LINK_FAIL; 688 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 689 690 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 691 } else { 692 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 693 if (err) 694 return err; 695 696 /* Clear any pending interrupts */ 697 err = at803x_ack_interrupt(phydev); 698 } 699 700 return err; 701 } 702 703 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 704 { 705 int irq_status, int_enabled; 706 707 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 708 if (irq_status < 0) { 709 phy_error(phydev); 710 return IRQ_NONE; 711 } 712 713 /* Read the current enabled interrupts */ 714 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 715 if (int_enabled < 0) { 716 phy_error(phydev); 717 return IRQ_NONE; 718 } 719 720 /* See if this was one of our enabled interrupts */ 721 if (!(irq_status & int_enabled)) 722 return IRQ_NONE; 723 724 phy_trigger_machine(phydev); 725 726 return IRQ_HANDLED; 727 } 728 729 static void at803x_link_change_notify(struct phy_device *phydev) 730 { 731 /* 732 * Conduct a hardware reset for AT8030 every time a link loss is 733 * signalled. This is necessary to circumvent a hardware bug that 734 * occurs when the cable is unplugged while TX packets are pending 735 * in the FIFO. In such cases, the FIFO enters an error mode it 736 * cannot recover from by software. 737 */ 738 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 739 struct at803x_context context; 740 741 at803x_context_save(phydev, &context); 742 743 phy_device_reset(phydev, 1); 744 msleep(1); 745 phy_device_reset(phydev, 0); 746 msleep(1); 747 748 at803x_context_restore(phydev, &context); 749 750 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 751 } 752 } 753 754 static int at803x_aneg_done(struct phy_device *phydev) 755 { 756 int ccr; 757 758 int aneg_done = genphy_aneg_done(phydev); 759 if (aneg_done != BMSR_ANEGCOMPLETE) 760 return aneg_done; 761 762 /* 763 * in SGMII mode, if copper side autoneg is successful, 764 * also check SGMII side autoneg result 765 */ 766 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 767 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII) 768 return aneg_done; 769 770 /* switch to SGMII/fiber page */ 771 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL); 772 773 /* check if the SGMII link is OK. */ 774 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { 775 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); 776 aneg_done = 0; 777 } 778 /* switch back to copper page */ 779 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); 780 781 return aneg_done; 782 } 783 784 static int at803x_read_status(struct phy_device *phydev) 785 { 786 int ss, err, old_link = phydev->link; 787 788 /* Update the link, but return if there was an error */ 789 err = genphy_update_link(phydev); 790 if (err) 791 return err; 792 793 /* why bother the PHY if nothing can have changed */ 794 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 795 return 0; 796 797 phydev->speed = SPEED_UNKNOWN; 798 phydev->duplex = DUPLEX_UNKNOWN; 799 phydev->pause = 0; 800 phydev->asym_pause = 0; 801 802 err = genphy_read_lpa(phydev); 803 if (err < 0) 804 return err; 805 806 /* Read the AT8035 PHY-Specific Status register, which indicates the 807 * speed and duplex that the PHY is actually using, irrespective of 808 * whether we are in autoneg mode or not. 809 */ 810 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 811 if (ss < 0) 812 return ss; 813 814 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 815 int sfc; 816 817 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 818 if (sfc < 0) 819 return sfc; 820 821 switch (ss & AT803X_SS_SPEED_MASK) { 822 case AT803X_SS_SPEED_10: 823 phydev->speed = SPEED_10; 824 break; 825 case AT803X_SS_SPEED_100: 826 phydev->speed = SPEED_100; 827 break; 828 case AT803X_SS_SPEED_1000: 829 phydev->speed = SPEED_1000; 830 break; 831 } 832 if (ss & AT803X_SS_DUPLEX) 833 phydev->duplex = DUPLEX_FULL; 834 else 835 phydev->duplex = DUPLEX_HALF; 836 837 if (ss & AT803X_SS_MDIX) 838 phydev->mdix = ETH_TP_MDI_X; 839 else 840 phydev->mdix = ETH_TP_MDI; 841 842 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 843 case AT803X_SFC_MANUAL_MDI: 844 phydev->mdix_ctrl = ETH_TP_MDI; 845 break; 846 case AT803X_SFC_MANUAL_MDIX: 847 phydev->mdix_ctrl = ETH_TP_MDI_X; 848 break; 849 case AT803X_SFC_AUTOMATIC_CROSSOVER: 850 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 851 break; 852 } 853 } 854 855 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 856 phy_resolve_aneg_pause(phydev); 857 858 return 0; 859 } 860 861 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 862 { 863 u16 val; 864 865 switch (ctrl) { 866 case ETH_TP_MDI: 867 val = AT803X_SFC_MANUAL_MDI; 868 break; 869 case ETH_TP_MDI_X: 870 val = AT803X_SFC_MANUAL_MDIX; 871 break; 872 case ETH_TP_MDI_AUTO: 873 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 874 break; 875 default: 876 return 0; 877 } 878 879 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 880 AT803X_SFC_MDI_CROSSOVER_MODE_M, 881 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 882 } 883 884 static int at803x_config_aneg(struct phy_device *phydev) 885 { 886 int ret; 887 888 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 889 if (ret < 0) 890 return ret; 891 892 /* Changes of the midx bits are disruptive to the normal operation; 893 * therefore any changes to these registers must be followed by a 894 * software reset to take effect. 895 */ 896 if (ret == 1) { 897 ret = genphy_soft_reset(phydev); 898 if (ret < 0) 899 return ret; 900 } 901 902 return genphy_config_aneg(phydev); 903 } 904 905 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 906 { 907 int val; 908 909 val = phy_read(phydev, AT803X_SMART_SPEED); 910 if (val < 0) 911 return val; 912 913 if (val & AT803X_SMART_SPEED_ENABLE) 914 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 915 else 916 *d = DOWNSHIFT_DEV_DISABLE; 917 918 return 0; 919 } 920 921 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 922 { 923 u16 mask, set; 924 int ret; 925 926 switch (cnt) { 927 case DOWNSHIFT_DEV_DEFAULT_COUNT: 928 cnt = AT803X_DEFAULT_DOWNSHIFT; 929 fallthrough; 930 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 931 set = AT803X_SMART_SPEED_ENABLE | 932 AT803X_SMART_SPEED_BYPASS_TIMER | 933 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 934 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 935 break; 936 case DOWNSHIFT_DEV_DISABLE: 937 set = 0; 938 mask = AT803X_SMART_SPEED_ENABLE | 939 AT803X_SMART_SPEED_BYPASS_TIMER; 940 break; 941 default: 942 return -EINVAL; 943 } 944 945 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 946 947 /* After changing the smart speed settings, we need to perform a 948 * software reset, use phy_init_hw() to make sure we set the 949 * reapply any values which might got lost during software reset. 950 */ 951 if (ret == 1) 952 ret = phy_init_hw(phydev); 953 954 return ret; 955 } 956 957 static int at803x_get_tunable(struct phy_device *phydev, 958 struct ethtool_tunable *tuna, void *data) 959 { 960 switch (tuna->id) { 961 case ETHTOOL_PHY_DOWNSHIFT: 962 return at803x_get_downshift(phydev, data); 963 default: 964 return -EOPNOTSUPP; 965 } 966 } 967 968 static int at803x_set_tunable(struct phy_device *phydev, 969 struct ethtool_tunable *tuna, const void *data) 970 { 971 switch (tuna->id) { 972 case ETHTOOL_PHY_DOWNSHIFT: 973 return at803x_set_downshift(phydev, *(const u8 *)data); 974 default: 975 return -EOPNOTSUPP; 976 } 977 } 978 979 static int at803x_cable_test_result_trans(u16 status) 980 { 981 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 982 case AT803X_CDT_STATUS_STAT_NORMAL: 983 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 984 case AT803X_CDT_STATUS_STAT_SHORT: 985 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 986 case AT803X_CDT_STATUS_STAT_OPEN: 987 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 988 case AT803X_CDT_STATUS_STAT_FAIL: 989 default: 990 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 991 } 992 } 993 994 static bool at803x_cdt_test_failed(u16 status) 995 { 996 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 997 AT803X_CDT_STATUS_STAT_FAIL; 998 } 999 1000 static bool at803x_cdt_fault_length_valid(u16 status) 1001 { 1002 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1003 case AT803X_CDT_STATUS_STAT_OPEN: 1004 case AT803X_CDT_STATUS_STAT_SHORT: 1005 return true; 1006 } 1007 return false; 1008 } 1009 1010 static int at803x_cdt_fault_length(u16 status) 1011 { 1012 int dt; 1013 1014 /* According to the datasheet the distance to the fault is 1015 * DELTA_TIME * 0.824 meters. 1016 * 1017 * The author suspect the correct formula is: 1018 * 1019 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1020 * 1021 * where c is the speed of light, VF is the velocity factor of 1022 * the twisted pair cable, 125MHz the counter frequency and 1023 * we need to divide by 2 because the hardware will measure the 1024 * round trip time to the fault and back to the PHY. 1025 * 1026 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1027 * datasheet. 1028 */ 1029 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1030 1031 return (dt * 824) / 10; 1032 } 1033 1034 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1035 { 1036 u16 cdt; 1037 1038 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1039 AT803X_CDT_ENABLE_TEST; 1040 1041 return phy_write(phydev, AT803X_CDT, cdt); 1042 } 1043 1044 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1045 { 1046 int val, ret; 1047 1048 /* One test run takes about 25ms */ 1049 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1050 !(val & AT803X_CDT_ENABLE_TEST), 1051 30000, 100000, true); 1052 1053 return ret < 0 ? ret : 0; 1054 } 1055 1056 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1057 { 1058 static const int ethtool_pair[] = { 1059 ETHTOOL_A_CABLE_PAIR_A, 1060 ETHTOOL_A_CABLE_PAIR_B, 1061 ETHTOOL_A_CABLE_PAIR_C, 1062 ETHTOOL_A_CABLE_PAIR_D, 1063 }; 1064 int ret, val; 1065 1066 ret = at803x_cdt_start(phydev, pair); 1067 if (ret) 1068 return ret; 1069 1070 ret = at803x_cdt_wait_for_completion(phydev); 1071 if (ret) 1072 return ret; 1073 1074 val = phy_read(phydev, AT803X_CDT_STATUS); 1075 if (val < 0) 1076 return val; 1077 1078 if (at803x_cdt_test_failed(val)) 1079 return 0; 1080 1081 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1082 at803x_cable_test_result_trans(val)); 1083 1084 if (at803x_cdt_fault_length_valid(val)) 1085 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1086 at803x_cdt_fault_length(val)); 1087 1088 return 1; 1089 } 1090 1091 static int at803x_cable_test_get_status(struct phy_device *phydev, 1092 bool *finished) 1093 { 1094 unsigned long pair_mask; 1095 int retries = 20; 1096 int pair, ret; 1097 1098 if (phydev->phy_id == ATH9331_PHY_ID || 1099 phydev->phy_id == ATH8032_PHY_ID) 1100 pair_mask = 0x3; 1101 else 1102 pair_mask = 0xf; 1103 1104 *finished = false; 1105 1106 /* According to the datasheet the CDT can be performed when 1107 * there is no link partner or when the link partner is 1108 * auto-negotiating. Starting the test will restart the AN 1109 * automatically. It seems that doing this repeatedly we will 1110 * get a slot where our link partner won't disturb our 1111 * measurement. 1112 */ 1113 while (pair_mask && retries--) { 1114 for_each_set_bit(pair, &pair_mask, 4) { 1115 ret = at803x_cable_test_one_pair(phydev, pair); 1116 if (ret < 0) 1117 return ret; 1118 if (ret) 1119 clear_bit(pair, &pair_mask); 1120 } 1121 if (pair_mask) 1122 msleep(250); 1123 } 1124 1125 *finished = true; 1126 1127 return 0; 1128 } 1129 1130 static int at803x_cable_test_start(struct phy_device *phydev) 1131 { 1132 /* Enable auto-negotiation, but advertise no capabilities, no link 1133 * will be established. A restart of the auto-negotiation is not 1134 * required, because the cable test will automatically break the link. 1135 */ 1136 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1137 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1138 if (phydev->phy_id != ATH9331_PHY_ID && 1139 phydev->phy_id != ATH8032_PHY_ID) 1140 phy_write(phydev, MII_CTRL1000, 0); 1141 1142 /* we do all the (time consuming) work later */ 1143 return 0; 1144 } 1145 1146 static struct phy_driver at803x_driver[] = { 1147 { 1148 /* Qualcomm Atheros AR8035 */ 1149 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1150 .name = "Qualcomm Atheros AR8035", 1151 .flags = PHY_POLL_CABLE_TEST, 1152 .probe = at803x_probe, 1153 .remove = at803x_remove, 1154 .config_aneg = at803x_config_aneg, 1155 .config_init = at803x_config_init, 1156 .soft_reset = genphy_soft_reset, 1157 .set_wol = at803x_set_wol, 1158 .get_wol = at803x_get_wol, 1159 .suspend = at803x_suspend, 1160 .resume = at803x_resume, 1161 /* PHY_GBIT_FEATURES */ 1162 .read_status = at803x_read_status, 1163 .config_intr = at803x_config_intr, 1164 .handle_interrupt = at803x_handle_interrupt, 1165 .get_tunable = at803x_get_tunable, 1166 .set_tunable = at803x_set_tunable, 1167 .cable_test_start = at803x_cable_test_start, 1168 .cable_test_get_status = at803x_cable_test_get_status, 1169 }, { 1170 /* Qualcomm Atheros AR8030 */ 1171 .phy_id = ATH8030_PHY_ID, 1172 .name = "Qualcomm Atheros AR8030", 1173 .phy_id_mask = AT8030_PHY_ID_MASK, 1174 .probe = at803x_probe, 1175 .remove = at803x_remove, 1176 .config_init = at803x_config_init, 1177 .link_change_notify = at803x_link_change_notify, 1178 .set_wol = at803x_set_wol, 1179 .get_wol = at803x_get_wol, 1180 .suspend = at803x_suspend, 1181 .resume = at803x_resume, 1182 /* PHY_BASIC_FEATURES */ 1183 .config_intr = at803x_config_intr, 1184 .handle_interrupt = at803x_handle_interrupt, 1185 }, { 1186 /* Qualcomm Atheros AR8031/AR8033 */ 1187 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1188 .name = "Qualcomm Atheros AR8031/AR8033", 1189 .flags = PHY_POLL_CABLE_TEST, 1190 .probe = at803x_probe, 1191 .remove = at803x_remove, 1192 .config_init = at803x_config_init, 1193 .config_aneg = at803x_config_aneg, 1194 .soft_reset = genphy_soft_reset, 1195 .set_wol = at803x_set_wol, 1196 .get_wol = at803x_get_wol, 1197 .suspend = at803x_suspend, 1198 .resume = at803x_resume, 1199 /* PHY_GBIT_FEATURES */ 1200 .read_status = at803x_read_status, 1201 .aneg_done = at803x_aneg_done, 1202 .config_intr = &at803x_config_intr, 1203 .handle_interrupt = at803x_handle_interrupt, 1204 .get_tunable = at803x_get_tunable, 1205 .set_tunable = at803x_set_tunable, 1206 .cable_test_start = at803x_cable_test_start, 1207 .cable_test_get_status = at803x_cable_test_get_status, 1208 }, { 1209 /* Qualcomm Atheros AR8032 */ 1210 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1211 .name = "Qualcomm Atheros AR8032", 1212 .probe = at803x_probe, 1213 .remove = at803x_remove, 1214 .flags = PHY_POLL_CABLE_TEST, 1215 .config_init = at803x_config_init, 1216 .link_change_notify = at803x_link_change_notify, 1217 .set_wol = at803x_set_wol, 1218 .get_wol = at803x_get_wol, 1219 .suspend = at803x_suspend, 1220 .resume = at803x_resume, 1221 /* PHY_BASIC_FEATURES */ 1222 .config_intr = at803x_config_intr, 1223 .handle_interrupt = at803x_handle_interrupt, 1224 .cable_test_start = at803x_cable_test_start, 1225 .cable_test_get_status = at803x_cable_test_get_status, 1226 }, { 1227 /* ATHEROS AR9331 */ 1228 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1229 .name = "Qualcomm Atheros AR9331 built-in PHY", 1230 .suspend = at803x_suspend, 1231 .resume = at803x_resume, 1232 .flags = PHY_POLL_CABLE_TEST, 1233 /* PHY_BASIC_FEATURES */ 1234 .config_intr = &at803x_config_intr, 1235 .handle_interrupt = at803x_handle_interrupt, 1236 .cable_test_start = at803x_cable_test_start, 1237 .cable_test_get_status = at803x_cable_test_get_status, 1238 .read_status = at803x_read_status, 1239 .soft_reset = genphy_soft_reset, 1240 .config_aneg = at803x_config_aneg, 1241 } }; 1242 1243 module_phy_driver(at803x_driver); 1244 1245 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1246 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1247 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1248 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1249 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1250 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1251 { } 1252 }; 1253 1254 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1255