1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <dt-bindings/net/qca-ar803x.h> 23 24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 25 #define AT803X_SFC_ASSERT_CRS BIT(11) 26 #define AT803X_SFC_FORCE_LINK BIT(10) 27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 29 #define AT803X_SFC_MANUAL_MDIX 0x1 30 #define AT803X_SFC_MANUAL_MDI 0x0 31 #define AT803X_SFC_SQE_TEST BIT(2) 32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 33 #define AT803X_SFC_DISABLE_JABBER BIT(0) 34 35 #define AT803X_SPECIFIC_STATUS 0x11 36 #define AT803X_SS_SPEED_MASK (3 << 14) 37 #define AT803X_SS_SPEED_1000 (2 << 14) 38 #define AT803X_SS_SPEED_100 (1 << 14) 39 #define AT803X_SS_SPEED_10 (0 << 14) 40 #define AT803X_SS_DUPLEX BIT(13) 41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 42 #define AT803X_SS_MDIX BIT(6) 43 44 #define AT803X_INTR_ENABLE 0x12 45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 53 #define AT803X_INTR_ENABLE_WOL BIT(0) 54 55 #define AT803X_INTR_STATUS 0x13 56 57 #define AT803X_SMART_SPEED 0x14 58 #define AT803X_SMART_SPEED_ENABLE BIT(5) 59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 61 #define AT803X_CDT 0x16 62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 63 #define AT803X_CDT_ENABLE_TEST BIT(0) 64 #define AT803X_CDT_STATUS 0x1c 65 #define AT803X_CDT_STATUS_STAT_NORMAL 0 66 #define AT803X_CDT_STATUS_STAT_SHORT 1 67 #define AT803X_CDT_STATUS_STAT_OPEN 2 68 #define AT803X_CDT_STATUS_STAT_FAIL 3 69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 71 #define AT803X_LED_CONTROL 0x18 72 73 #define AT803X_DEVICE_ADDR 0x03 74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 77 #define AT803X_REG_CHIP_CONFIG 0x1f 78 #define AT803X_BT_BX_REG_SEL 0x8000 79 80 #define AT803X_DEBUG_ADDR 0x1D 81 #define AT803X_DEBUG_DATA 0x1E 82 83 #define AT803X_MODE_CFG_MASK 0x0F 84 #define AT803X_MODE_CFG_SGMII 0x01 85 86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 88 89 #define AT803X_DEBUG_REG_0 0x00 90 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 91 92 #define AT803X_DEBUG_REG_5 0x05 93 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 94 95 #define AT803X_DEBUG_REG_3C 0x3C 96 97 #define AT803X_DEBUG_REG_3D 0x3D 98 99 #define AT803X_DEBUG_REG_1F 0x1F 100 #define AT803X_DEBUG_PLL_ON BIT(2) 101 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 102 103 #define MDIO_AZ_DEBUG 0x800D 104 105 /* AT803x supports either the XTAL input pad, an internal PLL or the 106 * DSP as clock reference for the clock output pad. The XTAL reference 107 * is only used for 25 MHz output, all other frequencies need the PLL. 108 * The DSP as a clock reference is used in synchronous ethernet 109 * applications. 110 * 111 * By default the PLL is only enabled if there is a link. Otherwise 112 * the PHY will go into low power state and disabled the PLL. You can 113 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 114 * enabled. 115 */ 116 #define AT803X_MMD7_CLK25M 0x8016 117 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 118 #define AT803X_CLK_OUT_25MHZ_XTAL 0 119 #define AT803X_CLK_OUT_25MHZ_DSP 1 120 #define AT803X_CLK_OUT_50MHZ_PLL 2 121 #define AT803X_CLK_OUT_50MHZ_DSP 3 122 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 123 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 124 #define AT803X_CLK_OUT_125MHZ_PLL 6 125 #define AT803X_CLK_OUT_125MHZ_DSP 7 126 127 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 128 * but doesn't support choosing between XTAL/PLL and DSP. 129 */ 130 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 131 132 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 133 #define AT803X_CLK_OUT_STRENGTH_FULL 0 134 #define AT803X_CLK_OUT_STRENGTH_HALF 1 135 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 136 137 #define AT803X_DEFAULT_DOWNSHIFT 5 138 #define AT803X_MIN_DOWNSHIFT 2 139 #define AT803X_MAX_DOWNSHIFT 9 140 141 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 142 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 143 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 144 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 145 146 #define ATH9331_PHY_ID 0x004dd041 147 #define ATH8030_PHY_ID 0x004dd076 148 #define ATH8031_PHY_ID 0x004dd074 149 #define ATH8032_PHY_ID 0x004dd023 150 #define ATH8035_PHY_ID 0x004dd072 151 #define AT8030_PHY_ID_MASK 0xffffffef 152 153 #define QCA8327_PHY_ID 0x004dd034 154 #define QCA8337_PHY_ID 0x004dd036 155 #define QCA8K_PHY_ID_MASK 0xffffffff 156 157 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 158 159 #define AT803X_PAGE_FIBER 0 160 #define AT803X_PAGE_COPPER 1 161 162 /* don't turn off internal PLL */ 163 #define AT803X_KEEP_PLL_ENABLED BIT(0) 164 #define AT803X_DISABLE_SMARTEEE BIT(1) 165 166 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 167 MODULE_AUTHOR("Matus Ujhelyi"); 168 MODULE_LICENSE("GPL"); 169 170 enum stat_access_type { 171 PHY, 172 MMD 173 }; 174 175 struct at803x_hw_stat { 176 const char *string; 177 u8 reg; 178 u32 mask; 179 enum stat_access_type access_type; 180 }; 181 182 static struct at803x_hw_stat at803x_hw_stats[] = { 183 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 184 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 185 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 186 }; 187 188 struct at803x_priv { 189 int flags; 190 u16 clk_25m_reg; 191 u16 clk_25m_mask; 192 u8 smarteee_lpi_tw_1g; 193 u8 smarteee_lpi_tw_100m; 194 struct regulator_dev *vddio_rdev; 195 struct regulator_dev *vddh_rdev; 196 struct regulator *vddio; 197 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 198 }; 199 200 struct at803x_context { 201 u16 bmcr; 202 u16 advertise; 203 u16 control1000; 204 u16 int_enable; 205 u16 smart_speed; 206 u16 led_control; 207 }; 208 209 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 210 { 211 int ret; 212 213 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 214 if (ret < 0) 215 return ret; 216 217 return phy_write(phydev, AT803X_DEBUG_DATA, data); 218 } 219 220 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 221 { 222 int ret; 223 224 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 225 if (ret < 0) 226 return ret; 227 228 return phy_read(phydev, AT803X_DEBUG_DATA); 229 } 230 231 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 232 u16 clear, u16 set) 233 { 234 u16 val; 235 int ret; 236 237 ret = at803x_debug_reg_read(phydev, reg); 238 if (ret < 0) 239 return ret; 240 241 val = ret & 0xffff; 242 val &= ~clear; 243 val |= set; 244 245 return phy_write(phydev, AT803X_DEBUG_DATA, val); 246 } 247 248 static int at803x_write_page(struct phy_device *phydev, int page) 249 { 250 int mask; 251 int set; 252 253 if (page == AT803X_PAGE_COPPER) { 254 set = AT803X_BT_BX_REG_SEL; 255 mask = 0; 256 } else { 257 set = 0; 258 mask = AT803X_BT_BX_REG_SEL; 259 } 260 261 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 262 } 263 264 static int at803x_read_page(struct phy_device *phydev) 265 { 266 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 267 268 if (ccr < 0) 269 return ccr; 270 271 if (ccr & AT803X_BT_BX_REG_SEL) 272 return AT803X_PAGE_COPPER; 273 274 return AT803X_PAGE_FIBER; 275 } 276 277 static int at803x_enable_rx_delay(struct phy_device *phydev) 278 { 279 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 280 AT803X_DEBUG_RX_CLK_DLY_EN); 281 } 282 283 static int at803x_enable_tx_delay(struct phy_device *phydev) 284 { 285 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 286 AT803X_DEBUG_TX_CLK_DLY_EN); 287 } 288 289 static int at803x_disable_rx_delay(struct phy_device *phydev) 290 { 291 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 292 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 293 } 294 295 static int at803x_disable_tx_delay(struct phy_device *phydev) 296 { 297 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 298 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 299 } 300 301 /* save relevant PHY registers to private copy */ 302 static void at803x_context_save(struct phy_device *phydev, 303 struct at803x_context *context) 304 { 305 context->bmcr = phy_read(phydev, MII_BMCR); 306 context->advertise = phy_read(phydev, MII_ADVERTISE); 307 context->control1000 = phy_read(phydev, MII_CTRL1000); 308 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 309 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 310 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 311 } 312 313 /* restore relevant PHY registers from private copy */ 314 static void at803x_context_restore(struct phy_device *phydev, 315 const struct at803x_context *context) 316 { 317 phy_write(phydev, MII_BMCR, context->bmcr); 318 phy_write(phydev, MII_ADVERTISE, context->advertise); 319 phy_write(phydev, MII_CTRL1000, context->control1000); 320 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 321 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 322 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 323 } 324 325 static int at803x_set_wol(struct phy_device *phydev, 326 struct ethtool_wolinfo *wol) 327 { 328 struct net_device *ndev = phydev->attached_dev; 329 const u8 *mac; 330 int ret; 331 u32 value; 332 unsigned int i, offsets[] = { 333 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 334 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 335 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 336 }; 337 338 if (!ndev) 339 return -ENODEV; 340 341 if (wol->wolopts & WAKE_MAGIC) { 342 mac = (const u8 *) ndev->dev_addr; 343 344 if (!is_valid_ether_addr(mac)) 345 return -EINVAL; 346 347 for (i = 0; i < 3; i++) 348 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 349 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 350 351 value = phy_read(phydev, AT803X_INTR_ENABLE); 352 value |= AT803X_INTR_ENABLE_WOL; 353 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 354 if (ret) 355 return ret; 356 value = phy_read(phydev, AT803X_INTR_STATUS); 357 } else { 358 value = phy_read(phydev, AT803X_INTR_ENABLE); 359 value &= (~AT803X_INTR_ENABLE_WOL); 360 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 361 if (ret) 362 return ret; 363 value = phy_read(phydev, AT803X_INTR_STATUS); 364 } 365 366 return ret; 367 } 368 369 static void at803x_get_wol(struct phy_device *phydev, 370 struct ethtool_wolinfo *wol) 371 { 372 u32 value; 373 374 wol->supported = WAKE_MAGIC; 375 wol->wolopts = 0; 376 377 value = phy_read(phydev, AT803X_INTR_ENABLE); 378 if (value & AT803X_INTR_ENABLE_WOL) 379 wol->wolopts |= WAKE_MAGIC; 380 } 381 382 static int at803x_get_sset_count(struct phy_device *phydev) 383 { 384 return ARRAY_SIZE(at803x_hw_stats); 385 } 386 387 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 388 { 389 int i; 390 391 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 392 strscpy(data + i * ETH_GSTRING_LEN, 393 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 394 } 395 } 396 397 static u64 at803x_get_stat(struct phy_device *phydev, int i) 398 { 399 struct at803x_hw_stat stat = at803x_hw_stats[i]; 400 struct at803x_priv *priv = phydev->priv; 401 int val; 402 u64 ret; 403 404 if (stat.access_type == MMD) 405 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 406 else 407 val = phy_read(phydev, stat.reg); 408 409 if (val < 0) { 410 ret = U64_MAX; 411 } else { 412 val = val & stat.mask; 413 priv->stats[i] += val; 414 ret = priv->stats[i]; 415 } 416 417 return ret; 418 } 419 420 static void at803x_get_stats(struct phy_device *phydev, 421 struct ethtool_stats *stats, u64 *data) 422 { 423 int i; 424 425 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 426 data[i] = at803x_get_stat(phydev, i); 427 } 428 429 static int at803x_suspend(struct phy_device *phydev) 430 { 431 int value; 432 int wol_enabled; 433 434 value = phy_read(phydev, AT803X_INTR_ENABLE); 435 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 436 437 if (wol_enabled) 438 value = BMCR_ISOLATE; 439 else 440 value = BMCR_PDOWN; 441 442 phy_modify(phydev, MII_BMCR, 0, value); 443 444 return 0; 445 } 446 447 static int at803x_resume(struct phy_device *phydev) 448 { 449 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 450 } 451 452 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 453 unsigned int selector) 454 { 455 struct phy_device *phydev = rdev_get_drvdata(rdev); 456 457 if (selector) 458 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 459 0, AT803X_DEBUG_RGMII_1V8); 460 else 461 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 462 AT803X_DEBUG_RGMII_1V8, 0); 463 } 464 465 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 466 { 467 struct phy_device *phydev = rdev_get_drvdata(rdev); 468 int val; 469 470 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 471 if (val < 0) 472 return val; 473 474 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 475 } 476 477 static const struct regulator_ops vddio_regulator_ops = { 478 .list_voltage = regulator_list_voltage_table, 479 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 480 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 481 }; 482 483 static const unsigned int vddio_voltage_table[] = { 484 1500000, 485 1800000, 486 }; 487 488 static const struct regulator_desc vddio_desc = { 489 .name = "vddio", 490 .of_match = of_match_ptr("vddio-regulator"), 491 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 492 .volt_table = vddio_voltage_table, 493 .ops = &vddio_regulator_ops, 494 .type = REGULATOR_VOLTAGE, 495 .owner = THIS_MODULE, 496 }; 497 498 static const struct regulator_ops vddh_regulator_ops = { 499 }; 500 501 static const struct regulator_desc vddh_desc = { 502 .name = "vddh", 503 .of_match = of_match_ptr("vddh-regulator"), 504 .n_voltages = 1, 505 .fixed_uV = 2500000, 506 .ops = &vddh_regulator_ops, 507 .type = REGULATOR_VOLTAGE, 508 .owner = THIS_MODULE, 509 }; 510 511 static int at8031_register_regulators(struct phy_device *phydev) 512 { 513 struct at803x_priv *priv = phydev->priv; 514 struct device *dev = &phydev->mdio.dev; 515 struct regulator_config config = { }; 516 517 config.dev = dev; 518 config.driver_data = phydev; 519 520 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 521 if (IS_ERR(priv->vddio_rdev)) { 522 phydev_err(phydev, "failed to register VDDIO regulator\n"); 523 return PTR_ERR(priv->vddio_rdev); 524 } 525 526 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 527 if (IS_ERR(priv->vddh_rdev)) { 528 phydev_err(phydev, "failed to register VDDH regulator\n"); 529 return PTR_ERR(priv->vddh_rdev); 530 } 531 532 return 0; 533 } 534 535 static int at803x_parse_dt(struct phy_device *phydev) 536 { 537 struct device_node *node = phydev->mdio.dev.of_node; 538 struct at803x_priv *priv = phydev->priv; 539 u32 freq, strength, tw; 540 unsigned int sel; 541 int ret; 542 543 if (!IS_ENABLED(CONFIG_OF_MDIO)) 544 return 0; 545 546 if (of_property_read_bool(node, "qca,disable-smarteee")) 547 priv->flags |= AT803X_DISABLE_SMARTEEE; 548 549 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 550 if (!tw || tw > 255) { 551 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 552 return -EINVAL; 553 } 554 priv->smarteee_lpi_tw_1g = tw; 555 } 556 557 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 558 if (!tw || tw > 255) { 559 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 560 return -EINVAL; 561 } 562 priv->smarteee_lpi_tw_100m = tw; 563 } 564 565 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 566 if (!ret) { 567 switch (freq) { 568 case 25000000: 569 sel = AT803X_CLK_OUT_25MHZ_XTAL; 570 break; 571 case 50000000: 572 sel = AT803X_CLK_OUT_50MHZ_PLL; 573 break; 574 case 62500000: 575 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 576 break; 577 case 125000000: 578 sel = AT803X_CLK_OUT_125MHZ_PLL; 579 break; 580 default: 581 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 582 return -EINVAL; 583 } 584 585 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 586 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 587 588 /* Fixup for the AR8030/AR8035. This chip has another mask and 589 * doesn't support the DSP reference. Eg. the lowest bit of the 590 * mask. The upper two bits select the same frequencies. Mask 591 * the lowest bit here. 592 * 593 * Warning: 594 * There was no datasheet for the AR8030 available so this is 595 * just a guess. But the AR8035 is listed as pin compatible 596 * to the AR8030 so there might be a good chance it works on 597 * the AR8030 too. 598 */ 599 if (phydev->drv->phy_id == ATH8030_PHY_ID || 600 phydev->drv->phy_id == ATH8035_PHY_ID) { 601 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 602 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 603 } 604 } 605 606 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 607 if (!ret) { 608 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 609 switch (strength) { 610 case AR803X_STRENGTH_FULL: 611 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 612 break; 613 case AR803X_STRENGTH_HALF: 614 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 615 break; 616 case AR803X_STRENGTH_QUARTER: 617 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 618 break; 619 default: 620 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 621 return -EINVAL; 622 } 623 } 624 625 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 626 * options. 627 */ 628 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 629 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 630 priv->flags |= AT803X_KEEP_PLL_ENABLED; 631 632 ret = at8031_register_regulators(phydev); 633 if (ret < 0) 634 return ret; 635 636 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 637 "vddio"); 638 if (IS_ERR(priv->vddio)) { 639 phydev_err(phydev, "failed to get VDDIO regulator\n"); 640 return PTR_ERR(priv->vddio); 641 } 642 } 643 644 return 0; 645 } 646 647 static int at803x_probe(struct phy_device *phydev) 648 { 649 struct device *dev = &phydev->mdio.dev; 650 struct at803x_priv *priv; 651 int ret; 652 653 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 654 if (!priv) 655 return -ENOMEM; 656 657 phydev->priv = priv; 658 659 ret = at803x_parse_dt(phydev); 660 if (ret) 661 return ret; 662 663 if (priv->vddio) { 664 ret = regulator_enable(priv->vddio); 665 if (ret < 0) 666 return ret; 667 } 668 669 /* Some bootloaders leave the fiber page selected. 670 * Switch to the copper page, as otherwise we read 671 * the PHY capabilities from the fiber side. 672 */ 673 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 674 phy_lock_mdio_bus(phydev); 675 ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); 676 phy_unlock_mdio_bus(phydev); 677 if (ret) 678 goto err; 679 } 680 681 return 0; 682 683 err: 684 if (priv->vddio) 685 regulator_disable(priv->vddio); 686 687 return ret; 688 } 689 690 static void at803x_remove(struct phy_device *phydev) 691 { 692 struct at803x_priv *priv = phydev->priv; 693 694 if (priv->vddio) 695 regulator_disable(priv->vddio); 696 } 697 698 static int at803x_get_features(struct phy_device *phydev) 699 { 700 int err; 701 702 err = genphy_read_abilities(phydev); 703 if (err) 704 return err; 705 706 if (phydev->drv->phy_id != ATH8031_PHY_ID) 707 return 0; 708 709 /* AR8031/AR8033 have different status registers 710 * for copper and fiber operation. However, the 711 * extended status register is the same for both 712 * operation modes. 713 * 714 * As a result of that, ESTATUS_1000_XFULL is set 715 * to 1 even when operating in copper TP mode. 716 * 717 * Remove this mode from the supported link modes, 718 * as this driver currently only supports copper 719 * operation. 720 */ 721 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 722 phydev->supported); 723 return 0; 724 } 725 726 static int at803x_smarteee_config(struct phy_device *phydev) 727 { 728 struct at803x_priv *priv = phydev->priv; 729 u16 mask = 0, val = 0; 730 int ret; 731 732 if (priv->flags & AT803X_DISABLE_SMARTEEE) 733 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 734 AT803X_MMD3_SMARTEEE_CTL3, 735 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 736 737 if (priv->smarteee_lpi_tw_1g) { 738 mask |= 0xff00; 739 val |= priv->smarteee_lpi_tw_1g << 8; 740 } 741 if (priv->smarteee_lpi_tw_100m) { 742 mask |= 0x00ff; 743 val |= priv->smarteee_lpi_tw_100m; 744 } 745 if (!mask) 746 return 0; 747 748 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 749 mask, val); 750 if (ret) 751 return ret; 752 753 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 754 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 755 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 756 } 757 758 static int at803x_clk_out_config(struct phy_device *phydev) 759 { 760 struct at803x_priv *priv = phydev->priv; 761 762 if (!priv->clk_25m_mask) 763 return 0; 764 765 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 766 priv->clk_25m_mask, priv->clk_25m_reg); 767 } 768 769 static int at8031_pll_config(struct phy_device *phydev) 770 { 771 struct at803x_priv *priv = phydev->priv; 772 773 /* The default after hardware reset is PLL OFF. After a soft reset, the 774 * values are retained. 775 */ 776 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 777 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 778 0, AT803X_DEBUG_PLL_ON); 779 else 780 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 781 AT803X_DEBUG_PLL_ON, 0); 782 } 783 784 static int at803x_config_init(struct phy_device *phydev) 785 { 786 int ret; 787 788 /* The RX and TX delay default is: 789 * after HW reset: RX delay enabled and TX delay disabled 790 * after SW reset: RX delay enabled, while TX delay retains the 791 * value before reset. 792 */ 793 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 794 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 795 ret = at803x_enable_rx_delay(phydev); 796 else 797 ret = at803x_disable_rx_delay(phydev); 798 if (ret < 0) 799 return ret; 800 801 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 802 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 803 ret = at803x_enable_tx_delay(phydev); 804 else 805 ret = at803x_disable_tx_delay(phydev); 806 if (ret < 0) 807 return ret; 808 809 ret = at803x_smarteee_config(phydev); 810 if (ret < 0) 811 return ret; 812 813 ret = at803x_clk_out_config(phydev); 814 if (ret < 0) 815 return ret; 816 817 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 818 ret = at8031_pll_config(phydev); 819 if (ret < 0) 820 return ret; 821 } 822 823 /* Ar803x extended next page bit is enabled by default. Cisco 824 * multigig switches read this bit and attempt to negotiate 10Gbps 825 * rates even if the next page bit is disabled. This is incorrect 826 * behaviour but we still need to accommodate it. XNP is only needed 827 * for 10Gbps support, so disable XNP. 828 */ 829 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 830 } 831 832 static int at803x_ack_interrupt(struct phy_device *phydev) 833 { 834 int err; 835 836 err = phy_read(phydev, AT803X_INTR_STATUS); 837 838 return (err < 0) ? err : 0; 839 } 840 841 static int at803x_config_intr(struct phy_device *phydev) 842 { 843 int err; 844 int value; 845 846 value = phy_read(phydev, AT803X_INTR_ENABLE); 847 848 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 849 /* Clear any pending interrupts */ 850 err = at803x_ack_interrupt(phydev); 851 if (err) 852 return err; 853 854 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 855 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 856 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 857 value |= AT803X_INTR_ENABLE_LINK_FAIL; 858 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 859 860 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 861 } else { 862 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 863 if (err) 864 return err; 865 866 /* Clear any pending interrupts */ 867 err = at803x_ack_interrupt(phydev); 868 } 869 870 return err; 871 } 872 873 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 874 { 875 int irq_status, int_enabled; 876 877 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 878 if (irq_status < 0) { 879 phy_error(phydev); 880 return IRQ_NONE; 881 } 882 883 /* Read the current enabled interrupts */ 884 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 885 if (int_enabled < 0) { 886 phy_error(phydev); 887 return IRQ_NONE; 888 } 889 890 /* See if this was one of our enabled interrupts */ 891 if (!(irq_status & int_enabled)) 892 return IRQ_NONE; 893 894 phy_trigger_machine(phydev); 895 896 return IRQ_HANDLED; 897 } 898 899 static void at803x_link_change_notify(struct phy_device *phydev) 900 { 901 /* 902 * Conduct a hardware reset for AT8030 every time a link loss is 903 * signalled. This is necessary to circumvent a hardware bug that 904 * occurs when the cable is unplugged while TX packets are pending 905 * in the FIFO. In such cases, the FIFO enters an error mode it 906 * cannot recover from by software. 907 */ 908 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 909 struct at803x_context context; 910 911 at803x_context_save(phydev, &context); 912 913 phy_device_reset(phydev, 1); 914 msleep(1); 915 phy_device_reset(phydev, 0); 916 msleep(1); 917 918 at803x_context_restore(phydev, &context); 919 920 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 921 } 922 } 923 924 static int at803x_read_status(struct phy_device *phydev) 925 { 926 int ss, err, old_link = phydev->link; 927 928 /* Update the link, but return if there was an error */ 929 err = genphy_update_link(phydev); 930 if (err) 931 return err; 932 933 /* why bother the PHY if nothing can have changed */ 934 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 935 return 0; 936 937 phydev->speed = SPEED_UNKNOWN; 938 phydev->duplex = DUPLEX_UNKNOWN; 939 phydev->pause = 0; 940 phydev->asym_pause = 0; 941 942 err = genphy_read_lpa(phydev); 943 if (err < 0) 944 return err; 945 946 /* Read the AT8035 PHY-Specific Status register, which indicates the 947 * speed and duplex that the PHY is actually using, irrespective of 948 * whether we are in autoneg mode or not. 949 */ 950 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 951 if (ss < 0) 952 return ss; 953 954 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 955 int sfc; 956 957 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 958 if (sfc < 0) 959 return sfc; 960 961 switch (ss & AT803X_SS_SPEED_MASK) { 962 case AT803X_SS_SPEED_10: 963 phydev->speed = SPEED_10; 964 break; 965 case AT803X_SS_SPEED_100: 966 phydev->speed = SPEED_100; 967 break; 968 case AT803X_SS_SPEED_1000: 969 phydev->speed = SPEED_1000; 970 break; 971 } 972 if (ss & AT803X_SS_DUPLEX) 973 phydev->duplex = DUPLEX_FULL; 974 else 975 phydev->duplex = DUPLEX_HALF; 976 977 if (ss & AT803X_SS_MDIX) 978 phydev->mdix = ETH_TP_MDI_X; 979 else 980 phydev->mdix = ETH_TP_MDI; 981 982 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 983 case AT803X_SFC_MANUAL_MDI: 984 phydev->mdix_ctrl = ETH_TP_MDI; 985 break; 986 case AT803X_SFC_MANUAL_MDIX: 987 phydev->mdix_ctrl = ETH_TP_MDI_X; 988 break; 989 case AT803X_SFC_AUTOMATIC_CROSSOVER: 990 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 991 break; 992 } 993 } 994 995 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 996 phy_resolve_aneg_pause(phydev); 997 998 return 0; 999 } 1000 1001 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 1002 { 1003 u16 val; 1004 1005 switch (ctrl) { 1006 case ETH_TP_MDI: 1007 val = AT803X_SFC_MANUAL_MDI; 1008 break; 1009 case ETH_TP_MDI_X: 1010 val = AT803X_SFC_MANUAL_MDIX; 1011 break; 1012 case ETH_TP_MDI_AUTO: 1013 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 1014 break; 1015 default: 1016 return 0; 1017 } 1018 1019 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 1020 AT803X_SFC_MDI_CROSSOVER_MODE_M, 1021 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1022 } 1023 1024 static int at803x_config_aneg(struct phy_device *phydev) 1025 { 1026 int ret; 1027 1028 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1029 if (ret < 0) 1030 return ret; 1031 1032 /* Changes of the midx bits are disruptive to the normal operation; 1033 * therefore any changes to these registers must be followed by a 1034 * software reset to take effect. 1035 */ 1036 if (ret == 1) { 1037 ret = genphy_soft_reset(phydev); 1038 if (ret < 0) 1039 return ret; 1040 } 1041 1042 return genphy_config_aneg(phydev); 1043 } 1044 1045 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1046 { 1047 int val; 1048 1049 val = phy_read(phydev, AT803X_SMART_SPEED); 1050 if (val < 0) 1051 return val; 1052 1053 if (val & AT803X_SMART_SPEED_ENABLE) 1054 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1055 else 1056 *d = DOWNSHIFT_DEV_DISABLE; 1057 1058 return 0; 1059 } 1060 1061 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1062 { 1063 u16 mask, set; 1064 int ret; 1065 1066 switch (cnt) { 1067 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1068 cnt = AT803X_DEFAULT_DOWNSHIFT; 1069 fallthrough; 1070 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1071 set = AT803X_SMART_SPEED_ENABLE | 1072 AT803X_SMART_SPEED_BYPASS_TIMER | 1073 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1074 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1075 break; 1076 case DOWNSHIFT_DEV_DISABLE: 1077 set = 0; 1078 mask = AT803X_SMART_SPEED_ENABLE | 1079 AT803X_SMART_SPEED_BYPASS_TIMER; 1080 break; 1081 default: 1082 return -EINVAL; 1083 } 1084 1085 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1086 1087 /* After changing the smart speed settings, we need to perform a 1088 * software reset, use phy_init_hw() to make sure we set the 1089 * reapply any values which might got lost during software reset. 1090 */ 1091 if (ret == 1) 1092 ret = phy_init_hw(phydev); 1093 1094 return ret; 1095 } 1096 1097 static int at803x_get_tunable(struct phy_device *phydev, 1098 struct ethtool_tunable *tuna, void *data) 1099 { 1100 switch (tuna->id) { 1101 case ETHTOOL_PHY_DOWNSHIFT: 1102 return at803x_get_downshift(phydev, data); 1103 default: 1104 return -EOPNOTSUPP; 1105 } 1106 } 1107 1108 static int at803x_set_tunable(struct phy_device *phydev, 1109 struct ethtool_tunable *tuna, const void *data) 1110 { 1111 switch (tuna->id) { 1112 case ETHTOOL_PHY_DOWNSHIFT: 1113 return at803x_set_downshift(phydev, *(const u8 *)data); 1114 default: 1115 return -EOPNOTSUPP; 1116 } 1117 } 1118 1119 static int at803x_cable_test_result_trans(u16 status) 1120 { 1121 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1122 case AT803X_CDT_STATUS_STAT_NORMAL: 1123 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1124 case AT803X_CDT_STATUS_STAT_SHORT: 1125 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1126 case AT803X_CDT_STATUS_STAT_OPEN: 1127 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1128 case AT803X_CDT_STATUS_STAT_FAIL: 1129 default: 1130 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1131 } 1132 } 1133 1134 static bool at803x_cdt_test_failed(u16 status) 1135 { 1136 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1137 AT803X_CDT_STATUS_STAT_FAIL; 1138 } 1139 1140 static bool at803x_cdt_fault_length_valid(u16 status) 1141 { 1142 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1143 case AT803X_CDT_STATUS_STAT_OPEN: 1144 case AT803X_CDT_STATUS_STAT_SHORT: 1145 return true; 1146 } 1147 return false; 1148 } 1149 1150 static int at803x_cdt_fault_length(u16 status) 1151 { 1152 int dt; 1153 1154 /* According to the datasheet the distance to the fault is 1155 * DELTA_TIME * 0.824 meters. 1156 * 1157 * The author suspect the correct formula is: 1158 * 1159 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1160 * 1161 * where c is the speed of light, VF is the velocity factor of 1162 * the twisted pair cable, 125MHz the counter frequency and 1163 * we need to divide by 2 because the hardware will measure the 1164 * round trip time to the fault and back to the PHY. 1165 * 1166 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1167 * datasheet. 1168 */ 1169 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1170 1171 return (dt * 824) / 10; 1172 } 1173 1174 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1175 { 1176 u16 cdt; 1177 1178 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1179 AT803X_CDT_ENABLE_TEST; 1180 1181 return phy_write(phydev, AT803X_CDT, cdt); 1182 } 1183 1184 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1185 { 1186 int val, ret; 1187 1188 /* One test run takes about 25ms */ 1189 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1190 !(val & AT803X_CDT_ENABLE_TEST), 1191 30000, 100000, true); 1192 1193 return ret < 0 ? ret : 0; 1194 } 1195 1196 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1197 { 1198 static const int ethtool_pair[] = { 1199 ETHTOOL_A_CABLE_PAIR_A, 1200 ETHTOOL_A_CABLE_PAIR_B, 1201 ETHTOOL_A_CABLE_PAIR_C, 1202 ETHTOOL_A_CABLE_PAIR_D, 1203 }; 1204 int ret, val; 1205 1206 ret = at803x_cdt_start(phydev, pair); 1207 if (ret) 1208 return ret; 1209 1210 ret = at803x_cdt_wait_for_completion(phydev); 1211 if (ret) 1212 return ret; 1213 1214 val = phy_read(phydev, AT803X_CDT_STATUS); 1215 if (val < 0) 1216 return val; 1217 1218 if (at803x_cdt_test_failed(val)) 1219 return 0; 1220 1221 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1222 at803x_cable_test_result_trans(val)); 1223 1224 if (at803x_cdt_fault_length_valid(val)) 1225 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1226 at803x_cdt_fault_length(val)); 1227 1228 return 1; 1229 } 1230 1231 static int at803x_cable_test_get_status(struct phy_device *phydev, 1232 bool *finished) 1233 { 1234 unsigned long pair_mask; 1235 int retries = 20; 1236 int pair, ret; 1237 1238 if (phydev->phy_id == ATH9331_PHY_ID || 1239 phydev->phy_id == ATH8032_PHY_ID) 1240 pair_mask = 0x3; 1241 else 1242 pair_mask = 0xf; 1243 1244 *finished = false; 1245 1246 /* According to the datasheet the CDT can be performed when 1247 * there is no link partner or when the link partner is 1248 * auto-negotiating. Starting the test will restart the AN 1249 * automatically. It seems that doing this repeatedly we will 1250 * get a slot where our link partner won't disturb our 1251 * measurement. 1252 */ 1253 while (pair_mask && retries--) { 1254 for_each_set_bit(pair, &pair_mask, 4) { 1255 ret = at803x_cable_test_one_pair(phydev, pair); 1256 if (ret < 0) 1257 return ret; 1258 if (ret) 1259 clear_bit(pair, &pair_mask); 1260 } 1261 if (pair_mask) 1262 msleep(250); 1263 } 1264 1265 *finished = true; 1266 1267 return 0; 1268 } 1269 1270 static int at803x_cable_test_start(struct phy_device *phydev) 1271 { 1272 /* Enable auto-negotiation, but advertise no capabilities, no link 1273 * will be established. A restart of the auto-negotiation is not 1274 * required, because the cable test will automatically break the link. 1275 */ 1276 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1277 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1278 if (phydev->phy_id != ATH9331_PHY_ID && 1279 phydev->phy_id != ATH8032_PHY_ID) 1280 phy_write(phydev, MII_CTRL1000, 0); 1281 1282 /* we do all the (time consuming) work later */ 1283 return 0; 1284 } 1285 1286 static int qca83xx_config_init(struct phy_device *phydev) 1287 { 1288 u8 switch_revision; 1289 1290 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1291 1292 switch (switch_revision) { 1293 case 1: 1294 /* For 100M waveform */ 1295 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea); 1296 /* Turn on Gigabit clock */ 1297 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0); 1298 break; 1299 1300 case 2: 1301 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1302 fallthrough; 1303 case 4: 1304 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1305 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860); 1306 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46); 1307 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1308 break; 1309 } 1310 1311 return 0; 1312 } 1313 1314 static struct phy_driver at803x_driver[] = { 1315 { 1316 /* Qualcomm Atheros AR8035 */ 1317 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1318 .name = "Qualcomm Atheros AR8035", 1319 .flags = PHY_POLL_CABLE_TEST, 1320 .probe = at803x_probe, 1321 .remove = at803x_remove, 1322 .config_aneg = at803x_config_aneg, 1323 .config_init = at803x_config_init, 1324 .soft_reset = genphy_soft_reset, 1325 .set_wol = at803x_set_wol, 1326 .get_wol = at803x_get_wol, 1327 .suspend = at803x_suspend, 1328 .resume = at803x_resume, 1329 /* PHY_GBIT_FEATURES */ 1330 .read_status = at803x_read_status, 1331 .config_intr = at803x_config_intr, 1332 .handle_interrupt = at803x_handle_interrupt, 1333 .get_tunable = at803x_get_tunable, 1334 .set_tunable = at803x_set_tunable, 1335 .cable_test_start = at803x_cable_test_start, 1336 .cable_test_get_status = at803x_cable_test_get_status, 1337 }, { 1338 /* Qualcomm Atheros AR8030 */ 1339 .phy_id = ATH8030_PHY_ID, 1340 .name = "Qualcomm Atheros AR8030", 1341 .phy_id_mask = AT8030_PHY_ID_MASK, 1342 .probe = at803x_probe, 1343 .remove = at803x_remove, 1344 .config_init = at803x_config_init, 1345 .link_change_notify = at803x_link_change_notify, 1346 .set_wol = at803x_set_wol, 1347 .get_wol = at803x_get_wol, 1348 .suspend = at803x_suspend, 1349 .resume = at803x_resume, 1350 /* PHY_BASIC_FEATURES */ 1351 .config_intr = at803x_config_intr, 1352 .handle_interrupt = at803x_handle_interrupt, 1353 }, { 1354 /* Qualcomm Atheros AR8031/AR8033 */ 1355 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1356 .name = "Qualcomm Atheros AR8031/AR8033", 1357 .flags = PHY_POLL_CABLE_TEST, 1358 .probe = at803x_probe, 1359 .remove = at803x_remove, 1360 .config_init = at803x_config_init, 1361 .config_aneg = at803x_config_aneg, 1362 .soft_reset = genphy_soft_reset, 1363 .set_wol = at803x_set_wol, 1364 .get_wol = at803x_get_wol, 1365 .suspend = at803x_suspend, 1366 .resume = at803x_resume, 1367 .read_page = at803x_read_page, 1368 .write_page = at803x_write_page, 1369 .get_features = at803x_get_features, 1370 .read_status = at803x_read_status, 1371 .config_intr = &at803x_config_intr, 1372 .handle_interrupt = at803x_handle_interrupt, 1373 .get_tunable = at803x_get_tunable, 1374 .set_tunable = at803x_set_tunable, 1375 .cable_test_start = at803x_cable_test_start, 1376 .cable_test_get_status = at803x_cable_test_get_status, 1377 }, { 1378 /* Qualcomm Atheros AR8032 */ 1379 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1380 .name = "Qualcomm Atheros AR8032", 1381 .probe = at803x_probe, 1382 .remove = at803x_remove, 1383 .flags = PHY_POLL_CABLE_TEST, 1384 .config_init = at803x_config_init, 1385 .link_change_notify = at803x_link_change_notify, 1386 .set_wol = at803x_set_wol, 1387 .get_wol = at803x_get_wol, 1388 .suspend = at803x_suspend, 1389 .resume = at803x_resume, 1390 /* PHY_BASIC_FEATURES */ 1391 .config_intr = at803x_config_intr, 1392 .handle_interrupt = at803x_handle_interrupt, 1393 .cable_test_start = at803x_cable_test_start, 1394 .cable_test_get_status = at803x_cable_test_get_status, 1395 }, { 1396 /* ATHEROS AR9331 */ 1397 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1398 .name = "Qualcomm Atheros AR9331 built-in PHY", 1399 .suspend = at803x_suspend, 1400 .resume = at803x_resume, 1401 .flags = PHY_POLL_CABLE_TEST, 1402 /* PHY_BASIC_FEATURES */ 1403 .config_intr = &at803x_config_intr, 1404 .handle_interrupt = at803x_handle_interrupt, 1405 .cable_test_start = at803x_cable_test_start, 1406 .cable_test_get_status = at803x_cable_test_get_status, 1407 .read_status = at803x_read_status, 1408 .soft_reset = genphy_soft_reset, 1409 .config_aneg = at803x_config_aneg, 1410 }, { 1411 /* QCA8337 */ 1412 .phy_id = QCA8337_PHY_ID, 1413 .phy_id_mask = QCA8K_PHY_ID_MASK, 1414 .name = "QCA PHY 8337", 1415 /* PHY_GBIT_FEATURES */ 1416 .probe = at803x_probe, 1417 .flags = PHY_IS_INTERNAL, 1418 .config_init = qca83xx_config_init, 1419 .soft_reset = genphy_soft_reset, 1420 .get_sset_count = at803x_get_sset_count, 1421 .get_strings = at803x_get_strings, 1422 .get_stats = at803x_get_stats, 1423 }, }; 1424 1425 module_phy_driver(at803x_driver); 1426 1427 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1428 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1429 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1430 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1431 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1432 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1433 { } 1434 }; 1435 1436 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1437