1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/phylink.h> 23 #include <linux/sfp.h> 24 #include <dt-bindings/net/qca-ar803x.h> 25 26 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 27 #define AT803X_SFC_ASSERT_CRS BIT(11) 28 #define AT803X_SFC_FORCE_LINK BIT(10) 29 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 30 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 31 #define AT803X_SFC_MANUAL_MDIX 0x1 32 #define AT803X_SFC_MANUAL_MDI 0x0 33 #define AT803X_SFC_SQE_TEST BIT(2) 34 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 35 #define AT803X_SFC_DISABLE_JABBER BIT(0) 36 37 #define AT803X_SPECIFIC_STATUS 0x11 38 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 39 #define AT803X_SS_SPEED_1000 2 40 #define AT803X_SS_SPEED_100 1 41 #define AT803X_SS_SPEED_10 0 42 #define AT803X_SS_DUPLEX BIT(13) 43 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 44 #define AT803X_SS_MDIX BIT(6) 45 46 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 47 #define QCA808X_SS_SPEED_2500 4 48 49 #define AT803X_INTR_ENABLE 0x12 50 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 51 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 52 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 53 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 54 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 55 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 56 #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 57 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 58 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 59 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 60 #define AT803X_INTR_ENABLE_WOL BIT(0) 61 62 #define AT803X_INTR_STATUS 0x13 63 64 #define AT803X_SMART_SPEED 0x14 65 #define AT803X_SMART_SPEED_ENABLE BIT(5) 66 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 67 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 68 #define AT803X_CDT 0x16 69 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 70 #define AT803X_CDT_ENABLE_TEST BIT(0) 71 #define AT803X_CDT_STATUS 0x1c 72 #define AT803X_CDT_STATUS_STAT_NORMAL 0 73 #define AT803X_CDT_STATUS_STAT_SHORT 1 74 #define AT803X_CDT_STATUS_STAT_OPEN 2 75 #define AT803X_CDT_STATUS_STAT_FAIL 3 76 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 77 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 78 #define AT803X_LED_CONTROL 0x18 79 80 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 81 #define AT803X_WOL_EN BIT(5) 82 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 83 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 84 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 85 #define AT803X_REG_CHIP_CONFIG 0x1f 86 #define AT803X_BT_BX_REG_SEL 0x8000 87 88 #define AT803X_DEBUG_ADDR 0x1D 89 #define AT803X_DEBUG_DATA 0x1E 90 91 #define AT803X_MODE_CFG_MASK 0x0F 92 #define AT803X_MODE_CFG_BASET_RGMII 0x00 93 #define AT803X_MODE_CFG_BASET_SGMII 0x01 94 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 95 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 96 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 97 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 98 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 99 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 100 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 101 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 102 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 103 104 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 105 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 106 107 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 108 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 109 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 110 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 111 112 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 113 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 114 115 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 116 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 117 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 118 #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) 119 120 #define AT803X_DEBUG_REG_3C 0x3C 121 122 #define AT803X_DEBUG_REG_GREEN 0x3D 123 #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 124 125 #define AT803X_DEBUG_REG_1F 0x1F 126 #define AT803X_DEBUG_PLL_ON BIT(2) 127 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 128 129 #define MDIO_AZ_DEBUG 0x800D 130 131 /* AT803x supports either the XTAL input pad, an internal PLL or the 132 * DSP as clock reference for the clock output pad. The XTAL reference 133 * is only used for 25 MHz output, all other frequencies need the PLL. 134 * The DSP as a clock reference is used in synchronous ethernet 135 * applications. 136 * 137 * By default the PLL is only enabled if there is a link. Otherwise 138 * the PHY will go into low power state and disabled the PLL. You can 139 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 140 * enabled. 141 */ 142 #define AT803X_MMD7_CLK25M 0x8016 143 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 144 #define AT803X_CLK_OUT_25MHZ_XTAL 0 145 #define AT803X_CLK_OUT_25MHZ_DSP 1 146 #define AT803X_CLK_OUT_50MHZ_PLL 2 147 #define AT803X_CLK_OUT_50MHZ_DSP 3 148 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 149 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 150 #define AT803X_CLK_OUT_125MHZ_PLL 6 151 #define AT803X_CLK_OUT_125MHZ_DSP 7 152 153 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 154 * but doesn't support choosing between XTAL/PLL and DSP. 155 */ 156 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 157 158 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 159 #define AT803X_CLK_OUT_STRENGTH_FULL 0 160 #define AT803X_CLK_OUT_STRENGTH_HALF 1 161 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 162 163 #define AT803X_DEFAULT_DOWNSHIFT 5 164 #define AT803X_MIN_DOWNSHIFT 2 165 #define AT803X_MAX_DOWNSHIFT 9 166 167 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 168 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 169 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 170 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 171 172 #define ATH9331_PHY_ID 0x004dd041 173 #define ATH8030_PHY_ID 0x004dd076 174 #define ATH8031_PHY_ID 0x004dd074 175 #define ATH8032_PHY_ID 0x004dd023 176 #define ATH8035_PHY_ID 0x004dd072 177 #define AT8030_PHY_ID_MASK 0xffffffef 178 179 #define QCA8081_PHY_ID 0x004dd101 180 181 #define QCA8327_A_PHY_ID 0x004dd033 182 #define QCA8327_B_PHY_ID 0x004dd034 183 #define QCA8337_PHY_ID 0x004dd036 184 #define QCA9561_PHY_ID 0x004dd042 185 #define QCA8K_PHY_ID_MASK 0xffffffff 186 187 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 188 189 #define AT803X_PAGE_FIBER 0 190 #define AT803X_PAGE_COPPER 1 191 192 /* don't turn off internal PLL */ 193 #define AT803X_KEEP_PLL_ENABLED BIT(0) 194 #define AT803X_DISABLE_SMARTEEE BIT(1) 195 196 /* disable hibernation mode */ 197 #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 198 199 /* ADC threshold */ 200 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 201 #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 202 #define QCA808X_ADC_THRESHOLD_80MV 0 203 #define QCA808X_ADC_THRESHOLD_100MV 0xf0 204 #define QCA808X_ADC_THRESHOLD_200MV 0x0f 205 #define QCA808X_ADC_THRESHOLD_300MV 0xff 206 207 /* CLD control */ 208 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 209 #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 210 #define QCA808X_8023AZ_AFE_EN 0x90 211 212 /* AZ control */ 213 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 214 #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 215 216 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 217 #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 218 219 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 220 #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 221 222 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 223 #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 224 225 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 226 #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 227 228 #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 229 #define QCA808X_TOP_OPTION1_DATA 0x0 230 231 #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 232 #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 233 #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 234 #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 235 #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 236 #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 237 #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 238 #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 239 #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 240 #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 241 #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 242 #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 243 244 /* master/slave seed config */ 245 #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 246 #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 247 #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 248 #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 249 250 /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 251 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 252 */ 253 #define QCA808X_DBG_AN_TEST 0xb 254 #define QCA808X_HIBERNATION_EN BIT(15) 255 256 #define QCA808X_CDT_ENABLE_TEST BIT(15) 257 #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 258 #define QCA808X_CDT_LENGTH_UNIT BIT(10) 259 260 #define QCA808X_MMD3_CDT_STATUS 0x8064 261 #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 262 #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 263 #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 264 #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 265 #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 266 267 #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 268 #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 269 #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 270 #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 271 #define QCA808X_CDT_STATUS_STAT_FAIL 0 272 #define QCA808X_CDT_STATUS_STAT_NORMAL 1 273 #define QCA808X_CDT_STATUS_STAT_OPEN 2 274 #define QCA808X_CDT_STATUS_STAT_SHORT 3 275 276 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 277 MODULE_AUTHOR("Matus Ujhelyi"); 278 MODULE_LICENSE("GPL"); 279 280 enum stat_access_type { 281 PHY, 282 MMD 283 }; 284 285 struct at803x_hw_stat { 286 const char *string; 287 u8 reg; 288 u32 mask; 289 enum stat_access_type access_type; 290 }; 291 292 static struct at803x_hw_stat at803x_hw_stats[] = { 293 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 294 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 295 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 296 }; 297 298 struct at803x_priv { 299 int flags; 300 u16 clk_25m_reg; 301 u16 clk_25m_mask; 302 u8 smarteee_lpi_tw_1g; 303 u8 smarteee_lpi_tw_100m; 304 bool is_fiber; 305 bool is_1000basex; 306 struct regulator_dev *vddio_rdev; 307 struct regulator_dev *vddh_rdev; 308 struct regulator *vddio; 309 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 310 }; 311 312 struct at803x_context { 313 u16 bmcr; 314 u16 advertise; 315 u16 control1000; 316 u16 int_enable; 317 u16 smart_speed; 318 u16 led_control; 319 }; 320 321 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 322 { 323 int ret; 324 325 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 326 if (ret < 0) 327 return ret; 328 329 return phy_write(phydev, AT803X_DEBUG_DATA, data); 330 } 331 332 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 333 { 334 int ret; 335 336 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 337 if (ret < 0) 338 return ret; 339 340 return phy_read(phydev, AT803X_DEBUG_DATA); 341 } 342 343 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 344 u16 clear, u16 set) 345 { 346 u16 val; 347 int ret; 348 349 ret = at803x_debug_reg_read(phydev, reg); 350 if (ret < 0) 351 return ret; 352 353 val = ret & 0xffff; 354 val &= ~clear; 355 val |= set; 356 357 return phy_write(phydev, AT803X_DEBUG_DATA, val); 358 } 359 360 static int at803x_write_page(struct phy_device *phydev, int page) 361 { 362 int mask; 363 int set; 364 365 if (page == AT803X_PAGE_COPPER) { 366 set = AT803X_BT_BX_REG_SEL; 367 mask = 0; 368 } else { 369 set = 0; 370 mask = AT803X_BT_BX_REG_SEL; 371 } 372 373 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 374 } 375 376 static int at803x_read_page(struct phy_device *phydev) 377 { 378 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 379 380 if (ccr < 0) 381 return ccr; 382 383 if (ccr & AT803X_BT_BX_REG_SEL) 384 return AT803X_PAGE_COPPER; 385 386 return AT803X_PAGE_FIBER; 387 } 388 389 static int at803x_enable_rx_delay(struct phy_device *phydev) 390 { 391 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 392 AT803X_DEBUG_RX_CLK_DLY_EN); 393 } 394 395 static int at803x_enable_tx_delay(struct phy_device *phydev) 396 { 397 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 398 AT803X_DEBUG_TX_CLK_DLY_EN); 399 } 400 401 static int at803x_disable_rx_delay(struct phy_device *phydev) 402 { 403 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 404 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 405 } 406 407 static int at803x_disable_tx_delay(struct phy_device *phydev) 408 { 409 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 410 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 411 } 412 413 /* save relevant PHY registers to private copy */ 414 static void at803x_context_save(struct phy_device *phydev, 415 struct at803x_context *context) 416 { 417 context->bmcr = phy_read(phydev, MII_BMCR); 418 context->advertise = phy_read(phydev, MII_ADVERTISE); 419 context->control1000 = phy_read(phydev, MII_CTRL1000); 420 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 421 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 422 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 423 } 424 425 /* restore relevant PHY registers from private copy */ 426 static void at803x_context_restore(struct phy_device *phydev, 427 const struct at803x_context *context) 428 { 429 phy_write(phydev, MII_BMCR, context->bmcr); 430 phy_write(phydev, MII_ADVERTISE, context->advertise); 431 phy_write(phydev, MII_CTRL1000, context->control1000); 432 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 433 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 434 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 435 } 436 437 static int at803x_set_wol(struct phy_device *phydev, 438 struct ethtool_wolinfo *wol) 439 { 440 int ret, irq_enabled; 441 442 if (wol->wolopts & WAKE_MAGIC) { 443 struct net_device *ndev = phydev->attached_dev; 444 const u8 *mac; 445 unsigned int i; 446 static const unsigned int offsets[] = { 447 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 448 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 449 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 450 }; 451 452 if (!ndev) 453 return -ENODEV; 454 455 mac = (const u8 *) ndev->dev_addr; 456 457 if (!is_valid_ether_addr(mac)) 458 return -EINVAL; 459 460 for (i = 0; i < 3; i++) 461 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 462 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 463 464 /* Enable WOL function */ 465 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 466 0, AT803X_WOL_EN); 467 if (ret) 468 return ret; 469 /* Enable WOL interrupt */ 470 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 471 if (ret) 472 return ret; 473 } else { 474 /* Disable WoL function */ 475 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 476 AT803X_WOL_EN, 0); 477 if (ret) 478 return ret; 479 /* Disable WOL interrupt */ 480 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 481 if (ret) 482 return ret; 483 } 484 485 /* Clear WOL status */ 486 ret = phy_read(phydev, AT803X_INTR_STATUS); 487 if (ret < 0) 488 return ret; 489 490 /* Check if there are other interrupts except for WOL triggered when PHY is 491 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 492 * be passed up to the interrupt PIN. 493 */ 494 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 495 if (irq_enabled < 0) 496 return irq_enabled; 497 498 irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 499 if (ret & irq_enabled && !phy_polling_mode(phydev)) 500 phy_trigger_machine(phydev); 501 502 return 0; 503 } 504 505 static void at803x_get_wol(struct phy_device *phydev, 506 struct ethtool_wolinfo *wol) 507 { 508 int value; 509 510 wol->supported = WAKE_MAGIC; 511 wol->wolopts = 0; 512 513 value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 514 if (value < 0) 515 return; 516 517 if (value & AT803X_WOL_EN) 518 wol->wolopts |= WAKE_MAGIC; 519 } 520 521 static int at803x_get_sset_count(struct phy_device *phydev) 522 { 523 return ARRAY_SIZE(at803x_hw_stats); 524 } 525 526 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 527 { 528 int i; 529 530 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 531 strscpy(data + i * ETH_GSTRING_LEN, 532 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 533 } 534 } 535 536 static u64 at803x_get_stat(struct phy_device *phydev, int i) 537 { 538 struct at803x_hw_stat stat = at803x_hw_stats[i]; 539 struct at803x_priv *priv = phydev->priv; 540 int val; 541 u64 ret; 542 543 if (stat.access_type == MMD) 544 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 545 else 546 val = phy_read(phydev, stat.reg); 547 548 if (val < 0) { 549 ret = U64_MAX; 550 } else { 551 val = val & stat.mask; 552 priv->stats[i] += val; 553 ret = priv->stats[i]; 554 } 555 556 return ret; 557 } 558 559 static void at803x_get_stats(struct phy_device *phydev, 560 struct ethtool_stats *stats, u64 *data) 561 { 562 int i; 563 564 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 565 data[i] = at803x_get_stat(phydev, i); 566 } 567 568 static int at803x_suspend(struct phy_device *phydev) 569 { 570 int value; 571 int wol_enabled; 572 573 value = phy_read(phydev, AT803X_INTR_ENABLE); 574 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 575 576 if (wol_enabled) 577 value = BMCR_ISOLATE; 578 else 579 value = BMCR_PDOWN; 580 581 phy_modify(phydev, MII_BMCR, 0, value); 582 583 return 0; 584 } 585 586 static int at803x_resume(struct phy_device *phydev) 587 { 588 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 589 } 590 591 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 592 unsigned int selector) 593 { 594 struct phy_device *phydev = rdev_get_drvdata(rdev); 595 596 if (selector) 597 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 598 0, AT803X_DEBUG_RGMII_1V8); 599 else 600 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 601 AT803X_DEBUG_RGMII_1V8, 0); 602 } 603 604 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 605 { 606 struct phy_device *phydev = rdev_get_drvdata(rdev); 607 int val; 608 609 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 610 if (val < 0) 611 return val; 612 613 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 614 } 615 616 static const struct regulator_ops vddio_regulator_ops = { 617 .list_voltage = regulator_list_voltage_table, 618 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 619 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 620 }; 621 622 static const unsigned int vddio_voltage_table[] = { 623 1500000, 624 1800000, 625 }; 626 627 static const struct regulator_desc vddio_desc = { 628 .name = "vddio", 629 .of_match = of_match_ptr("vddio-regulator"), 630 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 631 .volt_table = vddio_voltage_table, 632 .ops = &vddio_regulator_ops, 633 .type = REGULATOR_VOLTAGE, 634 .owner = THIS_MODULE, 635 }; 636 637 static const struct regulator_ops vddh_regulator_ops = { 638 }; 639 640 static const struct regulator_desc vddh_desc = { 641 .name = "vddh", 642 .of_match = of_match_ptr("vddh-regulator"), 643 .n_voltages = 1, 644 .fixed_uV = 2500000, 645 .ops = &vddh_regulator_ops, 646 .type = REGULATOR_VOLTAGE, 647 .owner = THIS_MODULE, 648 }; 649 650 static int at8031_register_regulators(struct phy_device *phydev) 651 { 652 struct at803x_priv *priv = phydev->priv; 653 struct device *dev = &phydev->mdio.dev; 654 struct regulator_config config = { }; 655 656 config.dev = dev; 657 config.driver_data = phydev; 658 659 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 660 if (IS_ERR(priv->vddio_rdev)) { 661 phydev_err(phydev, "failed to register VDDIO regulator\n"); 662 return PTR_ERR(priv->vddio_rdev); 663 } 664 665 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 666 if (IS_ERR(priv->vddh_rdev)) { 667 phydev_err(phydev, "failed to register VDDH regulator\n"); 668 return PTR_ERR(priv->vddh_rdev); 669 } 670 671 return 0; 672 } 673 674 static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 675 { 676 struct phy_device *phydev = upstream; 677 __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 678 __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 679 phy_interface_t iface; 680 681 linkmode_zero(phy_support); 682 phylink_set(phy_support, 1000baseX_Full); 683 phylink_set(phy_support, 1000baseT_Full); 684 phylink_set(phy_support, Autoneg); 685 phylink_set(phy_support, Pause); 686 phylink_set(phy_support, Asym_Pause); 687 688 linkmode_zero(sfp_support); 689 sfp_parse_support(phydev->sfp_bus, id, sfp_support); 690 /* Some modules support 10G modes as well as others we support. 691 * Mask out non-supported modes so the correct interface is picked. 692 */ 693 linkmode_and(sfp_support, phy_support, sfp_support); 694 695 if (linkmode_empty(sfp_support)) { 696 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 697 return -EINVAL; 698 } 699 700 iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 701 702 /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 703 * interface for use with SFP modules. 704 * However, some copper modules detected as having a preferred SGMII 705 * interface do default to and function in 1000Base-X mode, so just 706 * print a warning and allow such modules, as they may have some chance 707 * of working. 708 */ 709 if (iface == PHY_INTERFACE_MODE_SGMII) 710 dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 711 else if (iface != PHY_INTERFACE_MODE_1000BASEX) 712 return -EINVAL; 713 714 return 0; 715 } 716 717 static const struct sfp_upstream_ops at803x_sfp_ops = { 718 .attach = phy_sfp_attach, 719 .detach = phy_sfp_detach, 720 .module_insert = at803x_sfp_insert, 721 }; 722 723 static int at803x_parse_dt(struct phy_device *phydev) 724 { 725 struct device_node *node = phydev->mdio.dev.of_node; 726 struct at803x_priv *priv = phydev->priv; 727 u32 freq, strength, tw; 728 unsigned int sel; 729 int ret; 730 731 if (!IS_ENABLED(CONFIG_OF_MDIO)) 732 return 0; 733 734 if (of_property_read_bool(node, "qca,disable-smarteee")) 735 priv->flags |= AT803X_DISABLE_SMARTEEE; 736 737 if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 738 priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 739 740 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 741 if (!tw || tw > 255) { 742 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 743 return -EINVAL; 744 } 745 priv->smarteee_lpi_tw_1g = tw; 746 } 747 748 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 749 if (!tw || tw > 255) { 750 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 751 return -EINVAL; 752 } 753 priv->smarteee_lpi_tw_100m = tw; 754 } 755 756 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 757 if (!ret) { 758 switch (freq) { 759 case 25000000: 760 sel = AT803X_CLK_OUT_25MHZ_XTAL; 761 break; 762 case 50000000: 763 sel = AT803X_CLK_OUT_50MHZ_PLL; 764 break; 765 case 62500000: 766 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 767 break; 768 case 125000000: 769 sel = AT803X_CLK_OUT_125MHZ_PLL; 770 break; 771 default: 772 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 773 return -EINVAL; 774 } 775 776 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 777 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 778 779 /* Fixup for the AR8030/AR8035. This chip has another mask and 780 * doesn't support the DSP reference. Eg. the lowest bit of the 781 * mask. The upper two bits select the same frequencies. Mask 782 * the lowest bit here. 783 * 784 * Warning: 785 * There was no datasheet for the AR8030 available so this is 786 * just a guess. But the AR8035 is listed as pin compatible 787 * to the AR8030 so there might be a good chance it works on 788 * the AR8030 too. 789 */ 790 if (phydev->drv->phy_id == ATH8030_PHY_ID || 791 phydev->drv->phy_id == ATH8035_PHY_ID) { 792 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 793 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 794 } 795 } 796 797 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 798 if (!ret) { 799 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 800 switch (strength) { 801 case AR803X_STRENGTH_FULL: 802 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 803 break; 804 case AR803X_STRENGTH_HALF: 805 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 806 break; 807 case AR803X_STRENGTH_QUARTER: 808 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 809 break; 810 default: 811 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 812 return -EINVAL; 813 } 814 } 815 816 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 817 * options. 818 */ 819 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 820 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 821 priv->flags |= AT803X_KEEP_PLL_ENABLED; 822 823 ret = at8031_register_regulators(phydev); 824 if (ret < 0) 825 return ret; 826 827 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 828 "vddio"); 829 if (IS_ERR(priv->vddio)) { 830 phydev_err(phydev, "failed to get VDDIO regulator\n"); 831 return PTR_ERR(priv->vddio); 832 } 833 834 /* Only AR8031/8033 support 1000Base-X for SFP modules */ 835 ret = phy_sfp_probe(phydev, &at803x_sfp_ops); 836 if (ret < 0) 837 return ret; 838 } 839 840 return 0; 841 } 842 843 static int at803x_probe(struct phy_device *phydev) 844 { 845 struct device *dev = &phydev->mdio.dev; 846 struct at803x_priv *priv; 847 int ret; 848 849 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 850 if (!priv) 851 return -ENOMEM; 852 853 phydev->priv = priv; 854 855 ret = at803x_parse_dt(phydev); 856 if (ret) 857 return ret; 858 859 if (priv->vddio) { 860 ret = regulator_enable(priv->vddio); 861 if (ret < 0) 862 return ret; 863 } 864 865 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 866 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 867 int mode_cfg; 868 struct ethtool_wolinfo wol = { 869 .wolopts = 0, 870 }; 871 872 if (ccr < 0) 873 goto err; 874 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 875 876 switch (mode_cfg) { 877 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 878 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 879 priv->is_1000basex = true; 880 fallthrough; 881 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 882 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 883 priv->is_fiber = true; 884 break; 885 } 886 887 /* Disable WOL by default */ 888 ret = at803x_set_wol(phydev, &wol); 889 if (ret < 0) { 890 phydev_err(phydev, "failed to disable WOL on probe: %d\n", ret); 891 goto err; 892 } 893 } 894 895 return 0; 896 897 err: 898 if (priv->vddio) 899 regulator_disable(priv->vddio); 900 901 return ret; 902 } 903 904 static void at803x_remove(struct phy_device *phydev) 905 { 906 struct at803x_priv *priv = phydev->priv; 907 908 if (priv->vddio) 909 regulator_disable(priv->vddio); 910 } 911 912 static int at803x_get_features(struct phy_device *phydev) 913 { 914 struct at803x_priv *priv = phydev->priv; 915 int err; 916 917 err = genphy_read_abilities(phydev); 918 if (err) 919 return err; 920 921 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 922 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); 923 if (err < 0) 924 return err; 925 926 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 927 err & MDIO_PMA_NG_EXTABLE_2_5GBT); 928 } 929 930 if (phydev->drv->phy_id != ATH8031_PHY_ID) 931 return 0; 932 933 /* AR8031/AR8033 have different status registers 934 * for copper and fiber operation. However, the 935 * extended status register is the same for both 936 * operation modes. 937 * 938 * As a result of that, ESTATUS_1000_XFULL is set 939 * to 1 even when operating in copper TP mode. 940 * 941 * Remove this mode from the supported link modes 942 * when not operating in 1000BaseX mode. 943 */ 944 if (!priv->is_1000basex) 945 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 946 phydev->supported); 947 948 return 0; 949 } 950 951 static int at803x_smarteee_config(struct phy_device *phydev) 952 { 953 struct at803x_priv *priv = phydev->priv; 954 u16 mask = 0, val = 0; 955 int ret; 956 957 if (priv->flags & AT803X_DISABLE_SMARTEEE) 958 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 959 AT803X_MMD3_SMARTEEE_CTL3, 960 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 961 962 if (priv->smarteee_lpi_tw_1g) { 963 mask |= 0xff00; 964 val |= priv->smarteee_lpi_tw_1g << 8; 965 } 966 if (priv->smarteee_lpi_tw_100m) { 967 mask |= 0x00ff; 968 val |= priv->smarteee_lpi_tw_100m; 969 } 970 if (!mask) 971 return 0; 972 973 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 974 mask, val); 975 if (ret) 976 return ret; 977 978 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 979 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 980 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 981 } 982 983 static int at803x_clk_out_config(struct phy_device *phydev) 984 { 985 struct at803x_priv *priv = phydev->priv; 986 987 if (!priv->clk_25m_mask) 988 return 0; 989 990 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 991 priv->clk_25m_mask, priv->clk_25m_reg); 992 } 993 994 static int at8031_pll_config(struct phy_device *phydev) 995 { 996 struct at803x_priv *priv = phydev->priv; 997 998 /* The default after hardware reset is PLL OFF. After a soft reset, the 999 * values are retained. 1000 */ 1001 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 1002 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 1003 0, AT803X_DEBUG_PLL_ON); 1004 else 1005 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 1006 AT803X_DEBUG_PLL_ON, 0); 1007 } 1008 1009 static int at803x_hibernation_mode_config(struct phy_device *phydev) 1010 { 1011 struct at803x_priv *priv = phydev->priv; 1012 1013 /* The default after hardware reset is hibernation mode enabled. After 1014 * software reset, the value is retained. 1015 */ 1016 if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) 1017 return 0; 1018 1019 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1020 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 1021 } 1022 1023 static int at803x_config_init(struct phy_device *phydev) 1024 { 1025 struct at803x_priv *priv = phydev->priv; 1026 int ret; 1027 1028 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 1029 /* Some bootloaders leave the fiber page selected. 1030 * Switch to the appropriate page (fiber or copper), as otherwise we 1031 * read the PHY capabilities from the wrong page. 1032 */ 1033 phy_lock_mdio_bus(phydev); 1034 ret = at803x_write_page(phydev, 1035 priv->is_fiber ? AT803X_PAGE_FIBER : 1036 AT803X_PAGE_COPPER); 1037 phy_unlock_mdio_bus(phydev); 1038 if (ret) 1039 return ret; 1040 1041 ret = at8031_pll_config(phydev); 1042 if (ret < 0) 1043 return ret; 1044 } 1045 1046 /* The RX and TX delay default is: 1047 * after HW reset: RX delay enabled and TX delay disabled 1048 * after SW reset: RX delay enabled, while TX delay retains the 1049 * value before reset. 1050 */ 1051 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1052 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1053 ret = at803x_enable_rx_delay(phydev); 1054 else 1055 ret = at803x_disable_rx_delay(phydev); 1056 if (ret < 0) 1057 return ret; 1058 1059 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1060 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1061 ret = at803x_enable_tx_delay(phydev); 1062 else 1063 ret = at803x_disable_tx_delay(phydev); 1064 if (ret < 0) 1065 return ret; 1066 1067 ret = at803x_smarteee_config(phydev); 1068 if (ret < 0) 1069 return ret; 1070 1071 ret = at803x_clk_out_config(phydev); 1072 if (ret < 0) 1073 return ret; 1074 1075 ret = at803x_hibernation_mode_config(phydev); 1076 if (ret < 0) 1077 return ret; 1078 1079 /* Ar803x extended next page bit is enabled by default. Cisco 1080 * multigig switches read this bit and attempt to negotiate 10Gbps 1081 * rates even if the next page bit is disabled. This is incorrect 1082 * behaviour but we still need to accommodate it. XNP is only needed 1083 * for 10Gbps support, so disable XNP. 1084 */ 1085 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 1086 } 1087 1088 static int at803x_ack_interrupt(struct phy_device *phydev) 1089 { 1090 int err; 1091 1092 err = phy_read(phydev, AT803X_INTR_STATUS); 1093 1094 return (err < 0) ? err : 0; 1095 } 1096 1097 static int at803x_config_intr(struct phy_device *phydev) 1098 { 1099 struct at803x_priv *priv = phydev->priv; 1100 int err; 1101 int value; 1102 1103 value = phy_read(phydev, AT803X_INTR_ENABLE); 1104 1105 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1106 /* Clear any pending interrupts */ 1107 err = at803x_ack_interrupt(phydev); 1108 if (err) 1109 return err; 1110 1111 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 1112 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 1113 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 1114 value |= AT803X_INTR_ENABLE_LINK_FAIL; 1115 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 1116 if (priv->is_fiber) { 1117 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 1118 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 1119 } 1120 1121 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 1122 } else { 1123 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 1124 if (err) 1125 return err; 1126 1127 /* Clear any pending interrupts */ 1128 err = at803x_ack_interrupt(phydev); 1129 } 1130 1131 return err; 1132 } 1133 1134 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 1135 { 1136 int irq_status, int_enabled; 1137 1138 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 1139 if (irq_status < 0) { 1140 phy_error(phydev); 1141 return IRQ_NONE; 1142 } 1143 1144 /* Read the current enabled interrupts */ 1145 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 1146 if (int_enabled < 0) { 1147 phy_error(phydev); 1148 return IRQ_NONE; 1149 } 1150 1151 /* See if this was one of our enabled interrupts */ 1152 if (!(irq_status & int_enabled)) 1153 return IRQ_NONE; 1154 1155 phy_trigger_machine(phydev); 1156 1157 return IRQ_HANDLED; 1158 } 1159 1160 static void at803x_link_change_notify(struct phy_device *phydev) 1161 { 1162 /* 1163 * Conduct a hardware reset for AT8030 every time a link loss is 1164 * signalled. This is necessary to circumvent a hardware bug that 1165 * occurs when the cable is unplugged while TX packets are pending 1166 * in the FIFO. In such cases, the FIFO enters an error mode it 1167 * cannot recover from by software. 1168 */ 1169 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 1170 struct at803x_context context; 1171 1172 at803x_context_save(phydev, &context); 1173 1174 phy_device_reset(phydev, 1); 1175 msleep(1); 1176 phy_device_reset(phydev, 0); 1177 msleep(1); 1178 1179 at803x_context_restore(phydev, &context); 1180 1181 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 1182 } 1183 } 1184 1185 static int at803x_read_specific_status(struct phy_device *phydev) 1186 { 1187 int ss; 1188 1189 /* Read the AT8035 PHY-Specific Status register, which indicates the 1190 * speed and duplex that the PHY is actually using, irrespective of 1191 * whether we are in autoneg mode or not. 1192 */ 1193 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 1194 if (ss < 0) 1195 return ss; 1196 1197 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 1198 int sfc, speed; 1199 1200 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 1201 if (sfc < 0) 1202 return sfc; 1203 1204 /* qca8081 takes the different bits for speed value from at803x */ 1205 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1206 speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 1207 else 1208 speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 1209 1210 switch (speed) { 1211 case AT803X_SS_SPEED_10: 1212 phydev->speed = SPEED_10; 1213 break; 1214 case AT803X_SS_SPEED_100: 1215 phydev->speed = SPEED_100; 1216 break; 1217 case AT803X_SS_SPEED_1000: 1218 phydev->speed = SPEED_1000; 1219 break; 1220 case QCA808X_SS_SPEED_2500: 1221 phydev->speed = SPEED_2500; 1222 break; 1223 } 1224 if (ss & AT803X_SS_DUPLEX) 1225 phydev->duplex = DUPLEX_FULL; 1226 else 1227 phydev->duplex = DUPLEX_HALF; 1228 1229 if (ss & AT803X_SS_MDIX) 1230 phydev->mdix = ETH_TP_MDI_X; 1231 else 1232 phydev->mdix = ETH_TP_MDI; 1233 1234 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 1235 case AT803X_SFC_MANUAL_MDI: 1236 phydev->mdix_ctrl = ETH_TP_MDI; 1237 break; 1238 case AT803X_SFC_MANUAL_MDIX: 1239 phydev->mdix_ctrl = ETH_TP_MDI_X; 1240 break; 1241 case AT803X_SFC_AUTOMATIC_CROSSOVER: 1242 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1243 break; 1244 } 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int at803x_read_status(struct phy_device *phydev) 1251 { 1252 struct at803x_priv *priv = phydev->priv; 1253 int err, old_link = phydev->link; 1254 1255 if (priv->is_1000basex) 1256 return genphy_c37_read_status(phydev); 1257 1258 /* Update the link, but return if there was an error */ 1259 err = genphy_update_link(phydev); 1260 if (err) 1261 return err; 1262 1263 /* why bother the PHY if nothing can have changed */ 1264 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 1265 return 0; 1266 1267 phydev->speed = SPEED_UNKNOWN; 1268 phydev->duplex = DUPLEX_UNKNOWN; 1269 phydev->pause = 0; 1270 phydev->asym_pause = 0; 1271 1272 err = genphy_read_lpa(phydev); 1273 if (err < 0) 1274 return err; 1275 1276 err = at803x_read_specific_status(phydev); 1277 if (err < 0) 1278 return err; 1279 1280 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1281 phy_resolve_aneg_pause(phydev); 1282 1283 return 0; 1284 } 1285 1286 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 1287 { 1288 u16 val; 1289 1290 switch (ctrl) { 1291 case ETH_TP_MDI: 1292 val = AT803X_SFC_MANUAL_MDI; 1293 break; 1294 case ETH_TP_MDI_X: 1295 val = AT803X_SFC_MANUAL_MDIX; 1296 break; 1297 case ETH_TP_MDI_AUTO: 1298 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 1299 break; 1300 default: 1301 return 0; 1302 } 1303 1304 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 1305 AT803X_SFC_MDI_CROSSOVER_MODE_M, 1306 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1307 } 1308 1309 static int at803x_config_aneg(struct phy_device *phydev) 1310 { 1311 struct at803x_priv *priv = phydev->priv; 1312 int ret; 1313 1314 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1315 if (ret < 0) 1316 return ret; 1317 1318 /* Changes of the midx bits are disruptive to the normal operation; 1319 * therefore any changes to these registers must be followed by a 1320 * software reset to take effect. 1321 */ 1322 if (ret == 1) { 1323 ret = genphy_soft_reset(phydev); 1324 if (ret < 0) 1325 return ret; 1326 } 1327 1328 if (priv->is_1000basex) 1329 return genphy_c37_config_aneg(phydev); 1330 1331 /* Do not restart auto-negotiation by setting ret to 0 defautly, 1332 * when calling __genphy_config_aneg later. 1333 */ 1334 ret = 0; 1335 1336 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1337 int phy_ctrl = 0; 1338 1339 /* The reg MII_BMCR also needs to be configured for force mode, the 1340 * genphy_config_aneg is also needed. 1341 */ 1342 if (phydev->autoneg == AUTONEG_DISABLE) 1343 genphy_c45_pma_setup_forced(phydev); 1344 1345 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1346 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1347 1348 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1349 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1350 if (ret < 0) 1351 return ret; 1352 } 1353 1354 return __genphy_config_aneg(phydev, ret); 1355 } 1356 1357 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1358 { 1359 int val; 1360 1361 val = phy_read(phydev, AT803X_SMART_SPEED); 1362 if (val < 0) 1363 return val; 1364 1365 if (val & AT803X_SMART_SPEED_ENABLE) 1366 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1367 else 1368 *d = DOWNSHIFT_DEV_DISABLE; 1369 1370 return 0; 1371 } 1372 1373 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1374 { 1375 u16 mask, set; 1376 int ret; 1377 1378 switch (cnt) { 1379 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1380 cnt = AT803X_DEFAULT_DOWNSHIFT; 1381 fallthrough; 1382 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1383 set = AT803X_SMART_SPEED_ENABLE | 1384 AT803X_SMART_SPEED_BYPASS_TIMER | 1385 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1386 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1387 break; 1388 case DOWNSHIFT_DEV_DISABLE: 1389 set = 0; 1390 mask = AT803X_SMART_SPEED_ENABLE | 1391 AT803X_SMART_SPEED_BYPASS_TIMER; 1392 break; 1393 default: 1394 return -EINVAL; 1395 } 1396 1397 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1398 1399 /* After changing the smart speed settings, we need to perform a 1400 * software reset, use phy_init_hw() to make sure we set the 1401 * reapply any values which might got lost during software reset. 1402 */ 1403 if (ret == 1) 1404 ret = phy_init_hw(phydev); 1405 1406 return ret; 1407 } 1408 1409 static int at803x_get_tunable(struct phy_device *phydev, 1410 struct ethtool_tunable *tuna, void *data) 1411 { 1412 switch (tuna->id) { 1413 case ETHTOOL_PHY_DOWNSHIFT: 1414 return at803x_get_downshift(phydev, data); 1415 default: 1416 return -EOPNOTSUPP; 1417 } 1418 } 1419 1420 static int at803x_set_tunable(struct phy_device *phydev, 1421 struct ethtool_tunable *tuna, const void *data) 1422 { 1423 switch (tuna->id) { 1424 case ETHTOOL_PHY_DOWNSHIFT: 1425 return at803x_set_downshift(phydev, *(const u8 *)data); 1426 default: 1427 return -EOPNOTSUPP; 1428 } 1429 } 1430 1431 static int at803x_cable_test_result_trans(u16 status) 1432 { 1433 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1434 case AT803X_CDT_STATUS_STAT_NORMAL: 1435 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1436 case AT803X_CDT_STATUS_STAT_SHORT: 1437 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1438 case AT803X_CDT_STATUS_STAT_OPEN: 1439 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1440 case AT803X_CDT_STATUS_STAT_FAIL: 1441 default: 1442 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1443 } 1444 } 1445 1446 static bool at803x_cdt_test_failed(u16 status) 1447 { 1448 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1449 AT803X_CDT_STATUS_STAT_FAIL; 1450 } 1451 1452 static bool at803x_cdt_fault_length_valid(u16 status) 1453 { 1454 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1455 case AT803X_CDT_STATUS_STAT_OPEN: 1456 case AT803X_CDT_STATUS_STAT_SHORT: 1457 return true; 1458 } 1459 return false; 1460 } 1461 1462 static int at803x_cdt_fault_length(u16 status) 1463 { 1464 int dt; 1465 1466 /* According to the datasheet the distance to the fault is 1467 * DELTA_TIME * 0.824 meters. 1468 * 1469 * The author suspect the correct formula is: 1470 * 1471 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1472 * 1473 * where c is the speed of light, VF is the velocity factor of 1474 * the twisted pair cable, 125MHz the counter frequency and 1475 * we need to divide by 2 because the hardware will measure the 1476 * round trip time to the fault and back to the PHY. 1477 * 1478 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1479 * datasheet. 1480 */ 1481 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1482 1483 return (dt * 824) / 10; 1484 } 1485 1486 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1487 { 1488 u16 cdt; 1489 1490 /* qca8081 takes the different bit 15 to enable CDT test */ 1491 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1492 cdt = QCA808X_CDT_ENABLE_TEST | 1493 QCA808X_CDT_LENGTH_UNIT | 1494 QCA808X_CDT_INTER_CHECK_DIS; 1495 else 1496 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1497 AT803X_CDT_ENABLE_TEST; 1498 1499 return phy_write(phydev, AT803X_CDT, cdt); 1500 } 1501 1502 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1503 { 1504 int val, ret; 1505 u16 cdt_en; 1506 1507 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1508 cdt_en = QCA808X_CDT_ENABLE_TEST; 1509 else 1510 cdt_en = AT803X_CDT_ENABLE_TEST; 1511 1512 /* One test run takes about 25ms */ 1513 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1514 !(val & cdt_en), 1515 30000, 100000, true); 1516 1517 return ret < 0 ? ret : 0; 1518 } 1519 1520 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1521 { 1522 static const int ethtool_pair[] = { 1523 ETHTOOL_A_CABLE_PAIR_A, 1524 ETHTOOL_A_CABLE_PAIR_B, 1525 ETHTOOL_A_CABLE_PAIR_C, 1526 ETHTOOL_A_CABLE_PAIR_D, 1527 }; 1528 int ret, val; 1529 1530 ret = at803x_cdt_start(phydev, pair); 1531 if (ret) 1532 return ret; 1533 1534 ret = at803x_cdt_wait_for_completion(phydev); 1535 if (ret) 1536 return ret; 1537 1538 val = phy_read(phydev, AT803X_CDT_STATUS); 1539 if (val < 0) 1540 return val; 1541 1542 if (at803x_cdt_test_failed(val)) 1543 return 0; 1544 1545 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1546 at803x_cable_test_result_trans(val)); 1547 1548 if (at803x_cdt_fault_length_valid(val)) 1549 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1550 at803x_cdt_fault_length(val)); 1551 1552 return 1; 1553 } 1554 1555 static int at803x_cable_test_get_status(struct phy_device *phydev, 1556 bool *finished) 1557 { 1558 unsigned long pair_mask; 1559 int retries = 20; 1560 int pair, ret; 1561 1562 if (phydev->phy_id == ATH9331_PHY_ID || 1563 phydev->phy_id == ATH8032_PHY_ID || 1564 phydev->phy_id == QCA9561_PHY_ID) 1565 pair_mask = 0x3; 1566 else 1567 pair_mask = 0xf; 1568 1569 *finished = false; 1570 1571 /* According to the datasheet the CDT can be performed when 1572 * there is no link partner or when the link partner is 1573 * auto-negotiating. Starting the test will restart the AN 1574 * automatically. It seems that doing this repeatedly we will 1575 * get a slot where our link partner won't disturb our 1576 * measurement. 1577 */ 1578 while (pair_mask && retries--) { 1579 for_each_set_bit(pair, &pair_mask, 4) { 1580 ret = at803x_cable_test_one_pair(phydev, pair); 1581 if (ret < 0) 1582 return ret; 1583 if (ret) 1584 clear_bit(pair, &pair_mask); 1585 } 1586 if (pair_mask) 1587 msleep(250); 1588 } 1589 1590 *finished = true; 1591 1592 return 0; 1593 } 1594 1595 static int at803x_cable_test_start(struct phy_device *phydev) 1596 { 1597 /* Enable auto-negotiation, but advertise no capabilities, no link 1598 * will be established. A restart of the auto-negotiation is not 1599 * required, because the cable test will automatically break the link. 1600 */ 1601 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1602 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1603 if (phydev->phy_id != ATH9331_PHY_ID && 1604 phydev->phy_id != ATH8032_PHY_ID && 1605 phydev->phy_id != QCA9561_PHY_ID) 1606 phy_write(phydev, MII_CTRL1000, 0); 1607 1608 /* we do all the (time consuming) work later */ 1609 return 0; 1610 } 1611 1612 static int qca83xx_config_init(struct phy_device *phydev) 1613 { 1614 u8 switch_revision; 1615 1616 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1617 1618 switch (switch_revision) { 1619 case 1: 1620 /* For 100M waveform */ 1621 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1622 /* Turn on Gigabit clock */ 1623 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1624 break; 1625 1626 case 2: 1627 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1628 fallthrough; 1629 case 4: 1630 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1631 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 1632 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1633 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1634 break; 1635 } 1636 1637 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 1638 * Disable on init and enable only with 100m speed following 1639 * qca original source code. 1640 */ 1641 if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 1642 phydev->drv->phy_id == QCA8327_B_PHY_ID) 1643 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1644 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1645 1646 /* Following original QCA sourcecode set port to prefer master */ 1647 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 1648 1649 return 0; 1650 } 1651 1652 static void qca83xx_link_change_notify(struct phy_device *phydev) 1653 { 1654 /* QCA8337 doesn't require DAC Amplitude adjustement */ 1655 if (phydev->drv->phy_id == QCA8337_PHY_ID) 1656 return; 1657 1658 /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 1659 if (phydev->state == PHY_RUNNING) { 1660 if (phydev->speed == SPEED_100) 1661 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1662 QCA8327_DEBUG_MANU_CTRL_EN, 1663 QCA8327_DEBUG_MANU_CTRL_EN); 1664 } else { 1665 /* Reset DAC Amplitude adjustment */ 1666 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1667 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1668 } 1669 } 1670 1671 static int qca83xx_resume(struct phy_device *phydev) 1672 { 1673 int ret, val; 1674 1675 /* Skip reset if not suspended */ 1676 if (!phydev->suspended) 1677 return 0; 1678 1679 /* Reinit the port, reset values set by suspend */ 1680 qca83xx_config_init(phydev); 1681 1682 /* Reset the port on port resume */ 1683 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1684 1685 /* On resume from suspend the switch execute a reset and 1686 * restart auto-negotiation. Wait for reset to complete. 1687 */ 1688 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1689 50000, 600000, true); 1690 if (ret) 1691 return ret; 1692 1693 msleep(1); 1694 1695 return 0; 1696 } 1697 1698 static int qca83xx_suspend(struct phy_device *phydev) 1699 { 1700 u16 mask = 0; 1701 1702 /* Only QCA8337 support actual suspend. 1703 * QCA8327 cause port unreliability when phy suspend 1704 * is set. 1705 */ 1706 if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1707 genphy_suspend(phydev); 1708 } else { 1709 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1710 phy_modify(phydev, MII_BMCR, mask, 0); 1711 } 1712 1713 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1714 AT803X_DEBUG_GATE_CLK_IN1000, 0); 1715 1716 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1717 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1718 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1719 1720 return 0; 1721 } 1722 1723 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 1724 { 1725 int ret; 1726 1727 /* Enable fast retrain */ 1728 ret = genphy_c45_fast_retrain(phydev, true); 1729 if (ret) 1730 return ret; 1731 1732 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 1733 QCA808X_TOP_OPTION1_DATA); 1734 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 1735 QCA808X_MSE_THRESHOLD_20DB_VALUE); 1736 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 1737 QCA808X_MSE_THRESHOLD_17DB_VALUE); 1738 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 1739 QCA808X_MSE_THRESHOLD_27DB_VALUE); 1740 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 1741 QCA808X_MSE_THRESHOLD_28DB_VALUE); 1742 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 1743 QCA808X_MMD3_DEBUG_1_VALUE); 1744 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 1745 QCA808X_MMD3_DEBUG_4_VALUE); 1746 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 1747 QCA808X_MMD3_DEBUG_5_VALUE); 1748 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 1749 QCA808X_MMD3_DEBUG_3_VALUE); 1750 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 1751 QCA808X_MMD3_DEBUG_6_VALUE); 1752 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 1753 QCA808X_MMD3_DEBUG_2_VALUE); 1754 1755 return 0; 1756 } 1757 1758 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) 1759 { 1760 u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE); 1761 1762 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1763 QCA808X_MASTER_SLAVE_SEED_CFG, 1764 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); 1765 } 1766 1767 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 1768 { 1769 u16 seed_enable = 0; 1770 1771 if (enable) 1772 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; 1773 1774 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1775 QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); 1776 } 1777 1778 static int qca808x_config_init(struct phy_device *phydev) 1779 { 1780 int ret; 1781 1782 /* Active adc&vga on 802.3az for the link 1000M and 100M */ 1783 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 1784 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 1785 if (ret) 1786 return ret; 1787 1788 /* Adjust the threshold on 802.3az for the link 1000M */ 1789 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 1790 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 1791 if (ret) 1792 return ret; 1793 1794 /* Config the fast retrain for the link 2500M */ 1795 ret = qca808x_phy_fast_retrain_config(phydev); 1796 if (ret) 1797 return ret; 1798 1799 /* Configure lower ramdom seed to make phy linked as slave mode */ 1800 ret = qca808x_phy_ms_random_seed_set(phydev); 1801 if (ret) 1802 return ret; 1803 1804 /* Enable seed */ 1805 ret = qca808x_phy_ms_seed_enable(phydev, true); 1806 if (ret) 1807 return ret; 1808 1809 /* Configure adc threshold as 100mv for the link 10M */ 1810 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 1811 QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 1812 } 1813 1814 static int qca808x_read_status(struct phy_device *phydev) 1815 { 1816 int ret; 1817 1818 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1819 if (ret < 0) 1820 return ret; 1821 1822 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 1823 ret & MDIO_AN_10GBT_STAT_LP2_5G); 1824 1825 ret = genphy_read_status(phydev); 1826 if (ret) 1827 return ret; 1828 1829 ret = at803x_read_specific_status(phydev); 1830 if (ret < 0) 1831 return ret; 1832 1833 if (phydev->link) { 1834 if (phydev->speed == SPEED_2500) 1835 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1836 else 1837 phydev->interface = PHY_INTERFACE_MODE_SGMII; 1838 } else { 1839 /* generate seed as a lower random value to make PHY linked as SLAVE easily, 1840 * except for master/slave configuration fault detected. 1841 * the reason for not putting this code into the function link_change_notify is 1842 * the corner case where the link partner is also the qca8081 PHY and the seed 1843 * value is configured as the same value, the link can't be up and no link change 1844 * occurs. 1845 */ 1846 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { 1847 qca808x_phy_ms_seed_enable(phydev, false); 1848 } else { 1849 qca808x_phy_ms_random_seed_set(phydev); 1850 qca808x_phy_ms_seed_enable(phydev, true); 1851 } 1852 } 1853 1854 return 0; 1855 } 1856 1857 static int qca808x_soft_reset(struct phy_device *phydev) 1858 { 1859 int ret; 1860 1861 ret = genphy_soft_reset(phydev); 1862 if (ret < 0) 1863 return ret; 1864 1865 return qca808x_phy_ms_seed_enable(phydev, true); 1866 } 1867 1868 static bool qca808x_cdt_fault_length_valid(int cdt_code) 1869 { 1870 switch (cdt_code) { 1871 case QCA808X_CDT_STATUS_STAT_SHORT: 1872 case QCA808X_CDT_STATUS_STAT_OPEN: 1873 return true; 1874 default: 1875 return false; 1876 } 1877 } 1878 1879 static int qca808x_cable_test_result_trans(int cdt_code) 1880 { 1881 switch (cdt_code) { 1882 case QCA808X_CDT_STATUS_STAT_NORMAL: 1883 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1884 case QCA808X_CDT_STATUS_STAT_SHORT: 1885 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1886 case QCA808X_CDT_STATUS_STAT_OPEN: 1887 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1888 case QCA808X_CDT_STATUS_STAT_FAIL: 1889 default: 1890 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1891 } 1892 } 1893 1894 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 1895 { 1896 int val; 1897 u32 cdt_length_reg = 0; 1898 1899 switch (pair) { 1900 case ETHTOOL_A_CABLE_PAIR_A: 1901 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 1902 break; 1903 case ETHTOOL_A_CABLE_PAIR_B: 1904 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 1905 break; 1906 case ETHTOOL_A_CABLE_PAIR_C: 1907 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 1908 break; 1909 case ETHTOOL_A_CABLE_PAIR_D: 1910 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 1911 break; 1912 default: 1913 return -EINVAL; 1914 } 1915 1916 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 1917 if (val < 0) 1918 return val; 1919 1920 return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 1921 } 1922 1923 static int qca808x_cable_test_start(struct phy_device *phydev) 1924 { 1925 int ret; 1926 1927 /* perform CDT with the following configs: 1928 * 1. disable hibernation. 1929 * 2. force PHY working in MDI mode. 1930 * 3. for PHY working in 1000BaseT. 1931 * 4. configure the threshold. 1932 */ 1933 1934 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 1935 if (ret < 0) 1936 return ret; 1937 1938 ret = at803x_config_mdix(phydev, ETH_TP_MDI); 1939 if (ret < 0) 1940 return ret; 1941 1942 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 1943 phydev->duplex = DUPLEX_FULL; 1944 phydev->speed = SPEED_1000; 1945 ret = genphy_c45_pma_setup_forced(phydev); 1946 if (ret < 0) 1947 return ret; 1948 1949 ret = genphy_setup_forced(phydev); 1950 if (ret < 0) 1951 return ret; 1952 1953 /* configure the thresholds for open, short, pair ok test */ 1954 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 1955 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 1956 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 1957 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 1958 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 1959 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 1960 1961 return 0; 1962 } 1963 1964 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 1965 { 1966 int ret, val; 1967 int pair_a, pair_b, pair_c, pair_d; 1968 1969 *finished = false; 1970 1971 ret = at803x_cdt_start(phydev, 0); 1972 if (ret) 1973 return ret; 1974 1975 ret = at803x_cdt_wait_for_completion(phydev); 1976 if (ret) 1977 return ret; 1978 1979 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 1980 if (val < 0) 1981 return val; 1982 1983 pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 1984 pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 1985 pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 1986 pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 1987 1988 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1989 qca808x_cable_test_result_trans(pair_a)); 1990 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 1991 qca808x_cable_test_result_trans(pair_b)); 1992 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 1993 qca808x_cable_test_result_trans(pair_c)); 1994 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 1995 qca808x_cable_test_result_trans(pair_d)); 1996 1997 if (qca808x_cdt_fault_length_valid(pair_a)) 1998 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 1999 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 2000 if (qca808x_cdt_fault_length_valid(pair_b)) 2001 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 2002 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 2003 if (qca808x_cdt_fault_length_valid(pair_c)) 2004 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 2005 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 2006 if (qca808x_cdt_fault_length_valid(pair_d)) 2007 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 2008 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 2009 2010 *finished = true; 2011 2012 return 0; 2013 } 2014 2015 static struct phy_driver at803x_driver[] = { 2016 { 2017 /* Qualcomm Atheros AR8035 */ 2018 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 2019 .name = "Qualcomm Atheros AR8035", 2020 .flags = PHY_POLL_CABLE_TEST, 2021 .probe = at803x_probe, 2022 .remove = at803x_remove, 2023 .config_aneg = at803x_config_aneg, 2024 .config_init = at803x_config_init, 2025 .soft_reset = genphy_soft_reset, 2026 .set_wol = at803x_set_wol, 2027 .get_wol = at803x_get_wol, 2028 .suspend = at803x_suspend, 2029 .resume = at803x_resume, 2030 /* PHY_GBIT_FEATURES */ 2031 .read_status = at803x_read_status, 2032 .config_intr = at803x_config_intr, 2033 .handle_interrupt = at803x_handle_interrupt, 2034 .get_tunable = at803x_get_tunable, 2035 .set_tunable = at803x_set_tunable, 2036 .cable_test_start = at803x_cable_test_start, 2037 .cable_test_get_status = at803x_cable_test_get_status, 2038 }, { 2039 /* Qualcomm Atheros AR8030 */ 2040 .phy_id = ATH8030_PHY_ID, 2041 .name = "Qualcomm Atheros AR8030", 2042 .phy_id_mask = AT8030_PHY_ID_MASK, 2043 .probe = at803x_probe, 2044 .remove = at803x_remove, 2045 .config_init = at803x_config_init, 2046 .link_change_notify = at803x_link_change_notify, 2047 .set_wol = at803x_set_wol, 2048 .get_wol = at803x_get_wol, 2049 .suspend = at803x_suspend, 2050 .resume = at803x_resume, 2051 /* PHY_BASIC_FEATURES */ 2052 .config_intr = at803x_config_intr, 2053 .handle_interrupt = at803x_handle_interrupt, 2054 }, { 2055 /* Qualcomm Atheros AR8031/AR8033 */ 2056 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 2057 .name = "Qualcomm Atheros AR8031/AR8033", 2058 .flags = PHY_POLL_CABLE_TEST, 2059 .probe = at803x_probe, 2060 .remove = at803x_remove, 2061 .config_init = at803x_config_init, 2062 .config_aneg = at803x_config_aneg, 2063 .soft_reset = genphy_soft_reset, 2064 .set_wol = at803x_set_wol, 2065 .get_wol = at803x_get_wol, 2066 .suspend = at803x_suspend, 2067 .resume = at803x_resume, 2068 .read_page = at803x_read_page, 2069 .write_page = at803x_write_page, 2070 .get_features = at803x_get_features, 2071 .read_status = at803x_read_status, 2072 .config_intr = &at803x_config_intr, 2073 .handle_interrupt = at803x_handle_interrupt, 2074 .get_tunable = at803x_get_tunable, 2075 .set_tunable = at803x_set_tunable, 2076 .cable_test_start = at803x_cable_test_start, 2077 .cable_test_get_status = at803x_cable_test_get_status, 2078 }, { 2079 /* Qualcomm Atheros AR8032 */ 2080 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 2081 .name = "Qualcomm Atheros AR8032", 2082 .probe = at803x_probe, 2083 .remove = at803x_remove, 2084 .flags = PHY_POLL_CABLE_TEST, 2085 .config_init = at803x_config_init, 2086 .link_change_notify = at803x_link_change_notify, 2087 .set_wol = at803x_set_wol, 2088 .get_wol = at803x_get_wol, 2089 .suspend = at803x_suspend, 2090 .resume = at803x_resume, 2091 /* PHY_BASIC_FEATURES */ 2092 .config_intr = at803x_config_intr, 2093 .handle_interrupt = at803x_handle_interrupt, 2094 .cable_test_start = at803x_cable_test_start, 2095 .cable_test_get_status = at803x_cable_test_get_status, 2096 }, { 2097 /* ATHEROS AR9331 */ 2098 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 2099 .name = "Qualcomm Atheros AR9331 built-in PHY", 2100 .probe = at803x_probe, 2101 .remove = at803x_remove, 2102 .suspend = at803x_suspend, 2103 .resume = at803x_resume, 2104 .flags = PHY_POLL_CABLE_TEST, 2105 /* PHY_BASIC_FEATURES */ 2106 .config_intr = &at803x_config_intr, 2107 .handle_interrupt = at803x_handle_interrupt, 2108 .cable_test_start = at803x_cable_test_start, 2109 .cable_test_get_status = at803x_cable_test_get_status, 2110 .read_status = at803x_read_status, 2111 .soft_reset = genphy_soft_reset, 2112 .config_aneg = at803x_config_aneg, 2113 }, { 2114 /* Qualcomm Atheros QCA9561 */ 2115 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 2116 .name = "Qualcomm Atheros QCA9561 built-in PHY", 2117 .probe = at803x_probe, 2118 .remove = at803x_remove, 2119 .suspend = at803x_suspend, 2120 .resume = at803x_resume, 2121 .flags = PHY_POLL_CABLE_TEST, 2122 /* PHY_BASIC_FEATURES */ 2123 .config_intr = &at803x_config_intr, 2124 .handle_interrupt = at803x_handle_interrupt, 2125 .cable_test_start = at803x_cable_test_start, 2126 .cable_test_get_status = at803x_cable_test_get_status, 2127 .read_status = at803x_read_status, 2128 .soft_reset = genphy_soft_reset, 2129 .config_aneg = at803x_config_aneg, 2130 }, { 2131 /* QCA8337 */ 2132 .phy_id = QCA8337_PHY_ID, 2133 .phy_id_mask = QCA8K_PHY_ID_MASK, 2134 .name = "Qualcomm Atheros 8337 internal PHY", 2135 /* PHY_GBIT_FEATURES */ 2136 .link_change_notify = qca83xx_link_change_notify, 2137 .probe = at803x_probe, 2138 .flags = PHY_IS_INTERNAL, 2139 .config_init = qca83xx_config_init, 2140 .soft_reset = genphy_soft_reset, 2141 .get_sset_count = at803x_get_sset_count, 2142 .get_strings = at803x_get_strings, 2143 .get_stats = at803x_get_stats, 2144 .suspend = qca83xx_suspend, 2145 .resume = qca83xx_resume, 2146 }, { 2147 /* QCA8327-A from switch QCA8327-AL1A */ 2148 .phy_id = QCA8327_A_PHY_ID, 2149 .phy_id_mask = QCA8K_PHY_ID_MASK, 2150 .name = "Qualcomm Atheros 8327-A internal PHY", 2151 /* PHY_GBIT_FEATURES */ 2152 .link_change_notify = qca83xx_link_change_notify, 2153 .probe = at803x_probe, 2154 .flags = PHY_IS_INTERNAL, 2155 .config_init = qca83xx_config_init, 2156 .soft_reset = genphy_soft_reset, 2157 .get_sset_count = at803x_get_sset_count, 2158 .get_strings = at803x_get_strings, 2159 .get_stats = at803x_get_stats, 2160 .suspend = qca83xx_suspend, 2161 .resume = qca83xx_resume, 2162 }, { 2163 /* QCA8327-B from switch QCA8327-BL1A */ 2164 .phy_id = QCA8327_B_PHY_ID, 2165 .phy_id_mask = QCA8K_PHY_ID_MASK, 2166 .name = "Qualcomm Atheros 8327-B internal PHY", 2167 /* PHY_GBIT_FEATURES */ 2168 .link_change_notify = qca83xx_link_change_notify, 2169 .probe = at803x_probe, 2170 .flags = PHY_IS_INTERNAL, 2171 .config_init = qca83xx_config_init, 2172 .soft_reset = genphy_soft_reset, 2173 .get_sset_count = at803x_get_sset_count, 2174 .get_strings = at803x_get_strings, 2175 .get_stats = at803x_get_stats, 2176 .suspend = qca83xx_suspend, 2177 .resume = qca83xx_resume, 2178 }, { 2179 /* Qualcomm QCA8081 */ 2180 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2181 .name = "Qualcomm QCA8081", 2182 .flags = PHY_POLL_CABLE_TEST, 2183 .probe = at803x_probe, 2184 .remove = at803x_remove, 2185 .config_intr = at803x_config_intr, 2186 .handle_interrupt = at803x_handle_interrupt, 2187 .get_tunable = at803x_get_tunable, 2188 .set_tunable = at803x_set_tunable, 2189 .set_wol = at803x_set_wol, 2190 .get_wol = at803x_get_wol, 2191 .get_features = at803x_get_features, 2192 .config_aneg = at803x_config_aneg, 2193 .suspend = genphy_suspend, 2194 .resume = genphy_resume, 2195 .read_status = qca808x_read_status, 2196 .config_init = qca808x_config_init, 2197 .soft_reset = qca808x_soft_reset, 2198 .cable_test_start = qca808x_cable_test_start, 2199 .cable_test_get_status = qca808x_cable_test_get_status, 2200 }, }; 2201 2202 module_phy_driver(at803x_driver); 2203 2204 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 2205 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 2206 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 2207 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 2208 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 2209 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 2210 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2211 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2212 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2213 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2214 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 2215 { } 2216 }; 2217 2218 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2219