1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Atheros 803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of_gpio.h> 16 #include <linux/gpio/consumer.h> 17 18 #define AT803X_INTR_ENABLE 0x12 19 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 20 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 21 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 22 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 23 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 24 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 25 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 26 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 27 #define AT803X_INTR_ENABLE_WOL BIT(0) 28 29 #define AT803X_INTR_STATUS 0x13 30 31 #define AT803X_SMART_SPEED 0x14 32 #define AT803X_LED_CONTROL 0x18 33 34 #define AT803X_DEVICE_ADDR 0x03 35 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 36 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 37 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 38 #define AT803X_REG_CHIP_CONFIG 0x1f 39 #define AT803X_BT_BX_REG_SEL 0x8000 40 41 #define AT803X_DEBUG_ADDR 0x1D 42 #define AT803X_DEBUG_DATA 0x1E 43 44 #define AT803X_MODE_CFG_MASK 0x0F 45 #define AT803X_MODE_CFG_SGMII 0x01 46 47 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 48 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 49 50 #define AT803X_DEBUG_REG_0 0x00 51 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 52 53 #define AT803X_DEBUG_REG_5 0x05 54 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 55 56 #define ATH8030_PHY_ID 0x004dd076 57 #define ATH8031_PHY_ID 0x004dd074 58 #define ATH8035_PHY_ID 0x004dd072 59 #define AT803X_PHY_ID_MASK 0xffffffef 60 61 MODULE_DESCRIPTION("Atheros 803x PHY driver"); 62 MODULE_AUTHOR("Matus Ujhelyi"); 63 MODULE_LICENSE("GPL"); 64 65 struct at803x_priv { 66 bool phy_reset:1; 67 }; 68 69 struct at803x_context { 70 u16 bmcr; 71 u16 advertise; 72 u16 control1000; 73 u16 int_enable; 74 u16 smart_speed; 75 u16 led_control; 76 }; 77 78 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 79 { 80 int ret; 81 82 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 83 if (ret < 0) 84 return ret; 85 86 return phy_read(phydev, AT803X_DEBUG_DATA); 87 } 88 89 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 90 u16 clear, u16 set) 91 { 92 u16 val; 93 int ret; 94 95 ret = at803x_debug_reg_read(phydev, reg); 96 if (ret < 0) 97 return ret; 98 99 val = ret & 0xffff; 100 val &= ~clear; 101 val |= set; 102 103 return phy_write(phydev, AT803X_DEBUG_DATA, val); 104 } 105 106 static inline int at803x_disable_rx_delay(struct phy_device *phydev) 107 { 108 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 109 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 110 } 111 112 static inline int at803x_disable_tx_delay(struct phy_device *phydev) 113 { 114 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 115 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 116 } 117 118 /* save relevant PHY registers to private copy */ 119 static void at803x_context_save(struct phy_device *phydev, 120 struct at803x_context *context) 121 { 122 context->bmcr = phy_read(phydev, MII_BMCR); 123 context->advertise = phy_read(phydev, MII_ADVERTISE); 124 context->control1000 = phy_read(phydev, MII_CTRL1000); 125 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 126 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 127 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 128 } 129 130 /* restore relevant PHY registers from private copy */ 131 static void at803x_context_restore(struct phy_device *phydev, 132 const struct at803x_context *context) 133 { 134 phy_write(phydev, MII_BMCR, context->bmcr); 135 phy_write(phydev, MII_ADVERTISE, context->advertise); 136 phy_write(phydev, MII_CTRL1000, context->control1000); 137 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 138 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 139 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 140 } 141 142 static int at803x_set_wol(struct phy_device *phydev, 143 struct ethtool_wolinfo *wol) 144 { 145 struct net_device *ndev = phydev->attached_dev; 146 const u8 *mac; 147 int ret; 148 u32 value; 149 unsigned int i, offsets[] = { 150 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 151 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 152 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 153 }; 154 155 if (!ndev) 156 return -ENODEV; 157 158 if (wol->wolopts & WAKE_MAGIC) { 159 mac = (const u8 *) ndev->dev_addr; 160 161 if (!is_valid_ether_addr(mac)) 162 return -EINVAL; 163 164 for (i = 0; i < 3; i++) 165 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 166 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 167 168 value = phy_read(phydev, AT803X_INTR_ENABLE); 169 value |= AT803X_INTR_ENABLE_WOL; 170 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 171 if (ret) 172 return ret; 173 value = phy_read(phydev, AT803X_INTR_STATUS); 174 } else { 175 value = phy_read(phydev, AT803X_INTR_ENABLE); 176 value &= (~AT803X_INTR_ENABLE_WOL); 177 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 178 if (ret) 179 return ret; 180 value = phy_read(phydev, AT803X_INTR_STATUS); 181 } 182 183 return ret; 184 } 185 186 static void at803x_get_wol(struct phy_device *phydev, 187 struct ethtool_wolinfo *wol) 188 { 189 u32 value; 190 191 wol->supported = WAKE_MAGIC; 192 wol->wolopts = 0; 193 194 value = phy_read(phydev, AT803X_INTR_ENABLE); 195 if (value & AT803X_INTR_ENABLE_WOL) 196 wol->wolopts |= WAKE_MAGIC; 197 } 198 199 static int at803x_suspend(struct phy_device *phydev) 200 { 201 int value; 202 int wol_enabled; 203 204 value = phy_read(phydev, AT803X_INTR_ENABLE); 205 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 206 207 if (wol_enabled) 208 value = BMCR_ISOLATE; 209 else 210 value = BMCR_PDOWN; 211 212 phy_modify(phydev, MII_BMCR, 0, value); 213 214 return 0; 215 } 216 217 static int at803x_resume(struct phy_device *phydev) 218 { 219 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 220 } 221 222 static int at803x_probe(struct phy_device *phydev) 223 { 224 struct device *dev = &phydev->mdio.dev; 225 struct at803x_priv *priv; 226 227 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 228 if (!priv) 229 return -ENOMEM; 230 231 phydev->priv = priv; 232 233 return 0; 234 } 235 236 static int at803x_config_init(struct phy_device *phydev) 237 { 238 int ret; 239 240 ret = genphy_config_init(phydev); 241 if (ret < 0) 242 return ret; 243 244 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || 245 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 246 phydev->interface == PHY_INTERFACE_MODE_RGMII) { 247 ret = at803x_disable_rx_delay(phydev); 248 if (ret < 0) 249 return ret; 250 } 251 252 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || 253 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 254 phydev->interface == PHY_INTERFACE_MODE_RGMII) { 255 ret = at803x_disable_tx_delay(phydev); 256 if (ret < 0) 257 return ret; 258 } 259 260 return 0; 261 } 262 263 static int at803x_ack_interrupt(struct phy_device *phydev) 264 { 265 int err; 266 267 err = phy_read(phydev, AT803X_INTR_STATUS); 268 269 return (err < 0) ? err : 0; 270 } 271 272 static int at803x_config_intr(struct phy_device *phydev) 273 { 274 int err; 275 int value; 276 277 value = phy_read(phydev, AT803X_INTR_ENABLE); 278 279 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 280 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 281 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 282 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 283 value |= AT803X_INTR_ENABLE_LINK_FAIL; 284 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 285 286 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 287 } 288 else 289 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 290 291 return err; 292 } 293 294 static void at803x_link_change_notify(struct phy_device *phydev) 295 { 296 struct at803x_priv *priv = phydev->priv; 297 298 /* 299 * Conduct a hardware reset for AT8030 every time a link loss is 300 * signalled. This is necessary to circumvent a hardware bug that 301 * occurs when the cable is unplugged while TX packets are pending 302 * in the FIFO. In such cases, the FIFO enters an error mode it 303 * cannot recover from by software. 304 */ 305 if (phydev->state == PHY_NOLINK) { 306 if (phydev->mdio.reset && !priv->phy_reset) { 307 struct at803x_context context; 308 309 at803x_context_save(phydev, &context); 310 311 phy_device_reset(phydev, 1); 312 msleep(1); 313 phy_device_reset(phydev, 0); 314 msleep(1); 315 316 at803x_context_restore(phydev, &context); 317 318 phydev_dbg(phydev, "%s(): phy was reset\n", 319 __func__); 320 priv->phy_reset = true; 321 } 322 } else { 323 priv->phy_reset = false; 324 } 325 } 326 327 static int at803x_aneg_done(struct phy_device *phydev) 328 { 329 int ccr; 330 331 int aneg_done = genphy_aneg_done(phydev); 332 if (aneg_done != BMSR_ANEGCOMPLETE) 333 return aneg_done; 334 335 /* 336 * in SGMII mode, if copper side autoneg is successful, 337 * also check SGMII side autoneg result 338 */ 339 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 340 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII) 341 return aneg_done; 342 343 /* switch to SGMII/fiber page */ 344 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL); 345 346 /* check if the SGMII link is OK. */ 347 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { 348 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); 349 aneg_done = 0; 350 } 351 /* switch back to copper page */ 352 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); 353 354 return aneg_done; 355 } 356 357 static struct phy_driver at803x_driver[] = { 358 { 359 /* ATHEROS 8035 */ 360 .phy_id = ATH8035_PHY_ID, 361 .name = "Atheros 8035 ethernet", 362 .phy_id_mask = AT803X_PHY_ID_MASK, 363 .probe = at803x_probe, 364 .config_init = at803x_config_init, 365 .set_wol = at803x_set_wol, 366 .get_wol = at803x_get_wol, 367 .suspend = at803x_suspend, 368 .resume = at803x_resume, 369 .features = PHY_GBIT_FEATURES, 370 .ack_interrupt = at803x_ack_interrupt, 371 .config_intr = at803x_config_intr, 372 }, { 373 /* ATHEROS 8030 */ 374 .phy_id = ATH8030_PHY_ID, 375 .name = "Atheros 8030 ethernet", 376 .phy_id_mask = AT803X_PHY_ID_MASK, 377 .probe = at803x_probe, 378 .config_init = at803x_config_init, 379 .link_change_notify = at803x_link_change_notify, 380 .set_wol = at803x_set_wol, 381 .get_wol = at803x_get_wol, 382 .suspend = at803x_suspend, 383 .resume = at803x_resume, 384 .features = PHY_BASIC_FEATURES, 385 .ack_interrupt = at803x_ack_interrupt, 386 .config_intr = at803x_config_intr, 387 }, { 388 /* ATHEROS 8031 */ 389 .phy_id = ATH8031_PHY_ID, 390 .name = "Atheros 8031 ethernet", 391 .phy_id_mask = AT803X_PHY_ID_MASK, 392 .probe = at803x_probe, 393 .config_init = at803x_config_init, 394 .set_wol = at803x_set_wol, 395 .get_wol = at803x_get_wol, 396 .suspend = at803x_suspend, 397 .resume = at803x_resume, 398 .features = PHY_GBIT_FEATURES, 399 .aneg_done = at803x_aneg_done, 400 .ack_interrupt = &at803x_ack_interrupt, 401 .config_intr = &at803x_config_intr, 402 } }; 403 404 module_phy_driver(at803x_driver); 405 406 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 407 { ATH8030_PHY_ID, AT803X_PHY_ID_MASK }, 408 { ATH8031_PHY_ID, AT803X_PHY_ID_MASK }, 409 { ATH8035_PHY_ID, AT803X_PHY_ID_MASK }, 410 { } 411 }; 412 413 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 414