1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <dt-bindings/net/qca-ar803x.h> 23 24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 25 #define AT803X_SFC_ASSERT_CRS BIT(11) 26 #define AT803X_SFC_FORCE_LINK BIT(10) 27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 29 #define AT803X_SFC_MANUAL_MDIX 0x1 30 #define AT803X_SFC_MANUAL_MDI 0x0 31 #define AT803X_SFC_SQE_TEST BIT(2) 32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 33 #define AT803X_SFC_DISABLE_JABBER BIT(0) 34 35 #define AT803X_SPECIFIC_STATUS 0x11 36 #define AT803X_SS_SPEED_MASK (3 << 14) 37 #define AT803X_SS_SPEED_1000 (2 << 14) 38 #define AT803X_SS_SPEED_100 (1 << 14) 39 #define AT803X_SS_SPEED_10 (0 << 14) 40 #define AT803X_SS_DUPLEX BIT(13) 41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 42 #define AT803X_SS_MDIX BIT(6) 43 44 #define AT803X_INTR_ENABLE 0x12 45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 53 #define AT803X_INTR_ENABLE_WOL BIT(0) 54 55 #define AT803X_INTR_STATUS 0x13 56 57 #define AT803X_SMART_SPEED 0x14 58 #define AT803X_SMART_SPEED_ENABLE BIT(5) 59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 61 #define AT803X_CDT 0x16 62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 63 #define AT803X_CDT_ENABLE_TEST BIT(0) 64 #define AT803X_CDT_STATUS 0x1c 65 #define AT803X_CDT_STATUS_STAT_NORMAL 0 66 #define AT803X_CDT_STATUS_STAT_SHORT 1 67 #define AT803X_CDT_STATUS_STAT_OPEN 2 68 #define AT803X_CDT_STATUS_STAT_FAIL 3 69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 71 #define AT803X_LED_CONTROL 0x18 72 73 #define AT803X_DEVICE_ADDR 0x03 74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 77 #define AT803X_REG_CHIP_CONFIG 0x1f 78 #define AT803X_BT_BX_REG_SEL 0x8000 79 80 #define AT803X_DEBUG_ADDR 0x1D 81 #define AT803X_DEBUG_DATA 0x1E 82 83 #define AT803X_MODE_CFG_MASK 0x0F 84 #define AT803X_MODE_CFG_SGMII 0x01 85 86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 88 89 #define AT803X_DEBUG_REG_0 0x00 90 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 91 92 #define AT803X_DEBUG_REG_5 0x05 93 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 94 95 #define AT803X_DEBUG_REG_1F 0x1F 96 #define AT803X_DEBUG_PLL_ON BIT(2) 97 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 98 99 /* AT803x supports either the XTAL input pad, an internal PLL or the 100 * DSP as clock reference for the clock output pad. The XTAL reference 101 * is only used for 25 MHz output, all other frequencies need the PLL. 102 * The DSP as a clock reference is used in synchronous ethernet 103 * applications. 104 * 105 * By default the PLL is only enabled if there is a link. Otherwise 106 * the PHY will go into low power state and disabled the PLL. You can 107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 108 * enabled. 109 */ 110 #define AT803X_MMD7_CLK25M 0x8016 111 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 112 #define AT803X_CLK_OUT_25MHZ_XTAL 0 113 #define AT803X_CLK_OUT_25MHZ_DSP 1 114 #define AT803X_CLK_OUT_50MHZ_PLL 2 115 #define AT803X_CLK_OUT_50MHZ_DSP 3 116 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 117 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 118 #define AT803X_CLK_OUT_125MHZ_PLL 6 119 #define AT803X_CLK_OUT_125MHZ_DSP 7 120 121 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 122 * but doesn't support choosing between XTAL/PLL and DSP. 123 */ 124 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 125 126 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 127 #define AT803X_CLK_OUT_STRENGTH_FULL 0 128 #define AT803X_CLK_OUT_STRENGTH_HALF 1 129 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 130 131 #define AT803X_DEFAULT_DOWNSHIFT 5 132 #define AT803X_MIN_DOWNSHIFT 2 133 #define AT803X_MAX_DOWNSHIFT 9 134 135 #define ATH9331_PHY_ID 0x004dd041 136 #define ATH8030_PHY_ID 0x004dd076 137 #define ATH8031_PHY_ID 0x004dd074 138 #define ATH8032_PHY_ID 0x004dd023 139 #define ATH8035_PHY_ID 0x004dd072 140 #define AT8030_PHY_ID_MASK 0xffffffef 141 142 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 143 MODULE_AUTHOR("Matus Ujhelyi"); 144 MODULE_LICENSE("GPL"); 145 146 struct at803x_priv { 147 int flags; 148 #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ 149 u16 clk_25m_reg; 150 u16 clk_25m_mask; 151 struct regulator_dev *vddio_rdev; 152 struct regulator_dev *vddh_rdev; 153 struct regulator *vddio; 154 }; 155 156 struct at803x_context { 157 u16 bmcr; 158 u16 advertise; 159 u16 control1000; 160 u16 int_enable; 161 u16 smart_speed; 162 u16 led_control; 163 }; 164 165 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 166 { 167 int ret; 168 169 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 170 if (ret < 0) 171 return ret; 172 173 return phy_read(phydev, AT803X_DEBUG_DATA); 174 } 175 176 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 177 u16 clear, u16 set) 178 { 179 u16 val; 180 int ret; 181 182 ret = at803x_debug_reg_read(phydev, reg); 183 if (ret < 0) 184 return ret; 185 186 val = ret & 0xffff; 187 val &= ~clear; 188 val |= set; 189 190 return phy_write(phydev, AT803X_DEBUG_DATA, val); 191 } 192 193 static int at803x_enable_rx_delay(struct phy_device *phydev) 194 { 195 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 196 AT803X_DEBUG_RX_CLK_DLY_EN); 197 } 198 199 static int at803x_enable_tx_delay(struct phy_device *phydev) 200 { 201 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 202 AT803X_DEBUG_TX_CLK_DLY_EN); 203 } 204 205 static int at803x_disable_rx_delay(struct phy_device *phydev) 206 { 207 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 208 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 209 } 210 211 static int at803x_disable_tx_delay(struct phy_device *phydev) 212 { 213 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 214 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 215 } 216 217 /* save relevant PHY registers to private copy */ 218 static void at803x_context_save(struct phy_device *phydev, 219 struct at803x_context *context) 220 { 221 context->bmcr = phy_read(phydev, MII_BMCR); 222 context->advertise = phy_read(phydev, MII_ADVERTISE); 223 context->control1000 = phy_read(phydev, MII_CTRL1000); 224 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 225 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 226 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 227 } 228 229 /* restore relevant PHY registers from private copy */ 230 static void at803x_context_restore(struct phy_device *phydev, 231 const struct at803x_context *context) 232 { 233 phy_write(phydev, MII_BMCR, context->bmcr); 234 phy_write(phydev, MII_ADVERTISE, context->advertise); 235 phy_write(phydev, MII_CTRL1000, context->control1000); 236 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 237 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 238 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 239 } 240 241 static int at803x_set_wol(struct phy_device *phydev, 242 struct ethtool_wolinfo *wol) 243 { 244 struct net_device *ndev = phydev->attached_dev; 245 const u8 *mac; 246 int ret; 247 u32 value; 248 unsigned int i, offsets[] = { 249 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 250 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 251 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 252 }; 253 254 if (!ndev) 255 return -ENODEV; 256 257 if (wol->wolopts & WAKE_MAGIC) { 258 mac = (const u8 *) ndev->dev_addr; 259 260 if (!is_valid_ether_addr(mac)) 261 return -EINVAL; 262 263 for (i = 0; i < 3; i++) 264 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 265 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 266 267 value = phy_read(phydev, AT803X_INTR_ENABLE); 268 value |= AT803X_INTR_ENABLE_WOL; 269 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 270 if (ret) 271 return ret; 272 value = phy_read(phydev, AT803X_INTR_STATUS); 273 } else { 274 value = phy_read(phydev, AT803X_INTR_ENABLE); 275 value &= (~AT803X_INTR_ENABLE_WOL); 276 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 277 if (ret) 278 return ret; 279 value = phy_read(phydev, AT803X_INTR_STATUS); 280 } 281 282 return ret; 283 } 284 285 static void at803x_get_wol(struct phy_device *phydev, 286 struct ethtool_wolinfo *wol) 287 { 288 u32 value; 289 290 wol->supported = WAKE_MAGIC; 291 wol->wolopts = 0; 292 293 value = phy_read(phydev, AT803X_INTR_ENABLE); 294 if (value & AT803X_INTR_ENABLE_WOL) 295 wol->wolopts |= WAKE_MAGIC; 296 } 297 298 static int at803x_suspend(struct phy_device *phydev) 299 { 300 int value; 301 int wol_enabled; 302 303 value = phy_read(phydev, AT803X_INTR_ENABLE); 304 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 305 306 if (wol_enabled) 307 value = BMCR_ISOLATE; 308 else 309 value = BMCR_PDOWN; 310 311 phy_modify(phydev, MII_BMCR, 0, value); 312 313 return 0; 314 } 315 316 static int at803x_resume(struct phy_device *phydev) 317 { 318 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 319 } 320 321 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 322 unsigned int selector) 323 { 324 struct phy_device *phydev = rdev_get_drvdata(rdev); 325 326 if (selector) 327 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 328 0, AT803X_DEBUG_RGMII_1V8); 329 else 330 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 331 AT803X_DEBUG_RGMII_1V8, 0); 332 } 333 334 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 335 { 336 struct phy_device *phydev = rdev_get_drvdata(rdev); 337 int val; 338 339 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 340 if (val < 0) 341 return val; 342 343 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 344 } 345 346 static struct regulator_ops vddio_regulator_ops = { 347 .list_voltage = regulator_list_voltage_table, 348 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 349 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 350 }; 351 352 static const unsigned int vddio_voltage_table[] = { 353 1500000, 354 1800000, 355 }; 356 357 static const struct regulator_desc vddio_desc = { 358 .name = "vddio", 359 .of_match = of_match_ptr("vddio-regulator"), 360 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 361 .volt_table = vddio_voltage_table, 362 .ops = &vddio_regulator_ops, 363 .type = REGULATOR_VOLTAGE, 364 .owner = THIS_MODULE, 365 }; 366 367 static struct regulator_ops vddh_regulator_ops = { 368 }; 369 370 static const struct regulator_desc vddh_desc = { 371 .name = "vddh", 372 .of_match = of_match_ptr("vddh-regulator"), 373 .n_voltages = 1, 374 .fixed_uV = 2500000, 375 .ops = &vddh_regulator_ops, 376 .type = REGULATOR_VOLTAGE, 377 .owner = THIS_MODULE, 378 }; 379 380 static int at8031_register_regulators(struct phy_device *phydev) 381 { 382 struct at803x_priv *priv = phydev->priv; 383 struct device *dev = &phydev->mdio.dev; 384 struct regulator_config config = { }; 385 386 config.dev = dev; 387 config.driver_data = phydev; 388 389 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 390 if (IS_ERR(priv->vddio_rdev)) { 391 phydev_err(phydev, "failed to register VDDIO regulator\n"); 392 return PTR_ERR(priv->vddio_rdev); 393 } 394 395 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 396 if (IS_ERR(priv->vddh_rdev)) { 397 phydev_err(phydev, "failed to register VDDH regulator\n"); 398 return PTR_ERR(priv->vddh_rdev); 399 } 400 401 return 0; 402 } 403 404 static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) 405 { 406 return (phydev->phy_id & phydev->drv->phy_id_mask) 407 == (phy_id & phydev->drv->phy_id_mask); 408 } 409 410 static int at803x_parse_dt(struct phy_device *phydev) 411 { 412 struct device_node *node = phydev->mdio.dev.of_node; 413 struct at803x_priv *priv = phydev->priv; 414 u32 freq, strength; 415 unsigned int sel; 416 int ret; 417 418 if (!IS_ENABLED(CONFIG_OF_MDIO)) 419 return 0; 420 421 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 422 if (!ret) { 423 switch (freq) { 424 case 25000000: 425 sel = AT803X_CLK_OUT_25MHZ_XTAL; 426 break; 427 case 50000000: 428 sel = AT803X_CLK_OUT_50MHZ_PLL; 429 break; 430 case 62500000: 431 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 432 break; 433 case 125000000: 434 sel = AT803X_CLK_OUT_125MHZ_PLL; 435 break; 436 default: 437 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 438 return -EINVAL; 439 } 440 441 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 442 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 443 444 /* Fixup for the AR8030/AR8035. This chip has another mask and 445 * doesn't support the DSP reference. Eg. the lowest bit of the 446 * mask. The upper two bits select the same frequencies. Mask 447 * the lowest bit here. 448 * 449 * Warning: 450 * There was no datasheet for the AR8030 available so this is 451 * just a guess. But the AR8035 is listed as pin compatible 452 * to the AR8030 so there might be a good chance it works on 453 * the AR8030 too. 454 */ 455 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || 456 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { 457 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 458 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 459 } 460 } 461 462 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 463 if (!ret) { 464 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 465 switch (strength) { 466 case AR803X_STRENGTH_FULL: 467 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 468 break; 469 case AR803X_STRENGTH_HALF: 470 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 471 break; 472 case AR803X_STRENGTH_QUARTER: 473 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 474 break; 475 default: 476 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 477 return -EINVAL; 478 } 479 } 480 481 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 482 * options. 483 */ 484 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 485 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 486 priv->flags |= AT803X_KEEP_PLL_ENABLED; 487 488 ret = at8031_register_regulators(phydev); 489 if (ret < 0) 490 return ret; 491 492 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 493 "vddio"); 494 if (IS_ERR(priv->vddio)) { 495 phydev_err(phydev, "failed to get VDDIO regulator\n"); 496 return PTR_ERR(priv->vddio); 497 } 498 499 ret = regulator_enable(priv->vddio); 500 if (ret < 0) 501 return ret; 502 } 503 504 return 0; 505 } 506 507 static int at803x_probe(struct phy_device *phydev) 508 { 509 struct device *dev = &phydev->mdio.dev; 510 struct at803x_priv *priv; 511 512 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 513 if (!priv) 514 return -ENOMEM; 515 516 phydev->priv = priv; 517 518 return at803x_parse_dt(phydev); 519 } 520 521 static void at803x_remove(struct phy_device *phydev) 522 { 523 struct at803x_priv *priv = phydev->priv; 524 525 if (priv->vddio) 526 regulator_disable(priv->vddio); 527 } 528 529 static int at803x_clk_out_config(struct phy_device *phydev) 530 { 531 struct at803x_priv *priv = phydev->priv; 532 int val; 533 534 if (!priv->clk_25m_mask) 535 return 0; 536 537 val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M); 538 if (val < 0) 539 return val; 540 541 val &= ~priv->clk_25m_mask; 542 val |= priv->clk_25m_reg; 543 544 return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val); 545 } 546 547 static int at8031_pll_config(struct phy_device *phydev) 548 { 549 struct at803x_priv *priv = phydev->priv; 550 551 /* The default after hardware reset is PLL OFF. After a soft reset, the 552 * values are retained. 553 */ 554 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 555 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 556 0, AT803X_DEBUG_PLL_ON); 557 else 558 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 559 AT803X_DEBUG_PLL_ON, 0); 560 } 561 562 static int at803x_config_init(struct phy_device *phydev) 563 { 564 int ret; 565 566 /* The RX and TX delay default is: 567 * after HW reset: RX delay enabled and TX delay disabled 568 * after SW reset: RX delay enabled, while TX delay retains the 569 * value before reset. 570 */ 571 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 572 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 573 ret = at803x_enable_rx_delay(phydev); 574 else 575 ret = at803x_disable_rx_delay(phydev); 576 if (ret < 0) 577 return ret; 578 579 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 580 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 581 ret = at803x_enable_tx_delay(phydev); 582 else 583 ret = at803x_disable_tx_delay(phydev); 584 if (ret < 0) 585 return ret; 586 587 ret = at803x_clk_out_config(phydev); 588 if (ret < 0) 589 return ret; 590 591 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 592 ret = at8031_pll_config(phydev); 593 if (ret < 0) 594 return ret; 595 } 596 597 return 0; 598 } 599 600 static int at803x_ack_interrupt(struct phy_device *phydev) 601 { 602 int err; 603 604 err = phy_read(phydev, AT803X_INTR_STATUS); 605 606 return (err < 0) ? err : 0; 607 } 608 609 static int at803x_config_intr(struct phy_device *phydev) 610 { 611 int err; 612 int value; 613 614 value = phy_read(phydev, AT803X_INTR_ENABLE); 615 616 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 617 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 618 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 619 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 620 value |= AT803X_INTR_ENABLE_LINK_FAIL; 621 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 622 623 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 624 } 625 else 626 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 627 628 return err; 629 } 630 631 static void at803x_link_change_notify(struct phy_device *phydev) 632 { 633 /* 634 * Conduct a hardware reset for AT8030 every time a link loss is 635 * signalled. This is necessary to circumvent a hardware bug that 636 * occurs when the cable is unplugged while TX packets are pending 637 * in the FIFO. In such cases, the FIFO enters an error mode it 638 * cannot recover from by software. 639 */ 640 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 641 struct at803x_context context; 642 643 at803x_context_save(phydev, &context); 644 645 phy_device_reset(phydev, 1); 646 msleep(1); 647 phy_device_reset(phydev, 0); 648 msleep(1); 649 650 at803x_context_restore(phydev, &context); 651 652 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 653 } 654 } 655 656 static int at803x_aneg_done(struct phy_device *phydev) 657 { 658 int ccr; 659 660 int aneg_done = genphy_aneg_done(phydev); 661 if (aneg_done != BMSR_ANEGCOMPLETE) 662 return aneg_done; 663 664 /* 665 * in SGMII mode, if copper side autoneg is successful, 666 * also check SGMII side autoneg result 667 */ 668 ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 669 if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII) 670 return aneg_done; 671 672 /* switch to SGMII/fiber page */ 673 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL); 674 675 /* check if the SGMII link is OK. */ 676 if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { 677 phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); 678 aneg_done = 0; 679 } 680 /* switch back to copper page */ 681 phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); 682 683 return aneg_done; 684 } 685 686 static int at803x_read_status(struct phy_device *phydev) 687 { 688 int ss, err, old_link = phydev->link; 689 690 /* Update the link, but return if there was an error */ 691 err = genphy_update_link(phydev); 692 if (err) 693 return err; 694 695 /* why bother the PHY if nothing can have changed */ 696 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 697 return 0; 698 699 phydev->speed = SPEED_UNKNOWN; 700 phydev->duplex = DUPLEX_UNKNOWN; 701 phydev->pause = 0; 702 phydev->asym_pause = 0; 703 704 err = genphy_read_lpa(phydev); 705 if (err < 0) 706 return err; 707 708 /* Read the AT8035 PHY-Specific Status register, which indicates the 709 * speed and duplex that the PHY is actually using, irrespective of 710 * whether we are in autoneg mode or not. 711 */ 712 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 713 if (ss < 0) 714 return ss; 715 716 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 717 int sfc; 718 719 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 720 if (sfc < 0) 721 return sfc; 722 723 switch (ss & AT803X_SS_SPEED_MASK) { 724 case AT803X_SS_SPEED_10: 725 phydev->speed = SPEED_10; 726 break; 727 case AT803X_SS_SPEED_100: 728 phydev->speed = SPEED_100; 729 break; 730 case AT803X_SS_SPEED_1000: 731 phydev->speed = SPEED_1000; 732 break; 733 } 734 if (ss & AT803X_SS_DUPLEX) 735 phydev->duplex = DUPLEX_FULL; 736 else 737 phydev->duplex = DUPLEX_HALF; 738 739 if (ss & AT803X_SS_MDIX) 740 phydev->mdix = ETH_TP_MDI_X; 741 else 742 phydev->mdix = ETH_TP_MDI; 743 744 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 745 case AT803X_SFC_MANUAL_MDI: 746 phydev->mdix_ctrl = ETH_TP_MDI; 747 break; 748 case AT803X_SFC_MANUAL_MDIX: 749 phydev->mdix_ctrl = ETH_TP_MDI_X; 750 break; 751 case AT803X_SFC_AUTOMATIC_CROSSOVER: 752 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 753 break; 754 } 755 } 756 757 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 758 phy_resolve_aneg_pause(phydev); 759 760 return 0; 761 } 762 763 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 764 { 765 u16 val; 766 767 switch (ctrl) { 768 case ETH_TP_MDI: 769 val = AT803X_SFC_MANUAL_MDI; 770 break; 771 case ETH_TP_MDI_X: 772 val = AT803X_SFC_MANUAL_MDIX; 773 break; 774 case ETH_TP_MDI_AUTO: 775 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 776 break; 777 default: 778 return 0; 779 } 780 781 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 782 AT803X_SFC_MDI_CROSSOVER_MODE_M, 783 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 784 } 785 786 static int at803x_config_aneg(struct phy_device *phydev) 787 { 788 int ret; 789 790 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 791 if (ret < 0) 792 return ret; 793 794 /* Changes of the midx bits are disruptive to the normal operation; 795 * therefore any changes to these registers must be followed by a 796 * software reset to take effect. 797 */ 798 if (ret == 1) { 799 ret = genphy_soft_reset(phydev); 800 if (ret < 0) 801 return ret; 802 } 803 804 return genphy_config_aneg(phydev); 805 } 806 807 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 808 { 809 int val; 810 811 val = phy_read(phydev, AT803X_SMART_SPEED); 812 if (val < 0) 813 return val; 814 815 if (val & AT803X_SMART_SPEED_ENABLE) 816 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 817 else 818 *d = DOWNSHIFT_DEV_DISABLE; 819 820 return 0; 821 } 822 823 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 824 { 825 u16 mask, set; 826 int ret; 827 828 switch (cnt) { 829 case DOWNSHIFT_DEV_DEFAULT_COUNT: 830 cnt = AT803X_DEFAULT_DOWNSHIFT; 831 fallthrough; 832 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 833 set = AT803X_SMART_SPEED_ENABLE | 834 AT803X_SMART_SPEED_BYPASS_TIMER | 835 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 836 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 837 break; 838 case DOWNSHIFT_DEV_DISABLE: 839 set = 0; 840 mask = AT803X_SMART_SPEED_ENABLE | 841 AT803X_SMART_SPEED_BYPASS_TIMER; 842 break; 843 default: 844 return -EINVAL; 845 } 846 847 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 848 849 /* After changing the smart speed settings, we need to perform a 850 * software reset, use phy_init_hw() to make sure we set the 851 * reapply any values which might got lost during software reset. 852 */ 853 if (ret == 1) 854 ret = phy_init_hw(phydev); 855 856 return ret; 857 } 858 859 static int at803x_get_tunable(struct phy_device *phydev, 860 struct ethtool_tunable *tuna, void *data) 861 { 862 switch (tuna->id) { 863 case ETHTOOL_PHY_DOWNSHIFT: 864 return at803x_get_downshift(phydev, data); 865 default: 866 return -EOPNOTSUPP; 867 } 868 } 869 870 static int at803x_set_tunable(struct phy_device *phydev, 871 struct ethtool_tunable *tuna, const void *data) 872 { 873 switch (tuna->id) { 874 case ETHTOOL_PHY_DOWNSHIFT: 875 return at803x_set_downshift(phydev, *(const u8 *)data); 876 default: 877 return -EOPNOTSUPP; 878 } 879 } 880 881 static int at803x_cable_test_result_trans(u16 status) 882 { 883 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 884 case AT803X_CDT_STATUS_STAT_NORMAL: 885 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 886 case AT803X_CDT_STATUS_STAT_SHORT: 887 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 888 case AT803X_CDT_STATUS_STAT_OPEN: 889 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 890 case AT803X_CDT_STATUS_STAT_FAIL: 891 default: 892 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 893 } 894 } 895 896 static bool at803x_cdt_test_failed(u16 status) 897 { 898 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 899 AT803X_CDT_STATUS_STAT_FAIL; 900 } 901 902 static bool at803x_cdt_fault_length_valid(u16 status) 903 { 904 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 905 case AT803X_CDT_STATUS_STAT_OPEN: 906 case AT803X_CDT_STATUS_STAT_SHORT: 907 return true; 908 } 909 return false; 910 } 911 912 static int at803x_cdt_fault_length(u16 status) 913 { 914 int dt; 915 916 /* According to the datasheet the distance to the fault is 917 * DELTA_TIME * 0.824 meters. 918 * 919 * The author suspect the correct formula is: 920 * 921 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 922 * 923 * where c is the speed of light, VF is the velocity factor of 924 * the twisted pair cable, 125MHz the counter frequency and 925 * we need to divide by 2 because the hardware will measure the 926 * round trip time to the fault and back to the PHY. 927 * 928 * With a VF of 0.69 we get the factor 0.824 mentioned in the 929 * datasheet. 930 */ 931 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 932 933 return (dt * 824) / 10; 934 } 935 936 static int at803x_cdt_start(struct phy_device *phydev, int pair) 937 { 938 u16 cdt; 939 940 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 941 AT803X_CDT_ENABLE_TEST; 942 943 return phy_write(phydev, AT803X_CDT, cdt); 944 } 945 946 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 947 { 948 int val, ret; 949 950 /* One test run takes about 25ms */ 951 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 952 !(val & AT803X_CDT_ENABLE_TEST), 953 30000, 100000, true); 954 955 return ret < 0 ? ret : 0; 956 } 957 958 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 959 { 960 static const int ethtool_pair[] = { 961 ETHTOOL_A_CABLE_PAIR_A, 962 ETHTOOL_A_CABLE_PAIR_B, 963 ETHTOOL_A_CABLE_PAIR_C, 964 ETHTOOL_A_CABLE_PAIR_D, 965 }; 966 int ret, val; 967 968 ret = at803x_cdt_start(phydev, pair); 969 if (ret) 970 return ret; 971 972 ret = at803x_cdt_wait_for_completion(phydev); 973 if (ret) 974 return ret; 975 976 val = phy_read(phydev, AT803X_CDT_STATUS); 977 if (val < 0) 978 return val; 979 980 if (at803x_cdt_test_failed(val)) 981 return 0; 982 983 ethnl_cable_test_result(phydev, ethtool_pair[pair], 984 at803x_cable_test_result_trans(val)); 985 986 if (at803x_cdt_fault_length_valid(val)) 987 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 988 at803x_cdt_fault_length(val)); 989 990 return 1; 991 } 992 993 static int at803x_cable_test_get_status(struct phy_device *phydev, 994 bool *finished) 995 { 996 unsigned long pair_mask; 997 int retries = 20; 998 int pair, ret; 999 1000 if (phydev->phy_id == ATH9331_PHY_ID || 1001 phydev->phy_id == ATH8032_PHY_ID) 1002 pair_mask = 0x3; 1003 else 1004 pair_mask = 0xf; 1005 1006 *finished = false; 1007 1008 /* According to the datasheet the CDT can be performed when 1009 * there is no link partner or when the link partner is 1010 * auto-negotiating. Starting the test will restart the AN 1011 * automatically. It seems that doing this repeatedly we will 1012 * get a slot where our link partner won't disturb our 1013 * measurement. 1014 */ 1015 while (pair_mask && retries--) { 1016 for_each_set_bit(pair, &pair_mask, 4) { 1017 ret = at803x_cable_test_one_pair(phydev, pair); 1018 if (ret < 0) 1019 return ret; 1020 if (ret) 1021 clear_bit(pair, &pair_mask); 1022 } 1023 if (pair_mask) 1024 msleep(250); 1025 } 1026 1027 *finished = true; 1028 1029 return 0; 1030 } 1031 1032 static int at803x_cable_test_start(struct phy_device *phydev) 1033 { 1034 /* Enable auto-negotiation, but advertise no capabilities, no link 1035 * will be established. A restart of the auto-negotiation is not 1036 * required, because the cable test will automatically break the link. 1037 */ 1038 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1039 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1040 if (phydev->phy_id != ATH9331_PHY_ID && 1041 phydev->phy_id != ATH8032_PHY_ID) 1042 phy_write(phydev, MII_CTRL1000, 0); 1043 1044 /* we do all the (time consuming) work later */ 1045 return 0; 1046 } 1047 1048 static struct phy_driver at803x_driver[] = { 1049 { 1050 /* Qualcomm Atheros AR8035 */ 1051 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1052 .name = "Qualcomm Atheros AR8035", 1053 .flags = PHY_POLL_CABLE_TEST, 1054 .probe = at803x_probe, 1055 .remove = at803x_remove, 1056 .config_aneg = at803x_config_aneg, 1057 .config_init = at803x_config_init, 1058 .soft_reset = genphy_soft_reset, 1059 .set_wol = at803x_set_wol, 1060 .get_wol = at803x_get_wol, 1061 .suspend = at803x_suspend, 1062 .resume = at803x_resume, 1063 /* PHY_GBIT_FEATURES */ 1064 .read_status = at803x_read_status, 1065 .ack_interrupt = at803x_ack_interrupt, 1066 .config_intr = at803x_config_intr, 1067 .get_tunable = at803x_get_tunable, 1068 .set_tunable = at803x_set_tunable, 1069 .cable_test_start = at803x_cable_test_start, 1070 .cable_test_get_status = at803x_cable_test_get_status, 1071 }, { 1072 /* Qualcomm Atheros AR8030 */ 1073 .phy_id = ATH8030_PHY_ID, 1074 .name = "Qualcomm Atheros AR8030", 1075 .phy_id_mask = AT8030_PHY_ID_MASK, 1076 .probe = at803x_probe, 1077 .remove = at803x_remove, 1078 .config_init = at803x_config_init, 1079 .link_change_notify = at803x_link_change_notify, 1080 .set_wol = at803x_set_wol, 1081 .get_wol = at803x_get_wol, 1082 .suspend = at803x_suspend, 1083 .resume = at803x_resume, 1084 /* PHY_BASIC_FEATURES */ 1085 .ack_interrupt = at803x_ack_interrupt, 1086 .config_intr = at803x_config_intr, 1087 }, { 1088 /* Qualcomm Atheros AR8031/AR8033 */ 1089 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1090 .name = "Qualcomm Atheros AR8031/AR8033", 1091 .flags = PHY_POLL_CABLE_TEST, 1092 .probe = at803x_probe, 1093 .remove = at803x_remove, 1094 .config_init = at803x_config_init, 1095 .soft_reset = genphy_soft_reset, 1096 .set_wol = at803x_set_wol, 1097 .get_wol = at803x_get_wol, 1098 .suspend = at803x_suspend, 1099 .resume = at803x_resume, 1100 /* PHY_GBIT_FEATURES */ 1101 .read_status = at803x_read_status, 1102 .aneg_done = at803x_aneg_done, 1103 .ack_interrupt = &at803x_ack_interrupt, 1104 .config_intr = &at803x_config_intr, 1105 .get_tunable = at803x_get_tunable, 1106 .set_tunable = at803x_set_tunable, 1107 .cable_test_start = at803x_cable_test_start, 1108 .cable_test_get_status = at803x_cable_test_get_status, 1109 }, { 1110 /* Qualcomm Atheros AR8032 */ 1111 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1112 .name = "Qualcomm Atheros AR8032", 1113 .probe = at803x_probe, 1114 .remove = at803x_remove, 1115 .flags = PHY_POLL_CABLE_TEST, 1116 .config_init = at803x_config_init, 1117 .link_change_notify = at803x_link_change_notify, 1118 .set_wol = at803x_set_wol, 1119 .get_wol = at803x_get_wol, 1120 .suspend = at803x_suspend, 1121 .resume = at803x_resume, 1122 /* PHY_BASIC_FEATURES */ 1123 .ack_interrupt = at803x_ack_interrupt, 1124 .config_intr = at803x_config_intr, 1125 .cable_test_start = at803x_cable_test_start, 1126 .cable_test_get_status = at803x_cable_test_get_status, 1127 }, { 1128 /* ATHEROS AR9331 */ 1129 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1130 .name = "Qualcomm Atheros AR9331 built-in PHY", 1131 .suspend = at803x_suspend, 1132 .resume = at803x_resume, 1133 .flags = PHY_POLL_CABLE_TEST, 1134 /* PHY_BASIC_FEATURES */ 1135 .ack_interrupt = &at803x_ack_interrupt, 1136 .config_intr = &at803x_config_intr, 1137 .cable_test_start = at803x_cable_test_start, 1138 .cable_test_get_status = at803x_cable_test_get_status, 1139 .read_status = at803x_read_status, 1140 .soft_reset = genphy_soft_reset, 1141 .config_aneg = at803x_config_aneg, 1142 } }; 1143 1144 module_phy_driver(at803x_driver); 1145 1146 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1147 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1148 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1149 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1150 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1151 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1152 { } 1153 }; 1154 1155 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1156