1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <dt-bindings/net/qca-ar803x.h> 23 24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 25 #define AT803X_SFC_ASSERT_CRS BIT(11) 26 #define AT803X_SFC_FORCE_LINK BIT(10) 27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 29 #define AT803X_SFC_MANUAL_MDIX 0x1 30 #define AT803X_SFC_MANUAL_MDI 0x0 31 #define AT803X_SFC_SQE_TEST BIT(2) 32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 33 #define AT803X_SFC_DISABLE_JABBER BIT(0) 34 35 #define AT803X_SPECIFIC_STATUS 0x11 36 #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 37 #define AT803X_SS_SPEED_1000 2 38 #define AT803X_SS_SPEED_100 1 39 #define AT803X_SS_SPEED_10 0 40 #define AT803X_SS_DUPLEX BIT(13) 41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 42 #define AT803X_SS_MDIX BIT(6) 43 44 #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 45 #define QCA808X_SS_SPEED_2500 4 46 47 #define AT803X_INTR_ENABLE 0x12 48 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 49 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 50 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 51 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 52 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 53 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 54 #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 55 #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 56 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 57 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 58 #define AT803X_INTR_ENABLE_WOL BIT(0) 59 60 #define AT803X_INTR_STATUS 0x13 61 62 #define AT803X_SMART_SPEED 0x14 63 #define AT803X_SMART_SPEED_ENABLE BIT(5) 64 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 65 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 66 #define AT803X_CDT 0x16 67 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 68 #define AT803X_CDT_ENABLE_TEST BIT(0) 69 #define AT803X_CDT_STATUS 0x1c 70 #define AT803X_CDT_STATUS_STAT_NORMAL 0 71 #define AT803X_CDT_STATUS_STAT_SHORT 1 72 #define AT803X_CDT_STATUS_STAT_OPEN 2 73 #define AT803X_CDT_STATUS_STAT_FAIL 3 74 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 75 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 76 #define AT803X_LED_CONTROL 0x18 77 78 #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 79 #define AT803X_WOL_EN BIT(5) 80 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 81 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 82 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 83 #define AT803X_REG_CHIP_CONFIG 0x1f 84 #define AT803X_BT_BX_REG_SEL 0x8000 85 86 #define AT803X_DEBUG_ADDR 0x1D 87 #define AT803X_DEBUG_DATA 0x1E 88 89 #define AT803X_MODE_CFG_MASK 0x0F 90 #define AT803X_MODE_CFG_BASET_RGMII 0x00 91 #define AT803X_MODE_CFG_BASET_SGMII 0x01 92 #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 93 #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 94 #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 95 #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 96 #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 97 #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 98 #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 99 #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 100 #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 101 102 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 103 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 104 105 #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 106 #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 107 #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 108 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 109 110 #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 111 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 112 113 #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 114 #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 115 #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 116 117 #define AT803X_DEBUG_REG_3C 0x3C 118 119 #define AT803X_DEBUG_REG_GREEN 0x3D 120 #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 121 122 #define AT803X_DEBUG_REG_1F 0x1F 123 #define AT803X_DEBUG_PLL_ON BIT(2) 124 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 125 126 #define MDIO_AZ_DEBUG 0x800D 127 128 /* AT803x supports either the XTAL input pad, an internal PLL or the 129 * DSP as clock reference for the clock output pad. The XTAL reference 130 * is only used for 25 MHz output, all other frequencies need the PLL. 131 * The DSP as a clock reference is used in synchronous ethernet 132 * applications. 133 * 134 * By default the PLL is only enabled if there is a link. Otherwise 135 * the PHY will go into low power state and disabled the PLL. You can 136 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 137 * enabled. 138 */ 139 #define AT803X_MMD7_CLK25M 0x8016 140 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 141 #define AT803X_CLK_OUT_25MHZ_XTAL 0 142 #define AT803X_CLK_OUT_25MHZ_DSP 1 143 #define AT803X_CLK_OUT_50MHZ_PLL 2 144 #define AT803X_CLK_OUT_50MHZ_DSP 3 145 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 146 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 147 #define AT803X_CLK_OUT_125MHZ_PLL 6 148 #define AT803X_CLK_OUT_125MHZ_DSP 7 149 150 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 151 * but doesn't support choosing between XTAL/PLL and DSP. 152 */ 153 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 154 155 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 156 #define AT803X_CLK_OUT_STRENGTH_FULL 0 157 #define AT803X_CLK_OUT_STRENGTH_HALF 1 158 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 159 160 #define AT803X_DEFAULT_DOWNSHIFT 5 161 #define AT803X_MIN_DOWNSHIFT 2 162 #define AT803X_MAX_DOWNSHIFT 9 163 164 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 165 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 166 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 167 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 168 169 #define ATH9331_PHY_ID 0x004dd041 170 #define ATH8030_PHY_ID 0x004dd076 171 #define ATH8031_PHY_ID 0x004dd074 172 #define ATH8032_PHY_ID 0x004dd023 173 #define ATH8035_PHY_ID 0x004dd072 174 #define AT8030_PHY_ID_MASK 0xffffffef 175 176 #define QCA8081_PHY_ID 0x004dd101 177 178 #define QCA8327_A_PHY_ID 0x004dd033 179 #define QCA8327_B_PHY_ID 0x004dd034 180 #define QCA8337_PHY_ID 0x004dd036 181 #define QCA9561_PHY_ID 0x004dd042 182 #define QCA8K_PHY_ID_MASK 0xffffffff 183 184 #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 185 186 #define AT803X_PAGE_FIBER 0 187 #define AT803X_PAGE_COPPER 1 188 189 /* don't turn off internal PLL */ 190 #define AT803X_KEEP_PLL_ENABLED BIT(0) 191 #define AT803X_DISABLE_SMARTEEE BIT(1) 192 193 /* ADC threshold */ 194 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 195 #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 196 #define QCA808X_ADC_THRESHOLD_80MV 0 197 #define QCA808X_ADC_THRESHOLD_100MV 0xf0 198 #define QCA808X_ADC_THRESHOLD_200MV 0x0f 199 #define QCA808X_ADC_THRESHOLD_300MV 0xff 200 201 /* CLD control */ 202 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 203 #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 204 #define QCA808X_8023AZ_AFE_EN 0x90 205 206 /* AZ control */ 207 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 208 #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 209 210 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 211 #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 212 213 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 214 #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 215 216 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 217 #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 218 219 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 220 #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 221 222 #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 223 #define QCA808X_TOP_OPTION1_DATA 0x0 224 225 #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 226 #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 227 #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 228 #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 229 #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 230 #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 231 #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 232 #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 233 #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 234 #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 235 #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 236 #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 237 238 /* master/slave seed config */ 239 #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 240 #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 241 #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 242 #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 243 244 /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 245 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 246 */ 247 #define QCA808X_DBG_AN_TEST 0xb 248 #define QCA808X_HIBERNATION_EN BIT(15) 249 250 #define QCA808X_CDT_ENABLE_TEST BIT(15) 251 #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 252 #define QCA808X_CDT_LENGTH_UNIT BIT(10) 253 254 #define QCA808X_MMD3_CDT_STATUS 0x8064 255 #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 256 #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 257 #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 258 #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 259 #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 260 261 #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 262 #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 263 #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 264 #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 265 #define QCA808X_CDT_STATUS_STAT_FAIL 0 266 #define QCA808X_CDT_STATUS_STAT_NORMAL 1 267 #define QCA808X_CDT_STATUS_STAT_OPEN 2 268 #define QCA808X_CDT_STATUS_STAT_SHORT 3 269 270 MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 271 MODULE_AUTHOR("Matus Ujhelyi"); 272 MODULE_LICENSE("GPL"); 273 274 enum stat_access_type { 275 PHY, 276 MMD 277 }; 278 279 struct at803x_hw_stat { 280 const char *string; 281 u8 reg; 282 u32 mask; 283 enum stat_access_type access_type; 284 }; 285 286 static struct at803x_hw_stat at803x_hw_stats[] = { 287 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 288 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 289 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 290 }; 291 292 struct at803x_priv { 293 int flags; 294 u16 clk_25m_reg; 295 u16 clk_25m_mask; 296 u8 smarteee_lpi_tw_1g; 297 u8 smarteee_lpi_tw_100m; 298 bool is_fiber; 299 bool is_1000basex; 300 struct regulator_dev *vddio_rdev; 301 struct regulator_dev *vddh_rdev; 302 struct regulator *vddio; 303 u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 304 }; 305 306 struct at803x_context { 307 u16 bmcr; 308 u16 advertise; 309 u16 control1000; 310 u16 int_enable; 311 u16 smart_speed; 312 u16 led_control; 313 }; 314 315 static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 316 { 317 int ret; 318 319 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 320 if (ret < 0) 321 return ret; 322 323 return phy_write(phydev, AT803X_DEBUG_DATA, data); 324 } 325 326 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 327 { 328 int ret; 329 330 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 331 if (ret < 0) 332 return ret; 333 334 return phy_read(phydev, AT803X_DEBUG_DATA); 335 } 336 337 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 338 u16 clear, u16 set) 339 { 340 u16 val; 341 int ret; 342 343 ret = at803x_debug_reg_read(phydev, reg); 344 if (ret < 0) 345 return ret; 346 347 val = ret & 0xffff; 348 val &= ~clear; 349 val |= set; 350 351 return phy_write(phydev, AT803X_DEBUG_DATA, val); 352 } 353 354 static int at803x_write_page(struct phy_device *phydev, int page) 355 { 356 int mask; 357 int set; 358 359 if (page == AT803X_PAGE_COPPER) { 360 set = AT803X_BT_BX_REG_SEL; 361 mask = 0; 362 } else { 363 set = 0; 364 mask = AT803X_BT_BX_REG_SEL; 365 } 366 367 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 368 } 369 370 static int at803x_read_page(struct phy_device *phydev) 371 { 372 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 373 374 if (ccr < 0) 375 return ccr; 376 377 if (ccr & AT803X_BT_BX_REG_SEL) 378 return AT803X_PAGE_COPPER; 379 380 return AT803X_PAGE_FIBER; 381 } 382 383 static int at803x_enable_rx_delay(struct phy_device *phydev) 384 { 385 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 386 AT803X_DEBUG_RX_CLK_DLY_EN); 387 } 388 389 static int at803x_enable_tx_delay(struct phy_device *phydev) 390 { 391 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 392 AT803X_DEBUG_TX_CLK_DLY_EN); 393 } 394 395 static int at803x_disable_rx_delay(struct phy_device *phydev) 396 { 397 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 398 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 399 } 400 401 static int at803x_disable_tx_delay(struct phy_device *phydev) 402 { 403 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 404 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 405 } 406 407 /* save relevant PHY registers to private copy */ 408 static void at803x_context_save(struct phy_device *phydev, 409 struct at803x_context *context) 410 { 411 context->bmcr = phy_read(phydev, MII_BMCR); 412 context->advertise = phy_read(phydev, MII_ADVERTISE); 413 context->control1000 = phy_read(phydev, MII_CTRL1000); 414 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 415 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 416 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 417 } 418 419 /* restore relevant PHY registers from private copy */ 420 static void at803x_context_restore(struct phy_device *phydev, 421 const struct at803x_context *context) 422 { 423 phy_write(phydev, MII_BMCR, context->bmcr); 424 phy_write(phydev, MII_ADVERTISE, context->advertise); 425 phy_write(phydev, MII_CTRL1000, context->control1000); 426 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 427 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 428 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 429 } 430 431 static int at803x_set_wol(struct phy_device *phydev, 432 struct ethtool_wolinfo *wol) 433 { 434 struct net_device *ndev = phydev->attached_dev; 435 const u8 *mac; 436 int ret, irq_enabled; 437 unsigned int i; 438 static const unsigned int offsets[] = { 439 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 440 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 441 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 442 }; 443 444 if (!ndev) 445 return -ENODEV; 446 447 if (wol->wolopts & WAKE_MAGIC) { 448 mac = (const u8 *) ndev->dev_addr; 449 450 if (!is_valid_ether_addr(mac)) 451 return -EINVAL; 452 453 for (i = 0; i < 3; i++) 454 phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 455 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 456 457 /* Enable WOL function */ 458 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 459 0, AT803X_WOL_EN); 460 if (ret) 461 return ret; 462 /* Enable WOL interrupt */ 463 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 464 if (ret) 465 return ret; 466 } else { 467 /* Disable WoL function */ 468 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 469 AT803X_WOL_EN, 0); 470 if (ret) 471 return ret; 472 /* Disable WOL interrupt */ 473 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 474 if (ret) 475 return ret; 476 } 477 478 /* Clear WOL status */ 479 ret = phy_read(phydev, AT803X_INTR_STATUS); 480 if (ret < 0) 481 return ret; 482 483 /* Check if there are other interrupts except for WOL triggered when PHY is 484 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 485 * be passed up to the interrupt PIN. 486 */ 487 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 488 if (irq_enabled < 0) 489 return irq_enabled; 490 491 irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 492 if (ret & irq_enabled && !phy_polling_mode(phydev)) 493 phy_trigger_machine(phydev); 494 495 return 0; 496 } 497 498 static void at803x_get_wol(struct phy_device *phydev, 499 struct ethtool_wolinfo *wol) 500 { 501 int value; 502 503 wol->supported = WAKE_MAGIC; 504 wol->wolopts = 0; 505 506 value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 507 if (value < 0) 508 return; 509 510 if (value & AT803X_WOL_EN) 511 wol->wolopts |= WAKE_MAGIC; 512 } 513 514 static int at803x_get_sset_count(struct phy_device *phydev) 515 { 516 return ARRAY_SIZE(at803x_hw_stats); 517 } 518 519 static void at803x_get_strings(struct phy_device *phydev, u8 *data) 520 { 521 int i; 522 523 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 524 strscpy(data + i * ETH_GSTRING_LEN, 525 at803x_hw_stats[i].string, ETH_GSTRING_LEN); 526 } 527 } 528 529 static u64 at803x_get_stat(struct phy_device *phydev, int i) 530 { 531 struct at803x_hw_stat stat = at803x_hw_stats[i]; 532 struct at803x_priv *priv = phydev->priv; 533 int val; 534 u64 ret; 535 536 if (stat.access_type == MMD) 537 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 538 else 539 val = phy_read(phydev, stat.reg); 540 541 if (val < 0) { 542 ret = U64_MAX; 543 } else { 544 val = val & stat.mask; 545 priv->stats[i] += val; 546 ret = priv->stats[i]; 547 } 548 549 return ret; 550 } 551 552 static void at803x_get_stats(struct phy_device *phydev, 553 struct ethtool_stats *stats, u64 *data) 554 { 555 int i; 556 557 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 558 data[i] = at803x_get_stat(phydev, i); 559 } 560 561 static int at803x_suspend(struct phy_device *phydev) 562 { 563 int value; 564 int wol_enabled; 565 566 value = phy_read(phydev, AT803X_INTR_ENABLE); 567 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 568 569 if (wol_enabled) 570 value = BMCR_ISOLATE; 571 else 572 value = BMCR_PDOWN; 573 574 phy_modify(phydev, MII_BMCR, 0, value); 575 576 return 0; 577 } 578 579 static int at803x_resume(struct phy_device *phydev) 580 { 581 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 582 } 583 584 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 585 unsigned int selector) 586 { 587 struct phy_device *phydev = rdev_get_drvdata(rdev); 588 589 if (selector) 590 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 591 0, AT803X_DEBUG_RGMII_1V8); 592 else 593 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 594 AT803X_DEBUG_RGMII_1V8, 0); 595 } 596 597 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 598 { 599 struct phy_device *phydev = rdev_get_drvdata(rdev); 600 int val; 601 602 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 603 if (val < 0) 604 return val; 605 606 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 607 } 608 609 static const struct regulator_ops vddio_regulator_ops = { 610 .list_voltage = regulator_list_voltage_table, 611 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 612 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 613 }; 614 615 static const unsigned int vddio_voltage_table[] = { 616 1500000, 617 1800000, 618 }; 619 620 static const struct regulator_desc vddio_desc = { 621 .name = "vddio", 622 .of_match = of_match_ptr("vddio-regulator"), 623 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 624 .volt_table = vddio_voltage_table, 625 .ops = &vddio_regulator_ops, 626 .type = REGULATOR_VOLTAGE, 627 .owner = THIS_MODULE, 628 }; 629 630 static const struct regulator_ops vddh_regulator_ops = { 631 }; 632 633 static const struct regulator_desc vddh_desc = { 634 .name = "vddh", 635 .of_match = of_match_ptr("vddh-regulator"), 636 .n_voltages = 1, 637 .fixed_uV = 2500000, 638 .ops = &vddh_regulator_ops, 639 .type = REGULATOR_VOLTAGE, 640 .owner = THIS_MODULE, 641 }; 642 643 static int at8031_register_regulators(struct phy_device *phydev) 644 { 645 struct at803x_priv *priv = phydev->priv; 646 struct device *dev = &phydev->mdio.dev; 647 struct regulator_config config = { }; 648 649 config.dev = dev; 650 config.driver_data = phydev; 651 652 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 653 if (IS_ERR(priv->vddio_rdev)) { 654 phydev_err(phydev, "failed to register VDDIO regulator\n"); 655 return PTR_ERR(priv->vddio_rdev); 656 } 657 658 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 659 if (IS_ERR(priv->vddh_rdev)) { 660 phydev_err(phydev, "failed to register VDDH regulator\n"); 661 return PTR_ERR(priv->vddh_rdev); 662 } 663 664 return 0; 665 } 666 667 static int at803x_parse_dt(struct phy_device *phydev) 668 { 669 struct device_node *node = phydev->mdio.dev.of_node; 670 struct at803x_priv *priv = phydev->priv; 671 u32 freq, strength, tw; 672 unsigned int sel; 673 int ret; 674 675 if (!IS_ENABLED(CONFIG_OF_MDIO)) 676 return 0; 677 678 if (of_property_read_bool(node, "qca,disable-smarteee")) 679 priv->flags |= AT803X_DISABLE_SMARTEEE; 680 681 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 682 if (!tw || tw > 255) { 683 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 684 return -EINVAL; 685 } 686 priv->smarteee_lpi_tw_1g = tw; 687 } 688 689 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 690 if (!tw || tw > 255) { 691 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 692 return -EINVAL; 693 } 694 priv->smarteee_lpi_tw_100m = tw; 695 } 696 697 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 698 if (!ret) { 699 switch (freq) { 700 case 25000000: 701 sel = AT803X_CLK_OUT_25MHZ_XTAL; 702 break; 703 case 50000000: 704 sel = AT803X_CLK_OUT_50MHZ_PLL; 705 break; 706 case 62500000: 707 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 708 break; 709 case 125000000: 710 sel = AT803X_CLK_OUT_125MHZ_PLL; 711 break; 712 default: 713 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 714 return -EINVAL; 715 } 716 717 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 718 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 719 720 /* Fixup for the AR8030/AR8035. This chip has another mask and 721 * doesn't support the DSP reference. Eg. the lowest bit of the 722 * mask. The upper two bits select the same frequencies. Mask 723 * the lowest bit here. 724 * 725 * Warning: 726 * There was no datasheet for the AR8030 available so this is 727 * just a guess. But the AR8035 is listed as pin compatible 728 * to the AR8030 so there might be a good chance it works on 729 * the AR8030 too. 730 */ 731 if (phydev->drv->phy_id == ATH8030_PHY_ID || 732 phydev->drv->phy_id == ATH8035_PHY_ID) { 733 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 734 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 735 } 736 } 737 738 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 739 if (!ret) { 740 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 741 switch (strength) { 742 case AR803X_STRENGTH_FULL: 743 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 744 break; 745 case AR803X_STRENGTH_HALF: 746 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 747 break; 748 case AR803X_STRENGTH_QUARTER: 749 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 750 break; 751 default: 752 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 753 return -EINVAL; 754 } 755 } 756 757 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 758 * options. 759 */ 760 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 761 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 762 priv->flags |= AT803X_KEEP_PLL_ENABLED; 763 764 ret = at8031_register_regulators(phydev); 765 if (ret < 0) 766 return ret; 767 768 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 769 "vddio"); 770 if (IS_ERR(priv->vddio)) { 771 phydev_err(phydev, "failed to get VDDIO regulator\n"); 772 return PTR_ERR(priv->vddio); 773 } 774 } 775 776 return 0; 777 } 778 779 static int at803x_probe(struct phy_device *phydev) 780 { 781 struct device *dev = &phydev->mdio.dev; 782 struct at803x_priv *priv; 783 int ret; 784 785 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 786 if (!priv) 787 return -ENOMEM; 788 789 phydev->priv = priv; 790 791 ret = at803x_parse_dt(phydev); 792 if (ret) 793 return ret; 794 795 if (priv->vddio) { 796 ret = regulator_enable(priv->vddio); 797 if (ret < 0) 798 return ret; 799 } 800 801 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 802 int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 803 int mode_cfg; 804 805 if (ccr < 0) 806 goto err; 807 mode_cfg = ccr & AT803X_MODE_CFG_MASK; 808 809 switch (mode_cfg) { 810 case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 811 case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 812 priv->is_1000basex = true; 813 fallthrough; 814 case AT803X_MODE_CFG_FX100_RGMII_50OHM: 815 case AT803X_MODE_CFG_FX100_RGMII_75OHM: 816 priv->is_fiber = true; 817 break; 818 } 819 } 820 821 return 0; 822 823 err: 824 if (priv->vddio) 825 regulator_disable(priv->vddio); 826 827 return ret; 828 } 829 830 static void at803x_remove(struct phy_device *phydev) 831 { 832 struct at803x_priv *priv = phydev->priv; 833 834 if (priv->vddio) 835 regulator_disable(priv->vddio); 836 } 837 838 static int at803x_get_features(struct phy_device *phydev) 839 { 840 struct at803x_priv *priv = phydev->priv; 841 int err; 842 843 err = genphy_read_abilities(phydev); 844 if (err) 845 return err; 846 847 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 848 err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); 849 if (err < 0) 850 return err; 851 852 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 853 err & MDIO_PMA_NG_EXTABLE_2_5GBT); 854 } 855 856 if (phydev->drv->phy_id != ATH8031_PHY_ID) 857 return 0; 858 859 /* AR8031/AR8033 have different status registers 860 * for copper and fiber operation. However, the 861 * extended status register is the same for both 862 * operation modes. 863 * 864 * As a result of that, ESTATUS_1000_XFULL is set 865 * to 1 even when operating in copper TP mode. 866 * 867 * Remove this mode from the supported link modes 868 * when not operating in 1000BaseX mode. 869 */ 870 if (!priv->is_1000basex) 871 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 872 phydev->supported); 873 874 return 0; 875 } 876 877 static int at803x_smarteee_config(struct phy_device *phydev) 878 { 879 struct at803x_priv *priv = phydev->priv; 880 u16 mask = 0, val = 0; 881 int ret; 882 883 if (priv->flags & AT803X_DISABLE_SMARTEEE) 884 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 885 AT803X_MMD3_SMARTEEE_CTL3, 886 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 887 888 if (priv->smarteee_lpi_tw_1g) { 889 mask |= 0xff00; 890 val |= priv->smarteee_lpi_tw_1g << 8; 891 } 892 if (priv->smarteee_lpi_tw_100m) { 893 mask |= 0x00ff; 894 val |= priv->smarteee_lpi_tw_100m; 895 } 896 if (!mask) 897 return 0; 898 899 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 900 mask, val); 901 if (ret) 902 return ret; 903 904 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 905 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 906 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 907 } 908 909 static int at803x_clk_out_config(struct phy_device *phydev) 910 { 911 struct at803x_priv *priv = phydev->priv; 912 913 if (!priv->clk_25m_mask) 914 return 0; 915 916 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 917 priv->clk_25m_mask, priv->clk_25m_reg); 918 } 919 920 static int at8031_pll_config(struct phy_device *phydev) 921 { 922 struct at803x_priv *priv = phydev->priv; 923 924 /* The default after hardware reset is PLL OFF. After a soft reset, the 925 * values are retained. 926 */ 927 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 928 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 929 0, AT803X_DEBUG_PLL_ON); 930 else 931 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 932 AT803X_DEBUG_PLL_ON, 0); 933 } 934 935 static int at803x_config_init(struct phy_device *phydev) 936 { 937 struct at803x_priv *priv = phydev->priv; 938 int ret; 939 940 if (phydev->drv->phy_id == ATH8031_PHY_ID) { 941 /* Some bootloaders leave the fiber page selected. 942 * Switch to the appropriate page (fiber or copper), as otherwise we 943 * read the PHY capabilities from the wrong page. 944 */ 945 phy_lock_mdio_bus(phydev); 946 ret = at803x_write_page(phydev, 947 priv->is_fiber ? AT803X_PAGE_FIBER : 948 AT803X_PAGE_COPPER); 949 phy_unlock_mdio_bus(phydev); 950 if (ret) 951 return ret; 952 953 ret = at8031_pll_config(phydev); 954 if (ret < 0) 955 return ret; 956 } 957 958 /* The RX and TX delay default is: 959 * after HW reset: RX delay enabled and TX delay disabled 960 * after SW reset: RX delay enabled, while TX delay retains the 961 * value before reset. 962 */ 963 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 964 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 965 ret = at803x_enable_rx_delay(phydev); 966 else 967 ret = at803x_disable_rx_delay(phydev); 968 if (ret < 0) 969 return ret; 970 971 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 972 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 973 ret = at803x_enable_tx_delay(phydev); 974 else 975 ret = at803x_disable_tx_delay(phydev); 976 if (ret < 0) 977 return ret; 978 979 ret = at803x_smarteee_config(phydev); 980 if (ret < 0) 981 return ret; 982 983 ret = at803x_clk_out_config(phydev); 984 if (ret < 0) 985 return ret; 986 987 /* Ar803x extended next page bit is enabled by default. Cisco 988 * multigig switches read this bit and attempt to negotiate 10Gbps 989 * rates even if the next page bit is disabled. This is incorrect 990 * behaviour but we still need to accommodate it. XNP is only needed 991 * for 10Gbps support, so disable XNP. 992 */ 993 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 994 } 995 996 static int at803x_ack_interrupt(struct phy_device *phydev) 997 { 998 int err; 999 1000 err = phy_read(phydev, AT803X_INTR_STATUS); 1001 1002 return (err < 0) ? err : 0; 1003 } 1004 1005 static int at803x_config_intr(struct phy_device *phydev) 1006 { 1007 struct at803x_priv *priv = phydev->priv; 1008 int err; 1009 int value; 1010 1011 value = phy_read(phydev, AT803X_INTR_ENABLE); 1012 1013 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1014 /* Clear any pending interrupts */ 1015 err = at803x_ack_interrupt(phydev); 1016 if (err) 1017 return err; 1018 1019 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 1020 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 1021 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 1022 value |= AT803X_INTR_ENABLE_LINK_FAIL; 1023 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 1024 if (priv->is_fiber) { 1025 value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 1026 value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 1027 } 1028 1029 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 1030 } else { 1031 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 1032 if (err) 1033 return err; 1034 1035 /* Clear any pending interrupts */ 1036 err = at803x_ack_interrupt(phydev); 1037 } 1038 1039 return err; 1040 } 1041 1042 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 1043 { 1044 int irq_status, int_enabled; 1045 1046 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 1047 if (irq_status < 0) { 1048 phy_error(phydev); 1049 return IRQ_NONE; 1050 } 1051 1052 /* Read the current enabled interrupts */ 1053 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 1054 if (int_enabled < 0) { 1055 phy_error(phydev); 1056 return IRQ_NONE; 1057 } 1058 1059 /* See if this was one of our enabled interrupts */ 1060 if (!(irq_status & int_enabled)) 1061 return IRQ_NONE; 1062 1063 phy_trigger_machine(phydev); 1064 1065 return IRQ_HANDLED; 1066 } 1067 1068 static void at803x_link_change_notify(struct phy_device *phydev) 1069 { 1070 /* 1071 * Conduct a hardware reset for AT8030 every time a link loss is 1072 * signalled. This is necessary to circumvent a hardware bug that 1073 * occurs when the cable is unplugged while TX packets are pending 1074 * in the FIFO. In such cases, the FIFO enters an error mode it 1075 * cannot recover from by software. 1076 */ 1077 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 1078 struct at803x_context context; 1079 1080 at803x_context_save(phydev, &context); 1081 1082 phy_device_reset(phydev, 1); 1083 msleep(1); 1084 phy_device_reset(phydev, 0); 1085 msleep(1); 1086 1087 at803x_context_restore(phydev, &context); 1088 1089 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 1090 } 1091 } 1092 1093 static int at803x_read_specific_status(struct phy_device *phydev) 1094 { 1095 int ss; 1096 1097 /* Read the AT8035 PHY-Specific Status register, which indicates the 1098 * speed and duplex that the PHY is actually using, irrespective of 1099 * whether we are in autoneg mode or not. 1100 */ 1101 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 1102 if (ss < 0) 1103 return ss; 1104 1105 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 1106 int sfc, speed; 1107 1108 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 1109 if (sfc < 0) 1110 return sfc; 1111 1112 /* qca8081 takes the different bits for speed value from at803x */ 1113 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1114 speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 1115 else 1116 speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 1117 1118 switch (speed) { 1119 case AT803X_SS_SPEED_10: 1120 phydev->speed = SPEED_10; 1121 break; 1122 case AT803X_SS_SPEED_100: 1123 phydev->speed = SPEED_100; 1124 break; 1125 case AT803X_SS_SPEED_1000: 1126 phydev->speed = SPEED_1000; 1127 break; 1128 case QCA808X_SS_SPEED_2500: 1129 phydev->speed = SPEED_2500; 1130 break; 1131 } 1132 if (ss & AT803X_SS_DUPLEX) 1133 phydev->duplex = DUPLEX_FULL; 1134 else 1135 phydev->duplex = DUPLEX_HALF; 1136 1137 if (ss & AT803X_SS_MDIX) 1138 phydev->mdix = ETH_TP_MDI_X; 1139 else 1140 phydev->mdix = ETH_TP_MDI; 1141 1142 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 1143 case AT803X_SFC_MANUAL_MDI: 1144 phydev->mdix_ctrl = ETH_TP_MDI; 1145 break; 1146 case AT803X_SFC_MANUAL_MDIX: 1147 phydev->mdix_ctrl = ETH_TP_MDI_X; 1148 break; 1149 case AT803X_SFC_AUTOMATIC_CROSSOVER: 1150 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1151 break; 1152 } 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int at803x_read_status(struct phy_device *phydev) 1159 { 1160 struct at803x_priv *priv = phydev->priv; 1161 int err, old_link = phydev->link; 1162 1163 if (priv->is_1000basex) 1164 return genphy_c37_read_status(phydev); 1165 1166 /* Update the link, but return if there was an error */ 1167 err = genphy_update_link(phydev); 1168 if (err) 1169 return err; 1170 1171 /* why bother the PHY if nothing can have changed */ 1172 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 1173 return 0; 1174 1175 phydev->speed = SPEED_UNKNOWN; 1176 phydev->duplex = DUPLEX_UNKNOWN; 1177 phydev->pause = 0; 1178 phydev->asym_pause = 0; 1179 1180 err = genphy_read_lpa(phydev); 1181 if (err < 0) 1182 return err; 1183 1184 err = at803x_read_specific_status(phydev); 1185 if (err < 0) 1186 return err; 1187 1188 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 1189 phy_resolve_aneg_pause(phydev); 1190 1191 return 0; 1192 } 1193 1194 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 1195 { 1196 u16 val; 1197 1198 switch (ctrl) { 1199 case ETH_TP_MDI: 1200 val = AT803X_SFC_MANUAL_MDI; 1201 break; 1202 case ETH_TP_MDI_X: 1203 val = AT803X_SFC_MANUAL_MDIX; 1204 break; 1205 case ETH_TP_MDI_AUTO: 1206 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 1207 break; 1208 default: 1209 return 0; 1210 } 1211 1212 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 1213 AT803X_SFC_MDI_CROSSOVER_MODE_M, 1214 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 1215 } 1216 1217 static int at803x_config_aneg(struct phy_device *phydev) 1218 { 1219 struct at803x_priv *priv = phydev->priv; 1220 int ret; 1221 1222 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 1223 if (ret < 0) 1224 return ret; 1225 1226 /* Changes of the midx bits are disruptive to the normal operation; 1227 * therefore any changes to these registers must be followed by a 1228 * software reset to take effect. 1229 */ 1230 if (ret == 1) { 1231 ret = genphy_soft_reset(phydev); 1232 if (ret < 0) 1233 return ret; 1234 } 1235 1236 if (priv->is_1000basex) 1237 return genphy_c37_config_aneg(phydev); 1238 1239 /* Do not restart auto-negotiation by setting ret to 0 defautly, 1240 * when calling __genphy_config_aneg later. 1241 */ 1242 ret = 0; 1243 1244 if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1245 int phy_ctrl = 0; 1246 1247 /* The reg MII_BMCR also needs to be configured for force mode, the 1248 * genphy_config_aneg is also needed. 1249 */ 1250 if (phydev->autoneg == AUTONEG_DISABLE) 1251 genphy_c45_pma_setup_forced(phydev); 1252 1253 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1254 phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1255 1256 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1257 MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1258 if (ret < 0) 1259 return ret; 1260 } 1261 1262 return __genphy_config_aneg(phydev, ret); 1263 } 1264 1265 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1266 { 1267 int val; 1268 1269 val = phy_read(phydev, AT803X_SMART_SPEED); 1270 if (val < 0) 1271 return val; 1272 1273 if (val & AT803X_SMART_SPEED_ENABLE) 1274 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1275 else 1276 *d = DOWNSHIFT_DEV_DISABLE; 1277 1278 return 0; 1279 } 1280 1281 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1282 { 1283 u16 mask, set; 1284 int ret; 1285 1286 switch (cnt) { 1287 case DOWNSHIFT_DEV_DEFAULT_COUNT: 1288 cnt = AT803X_DEFAULT_DOWNSHIFT; 1289 fallthrough; 1290 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1291 set = AT803X_SMART_SPEED_ENABLE | 1292 AT803X_SMART_SPEED_BYPASS_TIMER | 1293 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1294 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1295 break; 1296 case DOWNSHIFT_DEV_DISABLE: 1297 set = 0; 1298 mask = AT803X_SMART_SPEED_ENABLE | 1299 AT803X_SMART_SPEED_BYPASS_TIMER; 1300 break; 1301 default: 1302 return -EINVAL; 1303 } 1304 1305 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1306 1307 /* After changing the smart speed settings, we need to perform a 1308 * software reset, use phy_init_hw() to make sure we set the 1309 * reapply any values which might got lost during software reset. 1310 */ 1311 if (ret == 1) 1312 ret = phy_init_hw(phydev); 1313 1314 return ret; 1315 } 1316 1317 static int at803x_get_tunable(struct phy_device *phydev, 1318 struct ethtool_tunable *tuna, void *data) 1319 { 1320 switch (tuna->id) { 1321 case ETHTOOL_PHY_DOWNSHIFT: 1322 return at803x_get_downshift(phydev, data); 1323 default: 1324 return -EOPNOTSUPP; 1325 } 1326 } 1327 1328 static int at803x_set_tunable(struct phy_device *phydev, 1329 struct ethtool_tunable *tuna, const void *data) 1330 { 1331 switch (tuna->id) { 1332 case ETHTOOL_PHY_DOWNSHIFT: 1333 return at803x_set_downshift(phydev, *(const u8 *)data); 1334 default: 1335 return -EOPNOTSUPP; 1336 } 1337 } 1338 1339 static int at803x_cable_test_result_trans(u16 status) 1340 { 1341 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1342 case AT803X_CDT_STATUS_STAT_NORMAL: 1343 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1344 case AT803X_CDT_STATUS_STAT_SHORT: 1345 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1346 case AT803X_CDT_STATUS_STAT_OPEN: 1347 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1348 case AT803X_CDT_STATUS_STAT_FAIL: 1349 default: 1350 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1351 } 1352 } 1353 1354 static bool at803x_cdt_test_failed(u16 status) 1355 { 1356 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1357 AT803X_CDT_STATUS_STAT_FAIL; 1358 } 1359 1360 static bool at803x_cdt_fault_length_valid(u16 status) 1361 { 1362 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1363 case AT803X_CDT_STATUS_STAT_OPEN: 1364 case AT803X_CDT_STATUS_STAT_SHORT: 1365 return true; 1366 } 1367 return false; 1368 } 1369 1370 static int at803x_cdt_fault_length(u16 status) 1371 { 1372 int dt; 1373 1374 /* According to the datasheet the distance to the fault is 1375 * DELTA_TIME * 0.824 meters. 1376 * 1377 * The author suspect the correct formula is: 1378 * 1379 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1380 * 1381 * where c is the speed of light, VF is the velocity factor of 1382 * the twisted pair cable, 125MHz the counter frequency and 1383 * we need to divide by 2 because the hardware will measure the 1384 * round trip time to the fault and back to the PHY. 1385 * 1386 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1387 * datasheet. 1388 */ 1389 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1390 1391 return (dt * 824) / 10; 1392 } 1393 1394 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1395 { 1396 u16 cdt; 1397 1398 /* qca8081 takes the different bit 15 to enable CDT test */ 1399 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1400 cdt = QCA808X_CDT_ENABLE_TEST | 1401 QCA808X_CDT_LENGTH_UNIT | 1402 QCA808X_CDT_INTER_CHECK_DIS; 1403 else 1404 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1405 AT803X_CDT_ENABLE_TEST; 1406 1407 return phy_write(phydev, AT803X_CDT, cdt); 1408 } 1409 1410 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1411 { 1412 int val, ret; 1413 u16 cdt_en; 1414 1415 if (phydev->drv->phy_id == QCA8081_PHY_ID) 1416 cdt_en = QCA808X_CDT_ENABLE_TEST; 1417 else 1418 cdt_en = AT803X_CDT_ENABLE_TEST; 1419 1420 /* One test run takes about 25ms */ 1421 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1422 !(val & cdt_en), 1423 30000, 100000, true); 1424 1425 return ret < 0 ? ret : 0; 1426 } 1427 1428 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1429 { 1430 static const int ethtool_pair[] = { 1431 ETHTOOL_A_CABLE_PAIR_A, 1432 ETHTOOL_A_CABLE_PAIR_B, 1433 ETHTOOL_A_CABLE_PAIR_C, 1434 ETHTOOL_A_CABLE_PAIR_D, 1435 }; 1436 int ret, val; 1437 1438 ret = at803x_cdt_start(phydev, pair); 1439 if (ret) 1440 return ret; 1441 1442 ret = at803x_cdt_wait_for_completion(phydev); 1443 if (ret) 1444 return ret; 1445 1446 val = phy_read(phydev, AT803X_CDT_STATUS); 1447 if (val < 0) 1448 return val; 1449 1450 if (at803x_cdt_test_failed(val)) 1451 return 0; 1452 1453 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1454 at803x_cable_test_result_trans(val)); 1455 1456 if (at803x_cdt_fault_length_valid(val)) 1457 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1458 at803x_cdt_fault_length(val)); 1459 1460 return 1; 1461 } 1462 1463 static int at803x_cable_test_get_status(struct phy_device *phydev, 1464 bool *finished) 1465 { 1466 unsigned long pair_mask; 1467 int retries = 20; 1468 int pair, ret; 1469 1470 if (phydev->phy_id == ATH9331_PHY_ID || 1471 phydev->phy_id == ATH8032_PHY_ID || 1472 phydev->phy_id == QCA9561_PHY_ID) 1473 pair_mask = 0x3; 1474 else 1475 pair_mask = 0xf; 1476 1477 *finished = false; 1478 1479 /* According to the datasheet the CDT can be performed when 1480 * there is no link partner or when the link partner is 1481 * auto-negotiating. Starting the test will restart the AN 1482 * automatically. It seems that doing this repeatedly we will 1483 * get a slot where our link partner won't disturb our 1484 * measurement. 1485 */ 1486 while (pair_mask && retries--) { 1487 for_each_set_bit(pair, &pair_mask, 4) { 1488 ret = at803x_cable_test_one_pair(phydev, pair); 1489 if (ret < 0) 1490 return ret; 1491 if (ret) 1492 clear_bit(pair, &pair_mask); 1493 } 1494 if (pair_mask) 1495 msleep(250); 1496 } 1497 1498 *finished = true; 1499 1500 return 0; 1501 } 1502 1503 static int at803x_cable_test_start(struct phy_device *phydev) 1504 { 1505 /* Enable auto-negotiation, but advertise no capabilities, no link 1506 * will be established. A restart of the auto-negotiation is not 1507 * required, because the cable test will automatically break the link. 1508 */ 1509 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1510 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1511 if (phydev->phy_id != ATH9331_PHY_ID && 1512 phydev->phy_id != ATH8032_PHY_ID && 1513 phydev->phy_id != QCA9561_PHY_ID) 1514 phy_write(phydev, MII_CTRL1000, 0); 1515 1516 /* we do all the (time consuming) work later */ 1517 return 0; 1518 } 1519 1520 static int qca83xx_config_init(struct phy_device *phydev) 1521 { 1522 u8 switch_revision; 1523 1524 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1525 1526 switch (switch_revision) { 1527 case 1: 1528 /* For 100M waveform */ 1529 at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1530 /* Turn on Gigabit clock */ 1531 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1532 break; 1533 1534 case 2: 1535 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1536 fallthrough; 1537 case 4: 1538 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 1539 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 1540 at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1541 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1542 break; 1543 } 1544 1545 /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 1546 * Disable on init and enable only with 100m speed following 1547 * qca original source code. 1548 */ 1549 if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 1550 phydev->drv->phy_id == QCA8327_B_PHY_ID) 1551 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1552 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1553 1554 /* Following original QCA sourcecode set port to prefer master */ 1555 phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 1556 1557 return 0; 1558 } 1559 1560 static void qca83xx_link_change_notify(struct phy_device *phydev) 1561 { 1562 /* QCA8337 doesn't require DAC Amplitude adjustement */ 1563 if (phydev->drv->phy_id == QCA8337_PHY_ID) 1564 return; 1565 1566 /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 1567 if (phydev->state == PHY_RUNNING) { 1568 if (phydev->speed == SPEED_100) 1569 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1570 QCA8327_DEBUG_MANU_CTRL_EN, 1571 QCA8327_DEBUG_MANU_CTRL_EN); 1572 } else { 1573 /* Reset DAC Amplitude adjustment */ 1574 at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 1575 QCA8327_DEBUG_MANU_CTRL_EN, 0); 1576 } 1577 } 1578 1579 static int qca83xx_resume(struct phy_device *phydev) 1580 { 1581 int ret, val; 1582 1583 /* Skip reset if not suspended */ 1584 if (!phydev->suspended) 1585 return 0; 1586 1587 /* Reinit the port, reset values set by suspend */ 1588 qca83xx_config_init(phydev); 1589 1590 /* Reset the port on port resume */ 1591 phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1592 1593 /* On resume from suspend the switch execute a reset and 1594 * restart auto-negotiation. Wait for reset to complete. 1595 */ 1596 ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1597 50000, 600000, true); 1598 if (ret) 1599 return ret; 1600 1601 msleep(1); 1602 1603 return 0; 1604 } 1605 1606 static int qca83xx_suspend(struct phy_device *phydev) 1607 { 1608 u16 mask = 0; 1609 1610 /* Only QCA8337 support actual suspend. 1611 * QCA8327 cause port unreliability when phy suspend 1612 * is set. 1613 */ 1614 if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1615 genphy_suspend(phydev); 1616 } else { 1617 mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1618 phy_modify(phydev, MII_BMCR, mask, 0); 1619 } 1620 1621 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1622 AT803X_DEBUG_GATE_CLK_IN1000, 0); 1623 1624 at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1625 AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1626 AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1627 1628 return 0; 1629 } 1630 1631 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 1632 { 1633 int ret; 1634 1635 /* Enable fast retrain */ 1636 ret = genphy_c45_fast_retrain(phydev, true); 1637 if (ret) 1638 return ret; 1639 1640 phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 1641 QCA808X_TOP_OPTION1_DATA); 1642 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 1643 QCA808X_MSE_THRESHOLD_20DB_VALUE); 1644 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 1645 QCA808X_MSE_THRESHOLD_17DB_VALUE); 1646 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 1647 QCA808X_MSE_THRESHOLD_27DB_VALUE); 1648 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 1649 QCA808X_MSE_THRESHOLD_28DB_VALUE); 1650 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 1651 QCA808X_MMD3_DEBUG_1_VALUE); 1652 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 1653 QCA808X_MMD3_DEBUG_4_VALUE); 1654 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 1655 QCA808X_MMD3_DEBUG_5_VALUE); 1656 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 1657 QCA808X_MMD3_DEBUG_3_VALUE); 1658 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 1659 QCA808X_MMD3_DEBUG_6_VALUE); 1660 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 1661 QCA808X_MMD3_DEBUG_2_VALUE); 1662 1663 return 0; 1664 } 1665 1666 static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) 1667 { 1668 u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE); 1669 1670 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1671 QCA808X_MASTER_SLAVE_SEED_CFG, 1672 FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); 1673 } 1674 1675 static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 1676 { 1677 u16 seed_enable = 0; 1678 1679 if (enable) 1680 seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; 1681 1682 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 1683 QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); 1684 } 1685 1686 static int qca808x_config_init(struct phy_device *phydev) 1687 { 1688 int ret; 1689 1690 /* Active adc&vga on 802.3az for the link 1000M and 100M */ 1691 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 1692 QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 1693 if (ret) 1694 return ret; 1695 1696 /* Adjust the threshold on 802.3az for the link 1000M */ 1697 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 1698 QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 1699 if (ret) 1700 return ret; 1701 1702 /* Config the fast retrain for the link 2500M */ 1703 ret = qca808x_phy_fast_retrain_config(phydev); 1704 if (ret) 1705 return ret; 1706 1707 /* Configure lower ramdom seed to make phy linked as slave mode */ 1708 ret = qca808x_phy_ms_random_seed_set(phydev); 1709 if (ret) 1710 return ret; 1711 1712 /* Enable seed */ 1713 ret = qca808x_phy_ms_seed_enable(phydev, true); 1714 if (ret) 1715 return ret; 1716 1717 /* Configure adc threshold as 100mv for the link 10M */ 1718 return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 1719 QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 1720 } 1721 1722 static int qca808x_read_status(struct phy_device *phydev) 1723 { 1724 int ret; 1725 1726 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1727 if (ret < 0) 1728 return ret; 1729 1730 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 1731 ret & MDIO_AN_10GBT_STAT_LP2_5G); 1732 1733 ret = genphy_read_status(phydev); 1734 if (ret) 1735 return ret; 1736 1737 ret = at803x_read_specific_status(phydev); 1738 if (ret < 0) 1739 return ret; 1740 1741 if (phydev->link && phydev->speed == SPEED_2500) 1742 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1743 else 1744 phydev->interface = PHY_INTERFACE_MODE_SMII; 1745 1746 /* generate seed as a lower random value to make PHY linked as SLAVE easily, 1747 * except for master/slave configuration fault detected. 1748 * the reason for not putting this code into the function link_change_notify is 1749 * the corner case where the link partner is also the qca8081 PHY and the seed 1750 * value is configured as the same value, the link can't be up and no link change 1751 * occurs. 1752 */ 1753 if (!phydev->link) { 1754 if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { 1755 qca808x_phy_ms_seed_enable(phydev, false); 1756 } else { 1757 qca808x_phy_ms_random_seed_set(phydev); 1758 qca808x_phy_ms_seed_enable(phydev, true); 1759 } 1760 } 1761 1762 return 0; 1763 } 1764 1765 static int qca808x_soft_reset(struct phy_device *phydev) 1766 { 1767 int ret; 1768 1769 ret = genphy_soft_reset(phydev); 1770 if (ret < 0) 1771 return ret; 1772 1773 return qca808x_phy_ms_seed_enable(phydev, true); 1774 } 1775 1776 static bool qca808x_cdt_fault_length_valid(int cdt_code) 1777 { 1778 switch (cdt_code) { 1779 case QCA808X_CDT_STATUS_STAT_SHORT: 1780 case QCA808X_CDT_STATUS_STAT_OPEN: 1781 return true; 1782 default: 1783 return false; 1784 } 1785 } 1786 1787 static int qca808x_cable_test_result_trans(int cdt_code) 1788 { 1789 switch (cdt_code) { 1790 case QCA808X_CDT_STATUS_STAT_NORMAL: 1791 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1792 case QCA808X_CDT_STATUS_STAT_SHORT: 1793 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1794 case QCA808X_CDT_STATUS_STAT_OPEN: 1795 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1796 case QCA808X_CDT_STATUS_STAT_FAIL: 1797 default: 1798 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1799 } 1800 } 1801 1802 static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 1803 { 1804 int val; 1805 u32 cdt_length_reg = 0; 1806 1807 switch (pair) { 1808 case ETHTOOL_A_CABLE_PAIR_A: 1809 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 1810 break; 1811 case ETHTOOL_A_CABLE_PAIR_B: 1812 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 1813 break; 1814 case ETHTOOL_A_CABLE_PAIR_C: 1815 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 1816 break; 1817 case ETHTOOL_A_CABLE_PAIR_D: 1818 cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 1819 break; 1820 default: 1821 return -EINVAL; 1822 } 1823 1824 val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 1825 if (val < 0) 1826 return val; 1827 1828 return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 1829 } 1830 1831 static int qca808x_cable_test_start(struct phy_device *phydev) 1832 { 1833 int ret; 1834 1835 /* perform CDT with the following configs: 1836 * 1. disable hibernation. 1837 * 2. force PHY working in MDI mode. 1838 * 3. for PHY working in 1000BaseT. 1839 * 4. configure the threshold. 1840 */ 1841 1842 ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 1843 if (ret < 0) 1844 return ret; 1845 1846 ret = at803x_config_mdix(phydev, ETH_TP_MDI); 1847 if (ret < 0) 1848 return ret; 1849 1850 /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 1851 phydev->duplex = DUPLEX_FULL; 1852 phydev->speed = SPEED_1000; 1853 ret = genphy_c45_pma_setup_forced(phydev); 1854 if (ret < 0) 1855 return ret; 1856 1857 ret = genphy_setup_forced(phydev); 1858 if (ret < 0) 1859 return ret; 1860 1861 /* configure the thresholds for open, short, pair ok test */ 1862 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 1863 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 1864 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 1865 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 1866 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 1867 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 1868 1869 return 0; 1870 } 1871 1872 static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 1873 { 1874 int ret, val; 1875 int pair_a, pair_b, pair_c, pair_d; 1876 1877 *finished = false; 1878 1879 ret = at803x_cdt_start(phydev, 0); 1880 if (ret) 1881 return ret; 1882 1883 ret = at803x_cdt_wait_for_completion(phydev); 1884 if (ret) 1885 return ret; 1886 1887 val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 1888 if (val < 0) 1889 return val; 1890 1891 pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 1892 pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 1893 pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 1894 pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 1895 1896 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 1897 qca808x_cable_test_result_trans(pair_a)); 1898 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 1899 qca808x_cable_test_result_trans(pair_b)); 1900 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 1901 qca808x_cable_test_result_trans(pair_c)); 1902 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 1903 qca808x_cable_test_result_trans(pair_d)); 1904 1905 if (qca808x_cdt_fault_length_valid(pair_a)) 1906 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 1907 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 1908 if (qca808x_cdt_fault_length_valid(pair_b)) 1909 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 1910 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 1911 if (qca808x_cdt_fault_length_valid(pair_c)) 1912 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 1913 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 1914 if (qca808x_cdt_fault_length_valid(pair_d)) 1915 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 1916 qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 1917 1918 *finished = true; 1919 1920 return 0; 1921 } 1922 1923 static struct phy_driver at803x_driver[] = { 1924 { 1925 /* Qualcomm Atheros AR8035 */ 1926 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1927 .name = "Qualcomm Atheros AR8035", 1928 .flags = PHY_POLL_CABLE_TEST, 1929 .probe = at803x_probe, 1930 .remove = at803x_remove, 1931 .config_aneg = at803x_config_aneg, 1932 .config_init = at803x_config_init, 1933 .soft_reset = genphy_soft_reset, 1934 .set_wol = at803x_set_wol, 1935 .get_wol = at803x_get_wol, 1936 .suspend = at803x_suspend, 1937 .resume = at803x_resume, 1938 /* PHY_GBIT_FEATURES */ 1939 .read_status = at803x_read_status, 1940 .config_intr = at803x_config_intr, 1941 .handle_interrupt = at803x_handle_interrupt, 1942 .get_tunable = at803x_get_tunable, 1943 .set_tunable = at803x_set_tunable, 1944 .cable_test_start = at803x_cable_test_start, 1945 .cable_test_get_status = at803x_cable_test_get_status, 1946 }, { 1947 /* Qualcomm Atheros AR8030 */ 1948 .phy_id = ATH8030_PHY_ID, 1949 .name = "Qualcomm Atheros AR8030", 1950 .phy_id_mask = AT8030_PHY_ID_MASK, 1951 .probe = at803x_probe, 1952 .remove = at803x_remove, 1953 .config_init = at803x_config_init, 1954 .link_change_notify = at803x_link_change_notify, 1955 .set_wol = at803x_set_wol, 1956 .get_wol = at803x_get_wol, 1957 .suspend = at803x_suspend, 1958 .resume = at803x_resume, 1959 /* PHY_BASIC_FEATURES */ 1960 .config_intr = at803x_config_intr, 1961 .handle_interrupt = at803x_handle_interrupt, 1962 }, { 1963 /* Qualcomm Atheros AR8031/AR8033 */ 1964 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1965 .name = "Qualcomm Atheros AR8031/AR8033", 1966 .flags = PHY_POLL_CABLE_TEST, 1967 .probe = at803x_probe, 1968 .remove = at803x_remove, 1969 .config_init = at803x_config_init, 1970 .config_aneg = at803x_config_aneg, 1971 .soft_reset = genphy_soft_reset, 1972 .set_wol = at803x_set_wol, 1973 .get_wol = at803x_get_wol, 1974 .suspend = at803x_suspend, 1975 .resume = at803x_resume, 1976 .read_page = at803x_read_page, 1977 .write_page = at803x_write_page, 1978 .get_features = at803x_get_features, 1979 .read_status = at803x_read_status, 1980 .config_intr = &at803x_config_intr, 1981 .handle_interrupt = at803x_handle_interrupt, 1982 .get_tunable = at803x_get_tunable, 1983 .set_tunable = at803x_set_tunable, 1984 .cable_test_start = at803x_cable_test_start, 1985 .cable_test_get_status = at803x_cable_test_get_status, 1986 }, { 1987 /* Qualcomm Atheros AR8032 */ 1988 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1989 .name = "Qualcomm Atheros AR8032", 1990 .probe = at803x_probe, 1991 .remove = at803x_remove, 1992 .flags = PHY_POLL_CABLE_TEST, 1993 .config_init = at803x_config_init, 1994 .link_change_notify = at803x_link_change_notify, 1995 .set_wol = at803x_set_wol, 1996 .get_wol = at803x_get_wol, 1997 .suspend = at803x_suspend, 1998 .resume = at803x_resume, 1999 /* PHY_BASIC_FEATURES */ 2000 .config_intr = at803x_config_intr, 2001 .handle_interrupt = at803x_handle_interrupt, 2002 .cable_test_start = at803x_cable_test_start, 2003 .cable_test_get_status = at803x_cable_test_get_status, 2004 }, { 2005 /* ATHEROS AR9331 */ 2006 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 2007 .name = "Qualcomm Atheros AR9331 built-in PHY", 2008 .suspend = at803x_suspend, 2009 .resume = at803x_resume, 2010 .flags = PHY_POLL_CABLE_TEST, 2011 /* PHY_BASIC_FEATURES */ 2012 .config_intr = &at803x_config_intr, 2013 .handle_interrupt = at803x_handle_interrupt, 2014 .cable_test_start = at803x_cable_test_start, 2015 .cable_test_get_status = at803x_cable_test_get_status, 2016 .read_status = at803x_read_status, 2017 .soft_reset = genphy_soft_reset, 2018 .config_aneg = at803x_config_aneg, 2019 }, { 2020 /* Qualcomm Atheros QCA9561 */ 2021 PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 2022 .name = "Qualcomm Atheros QCA9561 built-in PHY", 2023 .suspend = at803x_suspend, 2024 .resume = at803x_resume, 2025 .flags = PHY_POLL_CABLE_TEST, 2026 /* PHY_BASIC_FEATURES */ 2027 .config_intr = &at803x_config_intr, 2028 .handle_interrupt = at803x_handle_interrupt, 2029 .cable_test_start = at803x_cable_test_start, 2030 .cable_test_get_status = at803x_cable_test_get_status, 2031 .read_status = at803x_read_status, 2032 .soft_reset = genphy_soft_reset, 2033 .config_aneg = at803x_config_aneg, 2034 }, { 2035 /* QCA8337 */ 2036 .phy_id = QCA8337_PHY_ID, 2037 .phy_id_mask = QCA8K_PHY_ID_MASK, 2038 .name = "Qualcomm Atheros 8337 internal PHY", 2039 /* PHY_GBIT_FEATURES */ 2040 .link_change_notify = qca83xx_link_change_notify, 2041 .probe = at803x_probe, 2042 .flags = PHY_IS_INTERNAL, 2043 .config_init = qca83xx_config_init, 2044 .soft_reset = genphy_soft_reset, 2045 .get_sset_count = at803x_get_sset_count, 2046 .get_strings = at803x_get_strings, 2047 .get_stats = at803x_get_stats, 2048 .suspend = qca83xx_suspend, 2049 .resume = qca83xx_resume, 2050 }, { 2051 /* QCA8327-A from switch QCA8327-AL1A */ 2052 .phy_id = QCA8327_A_PHY_ID, 2053 .phy_id_mask = QCA8K_PHY_ID_MASK, 2054 .name = "Qualcomm Atheros 8327-A internal PHY", 2055 /* PHY_GBIT_FEATURES */ 2056 .link_change_notify = qca83xx_link_change_notify, 2057 .probe = at803x_probe, 2058 .flags = PHY_IS_INTERNAL, 2059 .config_init = qca83xx_config_init, 2060 .soft_reset = genphy_soft_reset, 2061 .get_sset_count = at803x_get_sset_count, 2062 .get_strings = at803x_get_strings, 2063 .get_stats = at803x_get_stats, 2064 .suspend = qca83xx_suspend, 2065 .resume = qca83xx_resume, 2066 }, { 2067 /* QCA8327-B from switch QCA8327-BL1A */ 2068 .phy_id = QCA8327_B_PHY_ID, 2069 .phy_id_mask = QCA8K_PHY_ID_MASK, 2070 .name = "Qualcomm Atheros 8327-B internal PHY", 2071 /* PHY_GBIT_FEATURES */ 2072 .link_change_notify = qca83xx_link_change_notify, 2073 .probe = at803x_probe, 2074 .flags = PHY_IS_INTERNAL, 2075 .config_init = qca83xx_config_init, 2076 .soft_reset = genphy_soft_reset, 2077 .get_sset_count = at803x_get_sset_count, 2078 .get_strings = at803x_get_strings, 2079 .get_stats = at803x_get_stats, 2080 .suspend = qca83xx_suspend, 2081 .resume = qca83xx_resume, 2082 }, { 2083 /* Qualcomm QCA8081 */ 2084 PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2085 .name = "Qualcomm QCA8081", 2086 .flags = PHY_POLL_CABLE_TEST, 2087 .config_intr = at803x_config_intr, 2088 .handle_interrupt = at803x_handle_interrupt, 2089 .get_tunable = at803x_get_tunable, 2090 .set_tunable = at803x_set_tunable, 2091 .set_wol = at803x_set_wol, 2092 .get_wol = at803x_get_wol, 2093 .get_features = at803x_get_features, 2094 .config_aneg = at803x_config_aneg, 2095 .suspend = genphy_suspend, 2096 .resume = genphy_resume, 2097 .read_status = qca808x_read_status, 2098 .config_init = qca808x_config_init, 2099 .soft_reset = qca808x_soft_reset, 2100 .cable_test_start = qca808x_cable_test_start, 2101 .cable_test_get_status = qca808x_cable_test_get_status, 2102 }, }; 2103 2104 module_phy_driver(at803x_driver); 2105 2106 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 2107 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 2108 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 2109 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 2110 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 2111 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 2112 { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2113 { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2114 { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2115 { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2116 { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 2117 { } 2118 }; 2119 2120 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2121