1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * drivers/net/phy/at803x.c 4 * 5 * Driver for Qualcomm Atheros AR803x PHY 6 * 7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 8 */ 9 10 #include <linux/phy.h> 11 #include <linux/module.h> 12 #include <linux/string.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool_netlink.h> 16 #include <linux/of_gpio.h> 17 #include <linux/bitfield.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/regulator/of_regulator.h> 20 #include <linux/regulator/driver.h> 21 #include <linux/regulator/consumer.h> 22 #include <dt-bindings/net/qca-ar803x.h> 23 24 #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 25 #define AT803X_SFC_ASSERT_CRS BIT(11) 26 #define AT803X_SFC_FORCE_LINK BIT(10) 27 #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 28 #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 29 #define AT803X_SFC_MANUAL_MDIX 0x1 30 #define AT803X_SFC_MANUAL_MDI 0x0 31 #define AT803X_SFC_SQE_TEST BIT(2) 32 #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 33 #define AT803X_SFC_DISABLE_JABBER BIT(0) 34 35 #define AT803X_SPECIFIC_STATUS 0x11 36 #define AT803X_SS_SPEED_MASK (3 << 14) 37 #define AT803X_SS_SPEED_1000 (2 << 14) 38 #define AT803X_SS_SPEED_100 (1 << 14) 39 #define AT803X_SS_SPEED_10 (0 << 14) 40 #define AT803X_SS_DUPLEX BIT(13) 41 #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 42 #define AT803X_SS_MDIX BIT(6) 43 44 #define AT803X_INTR_ENABLE 0x12 45 #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 46 #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 47 #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 48 #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 49 #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 50 #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 51 #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 52 #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 53 #define AT803X_INTR_ENABLE_WOL BIT(0) 54 55 #define AT803X_INTR_STATUS 0x13 56 57 #define AT803X_SMART_SPEED 0x14 58 #define AT803X_SMART_SPEED_ENABLE BIT(5) 59 #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 60 #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 61 #define AT803X_CDT 0x16 62 #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 63 #define AT803X_CDT_ENABLE_TEST BIT(0) 64 #define AT803X_CDT_STATUS 0x1c 65 #define AT803X_CDT_STATUS_STAT_NORMAL 0 66 #define AT803X_CDT_STATUS_STAT_SHORT 1 67 #define AT803X_CDT_STATUS_STAT_OPEN 2 68 #define AT803X_CDT_STATUS_STAT_FAIL 3 69 #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 70 #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 71 #define AT803X_LED_CONTROL 0x18 72 73 #define AT803X_DEVICE_ADDR 0x03 74 #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 75 #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 76 #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 77 #define AT803X_REG_CHIP_CONFIG 0x1f 78 #define AT803X_BT_BX_REG_SEL 0x8000 79 80 #define AT803X_DEBUG_ADDR 0x1D 81 #define AT803X_DEBUG_DATA 0x1E 82 83 #define AT803X_MODE_CFG_MASK 0x0F 84 #define AT803X_MODE_CFG_SGMII 0x01 85 86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 87 #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 88 89 #define AT803X_DEBUG_REG_0 0x00 90 #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 91 92 #define AT803X_DEBUG_REG_5 0x05 93 #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 94 95 #define AT803X_DEBUG_REG_1F 0x1F 96 #define AT803X_DEBUG_PLL_ON BIT(2) 97 #define AT803X_DEBUG_RGMII_1V8 BIT(3) 98 99 /* AT803x supports either the XTAL input pad, an internal PLL or the 100 * DSP as clock reference for the clock output pad. The XTAL reference 101 * is only used for 25 MHz output, all other frequencies need the PLL. 102 * The DSP as a clock reference is used in synchronous ethernet 103 * applications. 104 * 105 * By default the PLL is only enabled if there is a link. Otherwise 106 * the PHY will go into low power state and disabled the PLL. You can 107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 108 * enabled. 109 */ 110 #define AT803X_MMD7_CLK25M 0x8016 111 #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 112 #define AT803X_CLK_OUT_25MHZ_XTAL 0 113 #define AT803X_CLK_OUT_25MHZ_DSP 1 114 #define AT803X_CLK_OUT_50MHZ_PLL 2 115 #define AT803X_CLK_OUT_50MHZ_DSP 3 116 #define AT803X_CLK_OUT_62_5MHZ_PLL 4 117 #define AT803X_CLK_OUT_62_5MHZ_DSP 5 118 #define AT803X_CLK_OUT_125MHZ_PLL 6 119 #define AT803X_CLK_OUT_125MHZ_DSP 7 120 121 /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 122 * but doesn't support choosing between XTAL/PLL and DSP. 123 */ 124 #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 125 126 #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 127 #define AT803X_CLK_OUT_STRENGTH_FULL 0 128 #define AT803X_CLK_OUT_STRENGTH_HALF 1 129 #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 130 131 #define AT803X_DEFAULT_DOWNSHIFT 5 132 #define AT803X_MIN_DOWNSHIFT 2 133 #define AT803X_MAX_DOWNSHIFT 9 134 135 #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 136 #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 137 #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 138 #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 139 140 #define ATH9331_PHY_ID 0x004dd041 141 #define ATH8030_PHY_ID 0x004dd076 142 #define ATH8031_PHY_ID 0x004dd074 143 #define ATH8032_PHY_ID 0x004dd023 144 #define ATH8035_PHY_ID 0x004dd072 145 #define AT8030_PHY_ID_MASK 0xffffffef 146 147 #define AT803X_PAGE_FIBER 0 148 #define AT803X_PAGE_COPPER 1 149 150 MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 151 MODULE_AUTHOR("Matus Ujhelyi"); 152 MODULE_LICENSE("GPL"); 153 154 struct at803x_priv { 155 int flags; 156 #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ 157 #define AT803X_DISABLE_SMARTEEE BIT(1) 158 u16 clk_25m_reg; 159 u16 clk_25m_mask; 160 u8 smarteee_lpi_tw_1g; 161 u8 smarteee_lpi_tw_100m; 162 struct regulator_dev *vddio_rdev; 163 struct regulator_dev *vddh_rdev; 164 struct regulator *vddio; 165 }; 166 167 struct at803x_context { 168 u16 bmcr; 169 u16 advertise; 170 u16 control1000; 171 u16 int_enable; 172 u16 smart_speed; 173 u16 led_control; 174 }; 175 176 static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 177 { 178 int ret; 179 180 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 181 if (ret < 0) 182 return ret; 183 184 return phy_read(phydev, AT803X_DEBUG_DATA); 185 } 186 187 static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 188 u16 clear, u16 set) 189 { 190 u16 val; 191 int ret; 192 193 ret = at803x_debug_reg_read(phydev, reg); 194 if (ret < 0) 195 return ret; 196 197 val = ret & 0xffff; 198 val &= ~clear; 199 val |= set; 200 201 return phy_write(phydev, AT803X_DEBUG_DATA, val); 202 } 203 204 static int at803x_write_page(struct phy_device *phydev, int page) 205 { 206 int mask; 207 int set; 208 209 if (page == AT803X_PAGE_COPPER) { 210 set = AT803X_BT_BX_REG_SEL; 211 mask = 0; 212 } else { 213 set = 0; 214 mask = AT803X_BT_BX_REG_SEL; 215 } 216 217 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 218 } 219 220 static int at803x_read_page(struct phy_device *phydev) 221 { 222 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 223 224 if (ccr < 0) 225 return ccr; 226 227 if (ccr & AT803X_BT_BX_REG_SEL) 228 return AT803X_PAGE_COPPER; 229 230 return AT803X_PAGE_FIBER; 231 } 232 233 static int at803x_enable_rx_delay(struct phy_device *phydev) 234 { 235 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 236 AT803X_DEBUG_RX_CLK_DLY_EN); 237 } 238 239 static int at803x_enable_tx_delay(struct phy_device *phydev) 240 { 241 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 242 AT803X_DEBUG_TX_CLK_DLY_EN); 243 } 244 245 static int at803x_disable_rx_delay(struct phy_device *phydev) 246 { 247 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 248 AT803X_DEBUG_RX_CLK_DLY_EN, 0); 249 } 250 251 static int at803x_disable_tx_delay(struct phy_device *phydev) 252 { 253 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 254 AT803X_DEBUG_TX_CLK_DLY_EN, 0); 255 } 256 257 /* save relevant PHY registers to private copy */ 258 static void at803x_context_save(struct phy_device *phydev, 259 struct at803x_context *context) 260 { 261 context->bmcr = phy_read(phydev, MII_BMCR); 262 context->advertise = phy_read(phydev, MII_ADVERTISE); 263 context->control1000 = phy_read(phydev, MII_CTRL1000); 264 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 265 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 266 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 267 } 268 269 /* restore relevant PHY registers from private copy */ 270 static void at803x_context_restore(struct phy_device *phydev, 271 const struct at803x_context *context) 272 { 273 phy_write(phydev, MII_BMCR, context->bmcr); 274 phy_write(phydev, MII_ADVERTISE, context->advertise); 275 phy_write(phydev, MII_CTRL1000, context->control1000); 276 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 277 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 278 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 279 } 280 281 static int at803x_set_wol(struct phy_device *phydev, 282 struct ethtool_wolinfo *wol) 283 { 284 struct net_device *ndev = phydev->attached_dev; 285 const u8 *mac; 286 int ret; 287 u32 value; 288 unsigned int i, offsets[] = { 289 AT803X_LOC_MAC_ADDR_32_47_OFFSET, 290 AT803X_LOC_MAC_ADDR_16_31_OFFSET, 291 AT803X_LOC_MAC_ADDR_0_15_OFFSET, 292 }; 293 294 if (!ndev) 295 return -ENODEV; 296 297 if (wol->wolopts & WAKE_MAGIC) { 298 mac = (const u8 *) ndev->dev_addr; 299 300 if (!is_valid_ether_addr(mac)) 301 return -EINVAL; 302 303 for (i = 0; i < 3; i++) 304 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 305 mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 306 307 value = phy_read(phydev, AT803X_INTR_ENABLE); 308 value |= AT803X_INTR_ENABLE_WOL; 309 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 310 if (ret) 311 return ret; 312 value = phy_read(phydev, AT803X_INTR_STATUS); 313 } else { 314 value = phy_read(phydev, AT803X_INTR_ENABLE); 315 value &= (~AT803X_INTR_ENABLE_WOL); 316 ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 317 if (ret) 318 return ret; 319 value = phy_read(phydev, AT803X_INTR_STATUS); 320 } 321 322 return ret; 323 } 324 325 static void at803x_get_wol(struct phy_device *phydev, 326 struct ethtool_wolinfo *wol) 327 { 328 u32 value; 329 330 wol->supported = WAKE_MAGIC; 331 wol->wolopts = 0; 332 333 value = phy_read(phydev, AT803X_INTR_ENABLE); 334 if (value & AT803X_INTR_ENABLE_WOL) 335 wol->wolopts |= WAKE_MAGIC; 336 } 337 338 static int at803x_suspend(struct phy_device *phydev) 339 { 340 int value; 341 int wol_enabled; 342 343 value = phy_read(phydev, AT803X_INTR_ENABLE); 344 wol_enabled = value & AT803X_INTR_ENABLE_WOL; 345 346 if (wol_enabled) 347 value = BMCR_ISOLATE; 348 else 349 value = BMCR_PDOWN; 350 351 phy_modify(phydev, MII_BMCR, 0, value); 352 353 return 0; 354 } 355 356 static int at803x_resume(struct phy_device *phydev) 357 { 358 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 359 } 360 361 static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 362 unsigned int selector) 363 { 364 struct phy_device *phydev = rdev_get_drvdata(rdev); 365 366 if (selector) 367 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 368 0, AT803X_DEBUG_RGMII_1V8); 369 else 370 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 371 AT803X_DEBUG_RGMII_1V8, 0); 372 } 373 374 static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 375 { 376 struct phy_device *phydev = rdev_get_drvdata(rdev); 377 int val; 378 379 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 380 if (val < 0) 381 return val; 382 383 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 384 } 385 386 static const struct regulator_ops vddio_regulator_ops = { 387 .list_voltage = regulator_list_voltage_table, 388 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 389 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 390 }; 391 392 static const unsigned int vddio_voltage_table[] = { 393 1500000, 394 1800000, 395 }; 396 397 static const struct regulator_desc vddio_desc = { 398 .name = "vddio", 399 .of_match = of_match_ptr("vddio-regulator"), 400 .n_voltages = ARRAY_SIZE(vddio_voltage_table), 401 .volt_table = vddio_voltage_table, 402 .ops = &vddio_regulator_ops, 403 .type = REGULATOR_VOLTAGE, 404 .owner = THIS_MODULE, 405 }; 406 407 static const struct regulator_ops vddh_regulator_ops = { 408 }; 409 410 static const struct regulator_desc vddh_desc = { 411 .name = "vddh", 412 .of_match = of_match_ptr("vddh-regulator"), 413 .n_voltages = 1, 414 .fixed_uV = 2500000, 415 .ops = &vddh_regulator_ops, 416 .type = REGULATOR_VOLTAGE, 417 .owner = THIS_MODULE, 418 }; 419 420 static int at8031_register_regulators(struct phy_device *phydev) 421 { 422 struct at803x_priv *priv = phydev->priv; 423 struct device *dev = &phydev->mdio.dev; 424 struct regulator_config config = { }; 425 426 config.dev = dev; 427 config.driver_data = phydev; 428 429 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 430 if (IS_ERR(priv->vddio_rdev)) { 431 phydev_err(phydev, "failed to register VDDIO regulator\n"); 432 return PTR_ERR(priv->vddio_rdev); 433 } 434 435 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 436 if (IS_ERR(priv->vddh_rdev)) { 437 phydev_err(phydev, "failed to register VDDH regulator\n"); 438 return PTR_ERR(priv->vddh_rdev); 439 } 440 441 return 0; 442 } 443 444 static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) 445 { 446 return (phydev->phy_id & phydev->drv->phy_id_mask) 447 == (phy_id & phydev->drv->phy_id_mask); 448 } 449 450 static int at803x_parse_dt(struct phy_device *phydev) 451 { 452 struct device_node *node = phydev->mdio.dev.of_node; 453 struct at803x_priv *priv = phydev->priv; 454 u32 freq, strength, tw; 455 unsigned int sel; 456 int ret; 457 458 if (!IS_ENABLED(CONFIG_OF_MDIO)) 459 return 0; 460 461 if (of_property_read_bool(node, "qca,disable-smarteee")) 462 priv->flags |= AT803X_DISABLE_SMARTEEE; 463 464 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 465 if (!tw || tw > 255) { 466 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 467 return -EINVAL; 468 } 469 priv->smarteee_lpi_tw_1g = tw; 470 } 471 472 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 473 if (!tw || tw > 255) { 474 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 475 return -EINVAL; 476 } 477 priv->smarteee_lpi_tw_100m = tw; 478 } 479 480 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 481 if (!ret) { 482 switch (freq) { 483 case 25000000: 484 sel = AT803X_CLK_OUT_25MHZ_XTAL; 485 break; 486 case 50000000: 487 sel = AT803X_CLK_OUT_50MHZ_PLL; 488 break; 489 case 62500000: 490 sel = AT803X_CLK_OUT_62_5MHZ_PLL; 491 break; 492 case 125000000: 493 sel = AT803X_CLK_OUT_125MHZ_PLL; 494 break; 495 default: 496 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 497 return -EINVAL; 498 } 499 500 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 501 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 502 503 /* Fixup for the AR8030/AR8035. This chip has another mask and 504 * doesn't support the DSP reference. Eg. the lowest bit of the 505 * mask. The upper two bits select the same frequencies. Mask 506 * the lowest bit here. 507 * 508 * Warning: 509 * There was no datasheet for the AR8030 available so this is 510 * just a guess. But the AR8035 is listed as pin compatible 511 * to the AR8030 so there might be a good chance it works on 512 * the AR8030 too. 513 */ 514 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || 515 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { 516 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 517 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 518 } 519 } 520 521 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 522 if (!ret) { 523 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 524 switch (strength) { 525 case AR803X_STRENGTH_FULL: 526 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 527 break; 528 case AR803X_STRENGTH_HALF: 529 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 530 break; 531 case AR803X_STRENGTH_QUARTER: 532 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 533 break; 534 default: 535 phydev_err(phydev, "invalid qca,clk-out-strength\n"); 536 return -EINVAL; 537 } 538 } 539 540 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 541 * options. 542 */ 543 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 544 if (of_property_read_bool(node, "qca,keep-pll-enabled")) 545 priv->flags |= AT803X_KEEP_PLL_ENABLED; 546 547 ret = at8031_register_regulators(phydev); 548 if (ret < 0) 549 return ret; 550 551 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 552 "vddio"); 553 if (IS_ERR(priv->vddio)) { 554 phydev_err(phydev, "failed to get VDDIO regulator\n"); 555 return PTR_ERR(priv->vddio); 556 } 557 } 558 559 return 0; 560 } 561 562 static int at803x_probe(struct phy_device *phydev) 563 { 564 struct device *dev = &phydev->mdio.dev; 565 struct at803x_priv *priv; 566 int ret; 567 568 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 569 if (!priv) 570 return -ENOMEM; 571 572 phydev->priv = priv; 573 574 ret = at803x_parse_dt(phydev); 575 if (ret) 576 return ret; 577 578 if (priv->vddio) { 579 ret = regulator_enable(priv->vddio); 580 if (ret < 0) 581 return ret; 582 } 583 584 /* Some bootloaders leave the fiber page selected. 585 * Switch to the copper page, as otherwise we read 586 * the PHY capabilities from the fiber side. 587 */ 588 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 589 phy_lock_mdio_bus(phydev); 590 ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); 591 phy_unlock_mdio_bus(phydev); 592 if (ret) 593 goto err; 594 } 595 596 return 0; 597 598 err: 599 if (priv->vddio) 600 regulator_disable(priv->vddio); 601 602 return ret; 603 } 604 605 static void at803x_remove(struct phy_device *phydev) 606 { 607 struct at803x_priv *priv = phydev->priv; 608 609 if (priv->vddio) 610 regulator_disable(priv->vddio); 611 } 612 613 static int at803x_smarteee_config(struct phy_device *phydev) 614 { 615 struct at803x_priv *priv = phydev->priv; 616 u16 mask = 0, val = 0; 617 int ret; 618 619 if (priv->flags & AT803X_DISABLE_SMARTEEE) 620 return phy_modify_mmd(phydev, MDIO_MMD_PCS, 621 AT803X_MMD3_SMARTEEE_CTL3, 622 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 623 624 if (priv->smarteee_lpi_tw_1g) { 625 mask |= 0xff00; 626 val |= priv->smarteee_lpi_tw_1g << 8; 627 } 628 if (priv->smarteee_lpi_tw_100m) { 629 mask |= 0x00ff; 630 val |= priv->smarteee_lpi_tw_100m; 631 } 632 if (!mask) 633 return 0; 634 635 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 636 mask, val); 637 if (ret) 638 return ret; 639 640 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 641 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 642 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 643 } 644 645 static int at803x_clk_out_config(struct phy_device *phydev) 646 { 647 struct at803x_priv *priv = phydev->priv; 648 649 if (!priv->clk_25m_mask) 650 return 0; 651 652 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 653 priv->clk_25m_mask, priv->clk_25m_reg); 654 } 655 656 static int at8031_pll_config(struct phy_device *phydev) 657 { 658 struct at803x_priv *priv = phydev->priv; 659 660 /* The default after hardware reset is PLL OFF. After a soft reset, the 661 * values are retained. 662 */ 663 if (priv->flags & AT803X_KEEP_PLL_ENABLED) 664 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 665 0, AT803X_DEBUG_PLL_ON); 666 else 667 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 668 AT803X_DEBUG_PLL_ON, 0); 669 } 670 671 static int at803x_config_init(struct phy_device *phydev) 672 { 673 int ret; 674 675 /* The RX and TX delay default is: 676 * after HW reset: RX delay enabled and TX delay disabled 677 * after SW reset: RX delay enabled, while TX delay retains the 678 * value before reset. 679 */ 680 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 681 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 682 ret = at803x_enable_rx_delay(phydev); 683 else 684 ret = at803x_disable_rx_delay(phydev); 685 if (ret < 0) 686 return ret; 687 688 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 689 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 690 ret = at803x_enable_tx_delay(phydev); 691 else 692 ret = at803x_disable_tx_delay(phydev); 693 if (ret < 0) 694 return ret; 695 696 ret = at803x_smarteee_config(phydev); 697 if (ret < 0) 698 return ret; 699 700 ret = at803x_clk_out_config(phydev); 701 if (ret < 0) 702 return ret; 703 704 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 705 ret = at8031_pll_config(phydev); 706 if (ret < 0) 707 return ret; 708 } 709 710 /* Ar803x extended next page bit is enabled by default. Cisco 711 * multigig switches read this bit and attempt to negotiate 10Gbps 712 * rates even if the next page bit is disabled. This is incorrect 713 * behaviour but we still need to accommodate it. XNP is only needed 714 * for 10Gbps support, so disable XNP. 715 */ 716 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 717 } 718 719 static int at803x_ack_interrupt(struct phy_device *phydev) 720 { 721 int err; 722 723 err = phy_read(phydev, AT803X_INTR_STATUS); 724 725 return (err < 0) ? err : 0; 726 } 727 728 static int at803x_config_intr(struct phy_device *phydev) 729 { 730 int err; 731 int value; 732 733 value = phy_read(phydev, AT803X_INTR_ENABLE); 734 735 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 736 /* Clear any pending interrupts */ 737 err = at803x_ack_interrupt(phydev); 738 if (err) 739 return err; 740 741 value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 742 value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 743 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 744 value |= AT803X_INTR_ENABLE_LINK_FAIL; 745 value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 746 747 err = phy_write(phydev, AT803X_INTR_ENABLE, value); 748 } else { 749 err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 750 if (err) 751 return err; 752 753 /* Clear any pending interrupts */ 754 err = at803x_ack_interrupt(phydev); 755 } 756 757 return err; 758 } 759 760 static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 761 { 762 int irq_status, int_enabled; 763 764 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 765 if (irq_status < 0) { 766 phy_error(phydev); 767 return IRQ_NONE; 768 } 769 770 /* Read the current enabled interrupts */ 771 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 772 if (int_enabled < 0) { 773 phy_error(phydev); 774 return IRQ_NONE; 775 } 776 777 /* See if this was one of our enabled interrupts */ 778 if (!(irq_status & int_enabled)) 779 return IRQ_NONE; 780 781 phy_trigger_machine(phydev); 782 783 return IRQ_HANDLED; 784 } 785 786 static void at803x_link_change_notify(struct phy_device *phydev) 787 { 788 /* 789 * Conduct a hardware reset for AT8030 every time a link loss is 790 * signalled. This is necessary to circumvent a hardware bug that 791 * occurs when the cable is unplugged while TX packets are pending 792 * in the FIFO. In such cases, the FIFO enters an error mode it 793 * cannot recover from by software. 794 */ 795 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 796 struct at803x_context context; 797 798 at803x_context_save(phydev, &context); 799 800 phy_device_reset(phydev, 1); 801 msleep(1); 802 phy_device_reset(phydev, 0); 803 msleep(1); 804 805 at803x_context_restore(phydev, &context); 806 807 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 808 } 809 } 810 811 static int at803x_read_status(struct phy_device *phydev) 812 { 813 int ss, err, old_link = phydev->link; 814 815 /* Update the link, but return if there was an error */ 816 err = genphy_update_link(phydev); 817 if (err) 818 return err; 819 820 /* why bother the PHY if nothing can have changed */ 821 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 822 return 0; 823 824 phydev->speed = SPEED_UNKNOWN; 825 phydev->duplex = DUPLEX_UNKNOWN; 826 phydev->pause = 0; 827 phydev->asym_pause = 0; 828 829 err = genphy_read_lpa(phydev); 830 if (err < 0) 831 return err; 832 833 /* Read the AT8035 PHY-Specific Status register, which indicates the 834 * speed and duplex that the PHY is actually using, irrespective of 835 * whether we are in autoneg mode or not. 836 */ 837 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 838 if (ss < 0) 839 return ss; 840 841 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 842 int sfc; 843 844 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 845 if (sfc < 0) 846 return sfc; 847 848 switch (ss & AT803X_SS_SPEED_MASK) { 849 case AT803X_SS_SPEED_10: 850 phydev->speed = SPEED_10; 851 break; 852 case AT803X_SS_SPEED_100: 853 phydev->speed = SPEED_100; 854 break; 855 case AT803X_SS_SPEED_1000: 856 phydev->speed = SPEED_1000; 857 break; 858 } 859 if (ss & AT803X_SS_DUPLEX) 860 phydev->duplex = DUPLEX_FULL; 861 else 862 phydev->duplex = DUPLEX_HALF; 863 864 if (ss & AT803X_SS_MDIX) 865 phydev->mdix = ETH_TP_MDI_X; 866 else 867 phydev->mdix = ETH_TP_MDI; 868 869 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 870 case AT803X_SFC_MANUAL_MDI: 871 phydev->mdix_ctrl = ETH_TP_MDI; 872 break; 873 case AT803X_SFC_MANUAL_MDIX: 874 phydev->mdix_ctrl = ETH_TP_MDI_X; 875 break; 876 case AT803X_SFC_AUTOMATIC_CROSSOVER: 877 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 878 break; 879 } 880 } 881 882 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 883 phy_resolve_aneg_pause(phydev); 884 885 return 0; 886 } 887 888 static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 889 { 890 u16 val; 891 892 switch (ctrl) { 893 case ETH_TP_MDI: 894 val = AT803X_SFC_MANUAL_MDI; 895 break; 896 case ETH_TP_MDI_X: 897 val = AT803X_SFC_MANUAL_MDIX; 898 break; 899 case ETH_TP_MDI_AUTO: 900 val = AT803X_SFC_AUTOMATIC_CROSSOVER; 901 break; 902 default: 903 return 0; 904 } 905 906 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 907 AT803X_SFC_MDI_CROSSOVER_MODE_M, 908 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 909 } 910 911 static int at803x_config_aneg(struct phy_device *phydev) 912 { 913 int ret; 914 915 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 916 if (ret < 0) 917 return ret; 918 919 /* Changes of the midx bits are disruptive to the normal operation; 920 * therefore any changes to these registers must be followed by a 921 * software reset to take effect. 922 */ 923 if (ret == 1) { 924 ret = genphy_soft_reset(phydev); 925 if (ret < 0) 926 return ret; 927 } 928 929 return genphy_config_aneg(phydev); 930 } 931 932 static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 933 { 934 int val; 935 936 val = phy_read(phydev, AT803X_SMART_SPEED); 937 if (val < 0) 938 return val; 939 940 if (val & AT803X_SMART_SPEED_ENABLE) 941 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 942 else 943 *d = DOWNSHIFT_DEV_DISABLE; 944 945 return 0; 946 } 947 948 static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 949 { 950 u16 mask, set; 951 int ret; 952 953 switch (cnt) { 954 case DOWNSHIFT_DEV_DEFAULT_COUNT: 955 cnt = AT803X_DEFAULT_DOWNSHIFT; 956 fallthrough; 957 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 958 set = AT803X_SMART_SPEED_ENABLE | 959 AT803X_SMART_SPEED_BYPASS_TIMER | 960 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 961 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 962 break; 963 case DOWNSHIFT_DEV_DISABLE: 964 set = 0; 965 mask = AT803X_SMART_SPEED_ENABLE | 966 AT803X_SMART_SPEED_BYPASS_TIMER; 967 break; 968 default: 969 return -EINVAL; 970 } 971 972 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 973 974 /* After changing the smart speed settings, we need to perform a 975 * software reset, use phy_init_hw() to make sure we set the 976 * reapply any values which might got lost during software reset. 977 */ 978 if (ret == 1) 979 ret = phy_init_hw(phydev); 980 981 return ret; 982 } 983 984 static int at803x_get_tunable(struct phy_device *phydev, 985 struct ethtool_tunable *tuna, void *data) 986 { 987 switch (tuna->id) { 988 case ETHTOOL_PHY_DOWNSHIFT: 989 return at803x_get_downshift(phydev, data); 990 default: 991 return -EOPNOTSUPP; 992 } 993 } 994 995 static int at803x_set_tunable(struct phy_device *phydev, 996 struct ethtool_tunable *tuna, const void *data) 997 { 998 switch (tuna->id) { 999 case ETHTOOL_PHY_DOWNSHIFT: 1000 return at803x_set_downshift(phydev, *(const u8 *)data); 1001 default: 1002 return -EOPNOTSUPP; 1003 } 1004 } 1005 1006 static int at803x_cable_test_result_trans(u16 status) 1007 { 1008 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1009 case AT803X_CDT_STATUS_STAT_NORMAL: 1010 return ETHTOOL_A_CABLE_RESULT_CODE_OK; 1011 case AT803X_CDT_STATUS_STAT_SHORT: 1012 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 1013 case AT803X_CDT_STATUS_STAT_OPEN: 1014 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 1015 case AT803X_CDT_STATUS_STAT_FAIL: 1016 default: 1017 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 1018 } 1019 } 1020 1021 static bool at803x_cdt_test_failed(u16 status) 1022 { 1023 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 1024 AT803X_CDT_STATUS_STAT_FAIL; 1025 } 1026 1027 static bool at803x_cdt_fault_length_valid(u16 status) 1028 { 1029 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 1030 case AT803X_CDT_STATUS_STAT_OPEN: 1031 case AT803X_CDT_STATUS_STAT_SHORT: 1032 return true; 1033 } 1034 return false; 1035 } 1036 1037 static int at803x_cdt_fault_length(u16 status) 1038 { 1039 int dt; 1040 1041 /* According to the datasheet the distance to the fault is 1042 * DELTA_TIME * 0.824 meters. 1043 * 1044 * The author suspect the correct formula is: 1045 * 1046 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 1047 * 1048 * where c is the speed of light, VF is the velocity factor of 1049 * the twisted pair cable, 125MHz the counter frequency and 1050 * we need to divide by 2 because the hardware will measure the 1051 * round trip time to the fault and back to the PHY. 1052 * 1053 * With a VF of 0.69 we get the factor 0.824 mentioned in the 1054 * datasheet. 1055 */ 1056 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 1057 1058 return (dt * 824) / 10; 1059 } 1060 1061 static int at803x_cdt_start(struct phy_device *phydev, int pair) 1062 { 1063 u16 cdt; 1064 1065 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 1066 AT803X_CDT_ENABLE_TEST; 1067 1068 return phy_write(phydev, AT803X_CDT, cdt); 1069 } 1070 1071 static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 1072 { 1073 int val, ret; 1074 1075 /* One test run takes about 25ms */ 1076 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 1077 !(val & AT803X_CDT_ENABLE_TEST), 1078 30000, 100000, true); 1079 1080 return ret < 0 ? ret : 0; 1081 } 1082 1083 static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 1084 { 1085 static const int ethtool_pair[] = { 1086 ETHTOOL_A_CABLE_PAIR_A, 1087 ETHTOOL_A_CABLE_PAIR_B, 1088 ETHTOOL_A_CABLE_PAIR_C, 1089 ETHTOOL_A_CABLE_PAIR_D, 1090 }; 1091 int ret, val; 1092 1093 ret = at803x_cdt_start(phydev, pair); 1094 if (ret) 1095 return ret; 1096 1097 ret = at803x_cdt_wait_for_completion(phydev); 1098 if (ret) 1099 return ret; 1100 1101 val = phy_read(phydev, AT803X_CDT_STATUS); 1102 if (val < 0) 1103 return val; 1104 1105 if (at803x_cdt_test_failed(val)) 1106 return 0; 1107 1108 ethnl_cable_test_result(phydev, ethtool_pair[pair], 1109 at803x_cable_test_result_trans(val)); 1110 1111 if (at803x_cdt_fault_length_valid(val)) 1112 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 1113 at803x_cdt_fault_length(val)); 1114 1115 return 1; 1116 } 1117 1118 static int at803x_cable_test_get_status(struct phy_device *phydev, 1119 bool *finished) 1120 { 1121 unsigned long pair_mask; 1122 int retries = 20; 1123 int pair, ret; 1124 1125 if (phydev->phy_id == ATH9331_PHY_ID || 1126 phydev->phy_id == ATH8032_PHY_ID) 1127 pair_mask = 0x3; 1128 else 1129 pair_mask = 0xf; 1130 1131 *finished = false; 1132 1133 /* According to the datasheet the CDT can be performed when 1134 * there is no link partner or when the link partner is 1135 * auto-negotiating. Starting the test will restart the AN 1136 * automatically. It seems that doing this repeatedly we will 1137 * get a slot where our link partner won't disturb our 1138 * measurement. 1139 */ 1140 while (pair_mask && retries--) { 1141 for_each_set_bit(pair, &pair_mask, 4) { 1142 ret = at803x_cable_test_one_pair(phydev, pair); 1143 if (ret < 0) 1144 return ret; 1145 if (ret) 1146 clear_bit(pair, &pair_mask); 1147 } 1148 if (pair_mask) 1149 msleep(250); 1150 } 1151 1152 *finished = true; 1153 1154 return 0; 1155 } 1156 1157 static int at803x_cable_test_start(struct phy_device *phydev) 1158 { 1159 /* Enable auto-negotiation, but advertise no capabilities, no link 1160 * will be established. A restart of the auto-negotiation is not 1161 * required, because the cable test will automatically break the link. 1162 */ 1163 phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 1164 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1165 if (phydev->phy_id != ATH9331_PHY_ID && 1166 phydev->phy_id != ATH8032_PHY_ID) 1167 phy_write(phydev, MII_CTRL1000, 0); 1168 1169 /* we do all the (time consuming) work later */ 1170 return 0; 1171 } 1172 1173 static struct phy_driver at803x_driver[] = { 1174 { 1175 /* Qualcomm Atheros AR8035 */ 1176 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 1177 .name = "Qualcomm Atheros AR8035", 1178 .flags = PHY_POLL_CABLE_TEST, 1179 .probe = at803x_probe, 1180 .remove = at803x_remove, 1181 .config_aneg = at803x_config_aneg, 1182 .config_init = at803x_config_init, 1183 .soft_reset = genphy_soft_reset, 1184 .set_wol = at803x_set_wol, 1185 .get_wol = at803x_get_wol, 1186 .suspend = at803x_suspend, 1187 .resume = at803x_resume, 1188 /* PHY_GBIT_FEATURES */ 1189 .read_status = at803x_read_status, 1190 .config_intr = at803x_config_intr, 1191 .handle_interrupt = at803x_handle_interrupt, 1192 .get_tunable = at803x_get_tunable, 1193 .set_tunable = at803x_set_tunable, 1194 .cable_test_start = at803x_cable_test_start, 1195 .cable_test_get_status = at803x_cable_test_get_status, 1196 }, { 1197 /* Qualcomm Atheros AR8030 */ 1198 .phy_id = ATH8030_PHY_ID, 1199 .name = "Qualcomm Atheros AR8030", 1200 .phy_id_mask = AT8030_PHY_ID_MASK, 1201 .probe = at803x_probe, 1202 .remove = at803x_remove, 1203 .config_init = at803x_config_init, 1204 .link_change_notify = at803x_link_change_notify, 1205 .set_wol = at803x_set_wol, 1206 .get_wol = at803x_get_wol, 1207 .suspend = at803x_suspend, 1208 .resume = at803x_resume, 1209 /* PHY_BASIC_FEATURES */ 1210 .config_intr = at803x_config_intr, 1211 .handle_interrupt = at803x_handle_interrupt, 1212 }, { 1213 /* Qualcomm Atheros AR8031/AR8033 */ 1214 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 1215 .name = "Qualcomm Atheros AR8031/AR8033", 1216 .flags = PHY_POLL_CABLE_TEST, 1217 .probe = at803x_probe, 1218 .remove = at803x_remove, 1219 .config_init = at803x_config_init, 1220 .config_aneg = at803x_config_aneg, 1221 .soft_reset = genphy_soft_reset, 1222 .set_wol = at803x_set_wol, 1223 .get_wol = at803x_get_wol, 1224 .suspend = at803x_suspend, 1225 .resume = at803x_resume, 1226 .read_page = at803x_read_page, 1227 .write_page = at803x_write_page, 1228 /* PHY_GBIT_FEATURES */ 1229 .read_status = at803x_read_status, 1230 .config_intr = &at803x_config_intr, 1231 .handle_interrupt = at803x_handle_interrupt, 1232 .get_tunable = at803x_get_tunable, 1233 .set_tunable = at803x_set_tunable, 1234 .cable_test_start = at803x_cable_test_start, 1235 .cable_test_get_status = at803x_cable_test_get_status, 1236 }, { 1237 /* Qualcomm Atheros AR8032 */ 1238 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 1239 .name = "Qualcomm Atheros AR8032", 1240 .probe = at803x_probe, 1241 .remove = at803x_remove, 1242 .flags = PHY_POLL_CABLE_TEST, 1243 .config_init = at803x_config_init, 1244 .link_change_notify = at803x_link_change_notify, 1245 .set_wol = at803x_set_wol, 1246 .get_wol = at803x_get_wol, 1247 .suspend = at803x_suspend, 1248 .resume = at803x_resume, 1249 /* PHY_BASIC_FEATURES */ 1250 .config_intr = at803x_config_intr, 1251 .handle_interrupt = at803x_handle_interrupt, 1252 .cable_test_start = at803x_cable_test_start, 1253 .cable_test_get_status = at803x_cable_test_get_status, 1254 }, { 1255 /* ATHEROS AR9331 */ 1256 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 1257 .name = "Qualcomm Atheros AR9331 built-in PHY", 1258 .suspend = at803x_suspend, 1259 .resume = at803x_resume, 1260 .flags = PHY_POLL_CABLE_TEST, 1261 /* PHY_BASIC_FEATURES */ 1262 .config_intr = &at803x_config_intr, 1263 .handle_interrupt = at803x_handle_interrupt, 1264 .cable_test_start = at803x_cable_test_start, 1265 .cable_test_get_status = at803x_cable_test_get_status, 1266 .read_status = at803x_read_status, 1267 .soft_reset = genphy_soft_reset, 1268 .config_aneg = at803x_config_aneg, 1269 } }; 1270 1271 module_phy_driver(at803x_driver); 1272 1273 static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1274 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 1275 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 1276 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 1277 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 1278 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 1279 { } 1280 }; 1281 1282 MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1283