xref: /openbmc/linux/drivers/net/phy/at803x.c (revision ea13c9ee)
10ca7111aSMatus Ujhelyi /*
20ca7111aSMatus Ujhelyi  * drivers/net/phy/at803x.c
30ca7111aSMatus Ujhelyi  *
40ca7111aSMatus Ujhelyi  * Driver for Atheros 803x PHY
50ca7111aSMatus Ujhelyi  *
60ca7111aSMatus Ujhelyi  * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
70ca7111aSMatus Ujhelyi  *
80ca7111aSMatus Ujhelyi  * This program is free software; you can redistribute  it and/or modify it
90ca7111aSMatus Ujhelyi  * under  the terms of  the GNU General  Public License as published by the
100ca7111aSMatus Ujhelyi  * Free Software Foundation;  either version 2 of the  License, or (at your
110ca7111aSMatus Ujhelyi  * option) any later version.
120ca7111aSMatus Ujhelyi  */
130ca7111aSMatus Ujhelyi 
140ca7111aSMatus Ujhelyi #include <linux/phy.h>
150ca7111aSMatus Ujhelyi #include <linux/module.h>
160ca7111aSMatus Ujhelyi #include <linux/string.h>
170ca7111aSMatus Ujhelyi #include <linux/netdevice.h>
180ca7111aSMatus Ujhelyi #include <linux/etherdevice.h>
190ca7111aSMatus Ujhelyi 
200ca7111aSMatus Ujhelyi #define AT803X_INTR_ENABLE			0x12
210ca7111aSMatus Ujhelyi #define AT803X_INTR_STATUS			0x13
220ca7111aSMatus Ujhelyi #define AT803X_WOL_ENABLE			0x01
230ca7111aSMatus Ujhelyi #define AT803X_DEVICE_ADDR			0x03
240ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
250ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
260ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
270ca7111aSMatus Ujhelyi #define AT803X_MMD_ACCESS_CONTROL		0x0D
280ca7111aSMatus Ujhelyi #define AT803X_MMD_ACCESS_CONTROL_DATA		0x0E
290ca7111aSMatus Ujhelyi #define AT803X_FUNC_DATA			0x4003
300ca7111aSMatus Ujhelyi 
310ca7111aSMatus Ujhelyi MODULE_DESCRIPTION("Atheros 803x PHY driver");
320ca7111aSMatus Ujhelyi MODULE_AUTHOR("Matus Ujhelyi");
330ca7111aSMatus Ujhelyi MODULE_LICENSE("GPL");
340ca7111aSMatus Ujhelyi 
35ea13c9eeSMugunthan V N static int at803x_set_wol(struct phy_device *phydev,
36ea13c9eeSMugunthan V N 			  struct ethtool_wolinfo *wol)
370ca7111aSMatus Ujhelyi {
380ca7111aSMatus Ujhelyi 	struct net_device *ndev = phydev->attached_dev;
390ca7111aSMatus Ujhelyi 	const u8 *mac;
40ea13c9eeSMugunthan V N 	int ret;
41ea13c9eeSMugunthan V N 	u32 value;
420ca7111aSMatus Ujhelyi 	unsigned int i, offsets[] = {
430ca7111aSMatus Ujhelyi 		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
440ca7111aSMatus Ujhelyi 		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
450ca7111aSMatus Ujhelyi 		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
460ca7111aSMatus Ujhelyi 	};
470ca7111aSMatus Ujhelyi 
480ca7111aSMatus Ujhelyi 	if (!ndev)
49ea13c9eeSMugunthan V N 		return -ENODEV;
500ca7111aSMatus Ujhelyi 
51ea13c9eeSMugunthan V N 	if (wol->wolopts & WAKE_MAGIC) {
520ca7111aSMatus Ujhelyi 		mac = (const u8 *) ndev->dev_addr;
530ca7111aSMatus Ujhelyi 
540ca7111aSMatus Ujhelyi 		if (!is_valid_ether_addr(mac))
55ea13c9eeSMugunthan V N 			return -EFAULT;
560ca7111aSMatus Ujhelyi 
570ca7111aSMatus Ujhelyi 		for (i = 0; i < 3; i++) {
580ca7111aSMatus Ujhelyi 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
590ca7111aSMatus Ujhelyi 				  AT803X_DEVICE_ADDR);
600ca7111aSMatus Ujhelyi 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
610ca7111aSMatus Ujhelyi 				  offsets[i]);
620ca7111aSMatus Ujhelyi 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
630ca7111aSMatus Ujhelyi 				  AT803X_FUNC_DATA);
640ca7111aSMatus Ujhelyi 			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
650ca7111aSMatus Ujhelyi 				  mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
660ca7111aSMatus Ujhelyi 		}
67ea13c9eeSMugunthan V N 
68ea13c9eeSMugunthan V N 		value = phy_read(phydev, AT803X_INTR_ENABLE);
69ea13c9eeSMugunthan V N 		value |= AT803X_WOL_ENABLE;
70ea13c9eeSMugunthan V N 		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
71ea13c9eeSMugunthan V N 		if (ret)
72ea13c9eeSMugunthan V N 			return ret;
73ea13c9eeSMugunthan V N 		value = phy_read(phydev, AT803X_INTR_STATUS);
74ea13c9eeSMugunthan V N 	} else {
75ea13c9eeSMugunthan V N 		value = phy_read(phydev, AT803X_INTR_ENABLE);
76ea13c9eeSMugunthan V N 		value &= (~AT803X_WOL_ENABLE);
77ea13c9eeSMugunthan V N 		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
78ea13c9eeSMugunthan V N 		if (ret)
79ea13c9eeSMugunthan V N 			return ret;
80ea13c9eeSMugunthan V N 		value = phy_read(phydev, AT803X_INTR_STATUS);
81ea13c9eeSMugunthan V N 	}
82ea13c9eeSMugunthan V N 
83ea13c9eeSMugunthan V N 	return ret;
84ea13c9eeSMugunthan V N }
85ea13c9eeSMugunthan V N 
86ea13c9eeSMugunthan V N static void at803x_get_wol(struct phy_device *phydev,
87ea13c9eeSMugunthan V N 			   struct ethtool_wolinfo *wol)
88ea13c9eeSMugunthan V N {
89ea13c9eeSMugunthan V N 	u32 value;
90ea13c9eeSMugunthan V N 
91ea13c9eeSMugunthan V N 	wol->supported = WAKE_MAGIC;
92ea13c9eeSMugunthan V N 	wol->wolopts = 0;
93ea13c9eeSMugunthan V N 
94ea13c9eeSMugunthan V N 	value = phy_read(phydev, AT803X_INTR_ENABLE);
95ea13c9eeSMugunthan V N 	if (value & AT803X_WOL_ENABLE)
96ea13c9eeSMugunthan V N 		wol->wolopts |= WAKE_MAGIC;
970ca7111aSMatus Ujhelyi }
980ca7111aSMatus Ujhelyi 
990ca7111aSMatus Ujhelyi static int at803x_config_init(struct phy_device *phydev)
1000ca7111aSMatus Ujhelyi {
1010ca7111aSMatus Ujhelyi 	int val;
1020ca7111aSMatus Ujhelyi 	u32 features;
1030ca7111aSMatus Ujhelyi 
1040ca7111aSMatus Ujhelyi 	features = SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI |
1050ca7111aSMatus Ujhelyi 		   SUPPORTED_FIBRE | SUPPORTED_BNC;
1060ca7111aSMatus Ujhelyi 
1070ca7111aSMatus Ujhelyi 	val = phy_read(phydev, MII_BMSR);
1080ca7111aSMatus Ujhelyi 	if (val < 0)
1090ca7111aSMatus Ujhelyi 		return val;
1100ca7111aSMatus Ujhelyi 
1110ca7111aSMatus Ujhelyi 	if (val & BMSR_ANEGCAPABLE)
1120ca7111aSMatus Ujhelyi 		features |= SUPPORTED_Autoneg;
1130ca7111aSMatus Ujhelyi 	if (val & BMSR_100FULL)
1140ca7111aSMatus Ujhelyi 		features |= SUPPORTED_100baseT_Full;
1150ca7111aSMatus Ujhelyi 	if (val & BMSR_100HALF)
1160ca7111aSMatus Ujhelyi 		features |= SUPPORTED_100baseT_Half;
1170ca7111aSMatus Ujhelyi 	if (val & BMSR_10FULL)
1180ca7111aSMatus Ujhelyi 		features |= SUPPORTED_10baseT_Full;
1190ca7111aSMatus Ujhelyi 	if (val & BMSR_10HALF)
1200ca7111aSMatus Ujhelyi 		features |= SUPPORTED_10baseT_Half;
1210ca7111aSMatus Ujhelyi 
1220ca7111aSMatus Ujhelyi 	if (val & BMSR_ESTATEN) {
1230ca7111aSMatus Ujhelyi 		val = phy_read(phydev, MII_ESTATUS);
1240ca7111aSMatus Ujhelyi 		if (val < 0)
1250ca7111aSMatus Ujhelyi 			return val;
1260ca7111aSMatus Ujhelyi 
1270ca7111aSMatus Ujhelyi 		if (val & ESTATUS_1000_TFULL)
1280ca7111aSMatus Ujhelyi 			features |= SUPPORTED_1000baseT_Full;
1290ca7111aSMatus Ujhelyi 		if (val & ESTATUS_1000_THALF)
1300ca7111aSMatus Ujhelyi 			features |= SUPPORTED_1000baseT_Half;
1310ca7111aSMatus Ujhelyi 	}
1320ca7111aSMatus Ujhelyi 
1330ca7111aSMatus Ujhelyi 	phydev->supported = features;
1340ca7111aSMatus Ujhelyi 	phydev->advertising = features;
1350ca7111aSMatus Ujhelyi 
1360ca7111aSMatus Ujhelyi 	return 0;
1370ca7111aSMatus Ujhelyi }
1380ca7111aSMatus Ujhelyi 
139317420abSMugunthan V N static struct phy_driver at803x_driver[] = {
140317420abSMugunthan V N {
1410ca7111aSMatus Ujhelyi 	/* ATHEROS 8035 */
1420ca7111aSMatus Ujhelyi 	.phy_id		= 0x004dd072,
1430ca7111aSMatus Ujhelyi 	.name		= "Atheros 8035 ethernet",
1440ca7111aSMatus Ujhelyi 	.phy_id_mask	= 0xffffffef,
1450ca7111aSMatus Ujhelyi 	.config_init	= at803x_config_init,
146ea13c9eeSMugunthan V N 	.set_wol	= at803x_set_wol,
147ea13c9eeSMugunthan V N 	.get_wol	= at803x_get_wol,
1480ca7111aSMatus Ujhelyi 	.features	= PHY_GBIT_FEATURES,
1490ca7111aSMatus Ujhelyi 	.flags		= PHY_HAS_INTERRUPT,
1500ca7111aSMatus Ujhelyi 	.config_aneg	= &genphy_config_aneg,
1510ca7111aSMatus Ujhelyi 	.read_status	= &genphy_read_status,
1520ca7111aSMatus Ujhelyi 	.driver		= {
1530ca7111aSMatus Ujhelyi 		.owner = THIS_MODULE,
1540ca7111aSMatus Ujhelyi 	},
155317420abSMugunthan V N }, {
1560ca7111aSMatus Ujhelyi 	/* ATHEROS 8030 */
1570ca7111aSMatus Ujhelyi 	.phy_id		= 0x004dd076,
1580ca7111aSMatus Ujhelyi 	.name		= "Atheros 8030 ethernet",
1590ca7111aSMatus Ujhelyi 	.phy_id_mask	= 0xffffffef,
1600ca7111aSMatus Ujhelyi 	.config_init	= at803x_config_init,
161ea13c9eeSMugunthan V N 	.set_wol	= at803x_set_wol,
162ea13c9eeSMugunthan V N 	.get_wol	= at803x_get_wol,
1630ca7111aSMatus Ujhelyi 	.features	= PHY_GBIT_FEATURES,
1640ca7111aSMatus Ujhelyi 	.flags		= PHY_HAS_INTERRUPT,
1650ca7111aSMatus Ujhelyi 	.config_aneg	= &genphy_config_aneg,
1660ca7111aSMatus Ujhelyi 	.read_status	= &genphy_read_status,
1670ca7111aSMatus Ujhelyi 	.driver		= {
1680ca7111aSMatus Ujhelyi 		.owner = THIS_MODULE,
1690ca7111aSMatus Ujhelyi 	},
170317420abSMugunthan V N } };
1710ca7111aSMatus Ujhelyi 
1720ca7111aSMatus Ujhelyi static int __init atheros_init(void)
1730ca7111aSMatus Ujhelyi {
174317420abSMugunthan V N 	return phy_drivers_register(at803x_driver,
175317420abSMugunthan V N 				    ARRAY_SIZE(at803x_driver));
1760ca7111aSMatus Ujhelyi }
1770ca7111aSMatus Ujhelyi 
1780ca7111aSMatus Ujhelyi static void __exit atheros_exit(void)
1790ca7111aSMatus Ujhelyi {
180317420abSMugunthan V N 	return phy_drivers_unregister(at803x_driver,
181317420abSMugunthan V N 				      ARRAY_SIZE(at803x_driver));
1820ca7111aSMatus Ujhelyi }
1830ca7111aSMatus Ujhelyi 
1840ca7111aSMatus Ujhelyi module_init(atheros_init);
1850ca7111aSMatus Ujhelyi module_exit(atheros_exit);
1860ca7111aSMatus Ujhelyi 
1870ca7111aSMatus Ujhelyi static struct mdio_device_id __maybe_unused atheros_tbl[] = {
1880ca7111aSMatus Ujhelyi 	{ 0x004dd076, 0xffffffef },
1890ca7111aSMatus Ujhelyi 	{ 0x004dd072, 0xffffffef },
1900ca7111aSMatus Ujhelyi 	{ }
1910ca7111aSMatus Ujhelyi };
1920ca7111aSMatus Ujhelyi 
1930ca7111aSMatus Ujhelyi MODULE_DEVICE_TABLE(mdio, atheros_tbl);
194