1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 20ca7111aSMatus Ujhelyi /* 30ca7111aSMatus Ujhelyi * drivers/net/phy/at803x.c 40ca7111aSMatus Ujhelyi * 596c36712SMichael Walle * Driver for Qualcomm Atheros AR803x PHY 60ca7111aSMatus Ujhelyi * 70ca7111aSMatus Ujhelyi * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 80ca7111aSMatus Ujhelyi */ 90ca7111aSMatus Ujhelyi 100ca7111aSMatus Ujhelyi #include <linux/phy.h> 110ca7111aSMatus Ujhelyi #include <linux/module.h> 120ca7111aSMatus Ujhelyi #include <linux/string.h> 130ca7111aSMatus Ujhelyi #include <linux/netdevice.h> 140ca7111aSMatus Ujhelyi #include <linux/etherdevice.h> 1513a56b44SDaniel Mack #include <linux/of_gpio.h> 162f664823SMichael Walle #include <linux/bitfield.h> 1713a56b44SDaniel Mack #include <linux/gpio/consumer.h> 182f664823SMichael Walle #include <linux/regulator/of_regulator.h> 192f664823SMichael Walle #include <linux/regulator/driver.h> 202f664823SMichael Walle #include <linux/regulator/consumer.h> 212f664823SMichael Walle #include <dt-bindings/net/qca-ar803x.h> 220ca7111aSMatus Ujhelyi 2306d5f344SRussell King #define AT803X_SPECIFIC_STATUS 0x11 2406d5f344SRussell King #define AT803X_SS_SPEED_MASK (3 << 14) 2506d5f344SRussell King #define AT803X_SS_SPEED_1000 (2 << 14) 2606d5f344SRussell King #define AT803X_SS_SPEED_100 (1 << 14) 2706d5f344SRussell King #define AT803X_SS_SPEED_10 (0 << 14) 2806d5f344SRussell King #define AT803X_SS_DUPLEX BIT(13) 2906d5f344SRussell King #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 3006d5f344SRussell King #define AT803X_SS_MDIX BIT(6) 3106d5f344SRussell King 320ca7111aSMatus Ujhelyi #define AT803X_INTR_ENABLE 0x12 33e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 34e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 35e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 36e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 37e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 38e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 39e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 40e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 41e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WOL BIT(0) 42e6e4a556SMartin Blumenstingl 430ca7111aSMatus Ujhelyi #define AT803X_INTR_STATUS 0x13 44a46bd63bSMartin Blumenstingl 4513a56b44SDaniel Mack #define AT803X_SMART_SPEED 0x14 46cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_ENABLE BIT(5) 47cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 48cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 4913a56b44SDaniel Mack #define AT803X_LED_CONTROL 0x18 50a46bd63bSMartin Blumenstingl 510ca7111aSMatus Ujhelyi #define AT803X_DEVICE_ADDR 0x03 520ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 530ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 540ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 55f62265b5SZefir Kurtisi #define AT803X_REG_CHIP_CONFIG 0x1f 56f62265b5SZefir Kurtisi #define AT803X_BT_BX_REG_SEL 0x8000 57a46bd63bSMartin Blumenstingl 581ca6d1b1SMugunthan V N #define AT803X_DEBUG_ADDR 0x1D 591ca6d1b1SMugunthan V N #define AT803X_DEBUG_DATA 0x1E 60a46bd63bSMartin Blumenstingl 61f62265b5SZefir Kurtisi #define AT803X_MODE_CFG_MASK 0x0F 62f62265b5SZefir Kurtisi #define AT803X_MODE_CFG_SGMII 0x01 63f62265b5SZefir Kurtisi 64f62265b5SZefir Kurtisi #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 65f62265b5SZefir Kurtisi #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 66f62265b5SZefir Kurtisi 672e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_REG_0 0x00 682e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 69a46bd63bSMartin Blumenstingl 702e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_REG_5 0x05 712e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 720ca7111aSMatus Ujhelyi 732f664823SMichael Walle #define AT803X_DEBUG_REG_1F 0x1F 742f664823SMichael Walle #define AT803X_DEBUG_PLL_ON BIT(2) 752f664823SMichael Walle #define AT803X_DEBUG_RGMII_1V8 BIT(3) 762f664823SMichael Walle 772f664823SMichael Walle /* AT803x supports either the XTAL input pad, an internal PLL or the 782f664823SMichael Walle * DSP as clock reference for the clock output pad. The XTAL reference 792f664823SMichael Walle * is only used for 25 MHz output, all other frequencies need the PLL. 802f664823SMichael Walle * The DSP as a clock reference is used in synchronous ethernet 812f664823SMichael Walle * applications. 822f664823SMichael Walle * 832f664823SMichael Walle * By default the PLL is only enabled if there is a link. Otherwise 842f664823SMichael Walle * the PHY will go into low power state and disabled the PLL. You can 852f664823SMichael Walle * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 862f664823SMichael Walle * enabled. 872f664823SMichael Walle */ 882f664823SMichael Walle #define AT803X_MMD7_CLK25M 0x8016 892f664823SMichael Walle #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 902f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_XTAL 0 912f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_DSP 1 922f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_PLL 2 932f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_DSP 3 942f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_PLL 4 952f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_DSP 5 962f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_PLL 6 972f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_DSP 7 982f664823SMichael Walle 99428061f7SMichael Walle /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 100428061f7SMichael Walle * but doesn't support choosing between XTAL/PLL and DSP. 1012f664823SMichael Walle */ 1022f664823SMichael Walle #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 1032f664823SMichael Walle 1042f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 1052f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_FULL 0 1062f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_HALF 1 1072f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 1082f664823SMichael Walle 109cde0f4f8SMichael Walle #define AT803X_DEFAULT_DOWNSHIFT 5 110cde0f4f8SMichael Walle #define AT803X_MIN_DOWNSHIFT 2 111cde0f4f8SMichael Walle #define AT803X_MAX_DOWNSHIFT 9 112cde0f4f8SMichael Walle 1137908d2ceSOleksij Rempel #define ATH9331_PHY_ID 0x004dd041 114bd8ca17fSDaniel Mack #define ATH8030_PHY_ID 0x004dd076 115bd8ca17fSDaniel Mack #define ATH8031_PHY_ID 0x004dd074 1165800091aSDavid Bauer #define ATH8032_PHY_ID 0x004dd023 117bd8ca17fSDaniel Mack #define ATH8035_PHY_ID 0x004dd072 11858effd71SFabio Estevam #define AT803X_PHY_ID_MASK 0xffffffef 119bd8ca17fSDaniel Mack 12096c36712SMichael Walle MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); 1210ca7111aSMatus Ujhelyi MODULE_AUTHOR("Matus Ujhelyi"); 1220ca7111aSMatus Ujhelyi MODULE_LICENSE("GPL"); 1230ca7111aSMatus Ujhelyi 1242f664823SMichael Walle struct at803x_priv { 1252f664823SMichael Walle int flags; 1262f664823SMichael Walle #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ 1272f664823SMichael Walle u16 clk_25m_reg; 1282f664823SMichael Walle u16 clk_25m_mask; 1292f664823SMichael Walle struct regulator_dev *vddio_rdev; 1302f664823SMichael Walle struct regulator_dev *vddh_rdev; 1312f664823SMichael Walle struct regulator *vddio; 1322f664823SMichael Walle }; 1332f664823SMichael Walle 13413a56b44SDaniel Mack struct at803x_context { 13513a56b44SDaniel Mack u16 bmcr; 13613a56b44SDaniel Mack u16 advertise; 13713a56b44SDaniel Mack u16 control1000; 13813a56b44SDaniel Mack u16 int_enable; 13913a56b44SDaniel Mack u16 smart_speed; 14013a56b44SDaniel Mack u16 led_control; 14113a56b44SDaniel Mack }; 14213a56b44SDaniel Mack 1432e5f9f28SMartin Blumenstingl static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 1442e5f9f28SMartin Blumenstingl { 1452e5f9f28SMartin Blumenstingl int ret; 1462e5f9f28SMartin Blumenstingl 1472e5f9f28SMartin Blumenstingl ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 1482e5f9f28SMartin Blumenstingl if (ret < 0) 1492e5f9f28SMartin Blumenstingl return ret; 1502e5f9f28SMartin Blumenstingl 1512e5f9f28SMartin Blumenstingl return phy_read(phydev, AT803X_DEBUG_DATA); 1522e5f9f28SMartin Blumenstingl } 1532e5f9f28SMartin Blumenstingl 1542e5f9f28SMartin Blumenstingl static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 1552e5f9f28SMartin Blumenstingl u16 clear, u16 set) 1562e5f9f28SMartin Blumenstingl { 1572e5f9f28SMartin Blumenstingl u16 val; 1582e5f9f28SMartin Blumenstingl int ret; 1592e5f9f28SMartin Blumenstingl 1602e5f9f28SMartin Blumenstingl ret = at803x_debug_reg_read(phydev, reg); 1612e5f9f28SMartin Blumenstingl if (ret < 0) 1622e5f9f28SMartin Blumenstingl return ret; 1632e5f9f28SMartin Blumenstingl 1642e5f9f28SMartin Blumenstingl val = ret & 0xffff; 1652e5f9f28SMartin Blumenstingl val &= ~clear; 1662e5f9f28SMartin Blumenstingl val |= set; 1672e5f9f28SMartin Blumenstingl 1682e5f9f28SMartin Blumenstingl return phy_write(phydev, AT803X_DEBUG_DATA, val); 1692e5f9f28SMartin Blumenstingl } 1702e5f9f28SMartin Blumenstingl 1716d4cd041SVinod Koul static int at803x_enable_rx_delay(struct phy_device *phydev) 1726d4cd041SVinod Koul { 1736d4cd041SVinod Koul return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, 1746d4cd041SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN); 1756d4cd041SVinod Koul } 1766d4cd041SVinod Koul 1776d4cd041SVinod Koul static int at803x_enable_tx_delay(struct phy_device *phydev) 1786d4cd041SVinod Koul { 1796d4cd041SVinod Koul return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, 1806d4cd041SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN); 1816d4cd041SVinod Koul } 1826d4cd041SVinod Koul 18343f2ebd5SVinod Koul static int at803x_disable_rx_delay(struct phy_device *phydev) 1842e5f9f28SMartin Blumenstingl { 185cd28d1d6SVinod Koul return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 186cd28d1d6SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN, 0); 1872e5f9f28SMartin Blumenstingl } 1882e5f9f28SMartin Blumenstingl 18943f2ebd5SVinod Koul static int at803x_disable_tx_delay(struct phy_device *phydev) 1902e5f9f28SMartin Blumenstingl { 191cd28d1d6SVinod Koul return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 192cd28d1d6SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN, 0); 1932e5f9f28SMartin Blumenstingl } 1942e5f9f28SMartin Blumenstingl 19513a56b44SDaniel Mack /* save relevant PHY registers to private copy */ 19613a56b44SDaniel Mack static void at803x_context_save(struct phy_device *phydev, 19713a56b44SDaniel Mack struct at803x_context *context) 19813a56b44SDaniel Mack { 19913a56b44SDaniel Mack context->bmcr = phy_read(phydev, MII_BMCR); 20013a56b44SDaniel Mack context->advertise = phy_read(phydev, MII_ADVERTISE); 20113a56b44SDaniel Mack context->control1000 = phy_read(phydev, MII_CTRL1000); 20213a56b44SDaniel Mack context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 20313a56b44SDaniel Mack context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 20413a56b44SDaniel Mack context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 20513a56b44SDaniel Mack } 20613a56b44SDaniel Mack 20713a56b44SDaniel Mack /* restore relevant PHY registers from private copy */ 20813a56b44SDaniel Mack static void at803x_context_restore(struct phy_device *phydev, 20913a56b44SDaniel Mack const struct at803x_context *context) 21013a56b44SDaniel Mack { 21113a56b44SDaniel Mack phy_write(phydev, MII_BMCR, context->bmcr); 21213a56b44SDaniel Mack phy_write(phydev, MII_ADVERTISE, context->advertise); 21313a56b44SDaniel Mack phy_write(phydev, MII_CTRL1000, context->control1000); 21413a56b44SDaniel Mack phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 21513a56b44SDaniel Mack phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 21613a56b44SDaniel Mack phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 21713a56b44SDaniel Mack } 21813a56b44SDaniel Mack 219ea13c9eeSMugunthan V N static int at803x_set_wol(struct phy_device *phydev, 220ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 2210ca7111aSMatus Ujhelyi { 2220ca7111aSMatus Ujhelyi struct net_device *ndev = phydev->attached_dev; 2230ca7111aSMatus Ujhelyi const u8 *mac; 224ea13c9eeSMugunthan V N int ret; 225ea13c9eeSMugunthan V N u32 value; 2260ca7111aSMatus Ujhelyi unsigned int i, offsets[] = { 2270ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_32_47_OFFSET, 2280ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_16_31_OFFSET, 2290ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_0_15_OFFSET, 2300ca7111aSMatus Ujhelyi }; 2310ca7111aSMatus Ujhelyi 2320ca7111aSMatus Ujhelyi if (!ndev) 233ea13c9eeSMugunthan V N return -ENODEV; 2340ca7111aSMatus Ujhelyi 235ea13c9eeSMugunthan V N if (wol->wolopts & WAKE_MAGIC) { 2360ca7111aSMatus Ujhelyi mac = (const u8 *) ndev->dev_addr; 2370ca7111aSMatus Ujhelyi 2380ca7111aSMatus Ujhelyi if (!is_valid_ether_addr(mac)) 239fc755687SDan Murphy return -EINVAL; 2400ca7111aSMatus Ujhelyi 2410e021396SCarlo Caione for (i = 0; i < 3; i++) 2420e021396SCarlo Caione phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i], 2430ca7111aSMatus Ujhelyi mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 244ea13c9eeSMugunthan V N 245ea13c9eeSMugunthan V N value = phy_read(phydev, AT803X_INTR_ENABLE); 246e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_WOL; 247ea13c9eeSMugunthan V N ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 248ea13c9eeSMugunthan V N if (ret) 249ea13c9eeSMugunthan V N return ret; 250ea13c9eeSMugunthan V N value = phy_read(phydev, AT803X_INTR_STATUS); 251ea13c9eeSMugunthan V N } else { 252ea13c9eeSMugunthan V N value = phy_read(phydev, AT803X_INTR_ENABLE); 253e6e4a556SMartin Blumenstingl value &= (~AT803X_INTR_ENABLE_WOL); 254ea13c9eeSMugunthan V N ret = phy_write(phydev, AT803X_INTR_ENABLE, value); 255ea13c9eeSMugunthan V N if (ret) 256ea13c9eeSMugunthan V N return ret; 257ea13c9eeSMugunthan V N value = phy_read(phydev, AT803X_INTR_STATUS); 258ea13c9eeSMugunthan V N } 259ea13c9eeSMugunthan V N 260ea13c9eeSMugunthan V N return ret; 261ea13c9eeSMugunthan V N } 262ea13c9eeSMugunthan V N 263ea13c9eeSMugunthan V N static void at803x_get_wol(struct phy_device *phydev, 264ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 265ea13c9eeSMugunthan V N { 266ea13c9eeSMugunthan V N u32 value; 267ea13c9eeSMugunthan V N 268ea13c9eeSMugunthan V N wol->supported = WAKE_MAGIC; 269ea13c9eeSMugunthan V N wol->wolopts = 0; 270ea13c9eeSMugunthan V N 271ea13c9eeSMugunthan V N value = phy_read(phydev, AT803X_INTR_ENABLE); 272e6e4a556SMartin Blumenstingl if (value & AT803X_INTR_ENABLE_WOL) 273ea13c9eeSMugunthan V N wol->wolopts |= WAKE_MAGIC; 2740ca7111aSMatus Ujhelyi } 2750ca7111aSMatus Ujhelyi 2766229ed1fSDaniel Mack static int at803x_suspend(struct phy_device *phydev) 2776229ed1fSDaniel Mack { 2786229ed1fSDaniel Mack int value; 2796229ed1fSDaniel Mack int wol_enabled; 2806229ed1fSDaniel Mack 2816229ed1fSDaniel Mack value = phy_read(phydev, AT803X_INTR_ENABLE); 282e6e4a556SMartin Blumenstingl wol_enabled = value & AT803X_INTR_ENABLE_WOL; 2836229ed1fSDaniel Mack 2846229ed1fSDaniel Mack if (wol_enabled) 285fea23fb5SRussell King value = BMCR_ISOLATE; 2866229ed1fSDaniel Mack else 287fea23fb5SRussell King value = BMCR_PDOWN; 2886229ed1fSDaniel Mack 289fea23fb5SRussell King phy_modify(phydev, MII_BMCR, 0, value); 2906229ed1fSDaniel Mack 2916229ed1fSDaniel Mack return 0; 2926229ed1fSDaniel Mack } 2936229ed1fSDaniel Mack 2946229ed1fSDaniel Mack static int at803x_resume(struct phy_device *phydev) 2956229ed1fSDaniel Mack { 296f102852fSRussell King return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 2976229ed1fSDaniel Mack } 2986229ed1fSDaniel Mack 2992f664823SMichael Walle static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 3002f664823SMichael Walle unsigned int selector) 3012f664823SMichael Walle { 3022f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 3032f664823SMichael Walle 3042f664823SMichael Walle if (selector) 3052f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 3062f664823SMichael Walle 0, AT803X_DEBUG_RGMII_1V8); 3072f664823SMichael Walle else 3082f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 3092f664823SMichael Walle AT803X_DEBUG_RGMII_1V8, 0); 3102f664823SMichael Walle } 3112f664823SMichael Walle 3122f664823SMichael Walle static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 3132f664823SMichael Walle { 3142f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 3152f664823SMichael Walle int val; 3162f664823SMichael Walle 3172f664823SMichael Walle val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 3182f664823SMichael Walle if (val < 0) 3192f664823SMichael Walle return val; 3202f664823SMichael Walle 3212f664823SMichael Walle return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 3222f664823SMichael Walle } 3232f664823SMichael Walle 3242f664823SMichael Walle static struct regulator_ops vddio_regulator_ops = { 3252f664823SMichael Walle .list_voltage = regulator_list_voltage_table, 3262f664823SMichael Walle .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 3272f664823SMichael Walle .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 3282f664823SMichael Walle }; 3292f664823SMichael Walle 3302f664823SMichael Walle static const unsigned int vddio_voltage_table[] = { 3312f664823SMichael Walle 1500000, 3322f664823SMichael Walle 1800000, 3332f664823SMichael Walle }; 3342f664823SMichael Walle 3352f664823SMichael Walle static const struct regulator_desc vddio_desc = { 3362f664823SMichael Walle .name = "vddio", 3372f664823SMichael Walle .of_match = of_match_ptr("vddio-regulator"), 3382f664823SMichael Walle .n_voltages = ARRAY_SIZE(vddio_voltage_table), 3392f664823SMichael Walle .volt_table = vddio_voltage_table, 3402f664823SMichael Walle .ops = &vddio_regulator_ops, 3412f664823SMichael Walle .type = REGULATOR_VOLTAGE, 3422f664823SMichael Walle .owner = THIS_MODULE, 3432f664823SMichael Walle }; 3442f664823SMichael Walle 3452f664823SMichael Walle static struct regulator_ops vddh_regulator_ops = { 3462f664823SMichael Walle }; 3472f664823SMichael Walle 3482f664823SMichael Walle static const struct regulator_desc vddh_desc = { 3492f664823SMichael Walle .name = "vddh", 3502f664823SMichael Walle .of_match = of_match_ptr("vddh-regulator"), 3512f664823SMichael Walle .n_voltages = 1, 3522f664823SMichael Walle .fixed_uV = 2500000, 3532f664823SMichael Walle .ops = &vddh_regulator_ops, 3542f664823SMichael Walle .type = REGULATOR_VOLTAGE, 3552f664823SMichael Walle .owner = THIS_MODULE, 3562f664823SMichael Walle }; 3572f664823SMichael Walle 3582f664823SMichael Walle static int at8031_register_regulators(struct phy_device *phydev) 3592f664823SMichael Walle { 3602f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 3612f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 3622f664823SMichael Walle struct regulator_config config = { }; 3632f664823SMichael Walle 3642f664823SMichael Walle config.dev = dev; 3652f664823SMichael Walle config.driver_data = phydev; 3662f664823SMichael Walle 3672f664823SMichael Walle priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 3682f664823SMichael Walle if (IS_ERR(priv->vddio_rdev)) { 3692f664823SMichael Walle phydev_err(phydev, "failed to register VDDIO regulator\n"); 3702f664823SMichael Walle return PTR_ERR(priv->vddio_rdev); 3712f664823SMichael Walle } 3722f664823SMichael Walle 3732f664823SMichael Walle priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 3742f664823SMichael Walle if (IS_ERR(priv->vddh_rdev)) { 3752f664823SMichael Walle phydev_err(phydev, "failed to register VDDH regulator\n"); 3762f664823SMichael Walle return PTR_ERR(priv->vddh_rdev); 3772f664823SMichael Walle } 3782f664823SMichael Walle 3792f664823SMichael Walle return 0; 3802f664823SMichael Walle } 3812f664823SMichael Walle 3822f664823SMichael Walle static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id) 3832f664823SMichael Walle { 3842f664823SMichael Walle return (phydev->phy_id & phydev->drv->phy_id_mask) 3852f664823SMichael Walle == (phy_id & phydev->drv->phy_id_mask); 3862f664823SMichael Walle } 3872f664823SMichael Walle 3882f664823SMichael Walle static int at803x_parse_dt(struct phy_device *phydev) 3892f664823SMichael Walle { 3902f664823SMichael Walle struct device_node *node = phydev->mdio.dev.of_node; 3912f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 3922f664823SMichael Walle unsigned int sel, mask; 3932f664823SMichael Walle u32 freq, strength; 3942f664823SMichael Walle int ret; 3952f664823SMichael Walle 3962f664823SMichael Walle if (!IS_ENABLED(CONFIG_OF_MDIO)) 3972f664823SMichael Walle return 0; 3982f664823SMichael Walle 3992f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 4002f664823SMichael Walle if (!ret) { 4012f664823SMichael Walle mask = AT803X_CLK_OUT_MASK; 4022f664823SMichael Walle switch (freq) { 4032f664823SMichael Walle case 25000000: 4042f664823SMichael Walle sel = AT803X_CLK_OUT_25MHZ_XTAL; 4052f664823SMichael Walle break; 4062f664823SMichael Walle case 50000000: 4072f664823SMichael Walle sel = AT803X_CLK_OUT_50MHZ_PLL; 4082f664823SMichael Walle break; 4092f664823SMichael Walle case 62500000: 4102f664823SMichael Walle sel = AT803X_CLK_OUT_62_5MHZ_PLL; 4112f664823SMichael Walle break; 4122f664823SMichael Walle case 125000000: 4132f664823SMichael Walle sel = AT803X_CLK_OUT_125MHZ_PLL; 4142f664823SMichael Walle break; 4152f664823SMichael Walle default: 4162f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 4172f664823SMichael Walle return -EINVAL; 4182f664823SMichael Walle } 4192f664823SMichael Walle 4202f664823SMichael Walle priv->clk_25m_reg |= FIELD_PREP(mask, sel); 4212f664823SMichael Walle priv->clk_25m_mask |= mask; 4222f664823SMichael Walle 4232f664823SMichael Walle /* Fixup for the AR8030/AR8035. This chip has another mask and 4242f664823SMichael Walle * doesn't support the DSP reference. Eg. the lowest bit of the 4252f664823SMichael Walle * mask. The upper two bits select the same frequencies. Mask 4262f664823SMichael Walle * the lowest bit here. 4272f664823SMichael Walle * 4282f664823SMichael Walle * Warning: 4292f664823SMichael Walle * There was no datasheet for the AR8030 available so this is 4302f664823SMichael Walle * just a guess. But the AR8035 is listed as pin compatible 4312f664823SMichael Walle * to the AR8030 so there might be a good chance it works on 4322f664823SMichael Walle * the AR8030 too. 4332f664823SMichael Walle */ 4342f664823SMichael Walle if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) || 4352f664823SMichael Walle at803x_match_phy_id(phydev, ATH8035_PHY_ID)) { 436b1f4c209SOleksij Rempel priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 437b1f4c209SOleksij Rempel priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 4382f664823SMichael Walle } 4392f664823SMichael Walle } 4402f664823SMichael Walle 4412f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 4422f664823SMichael Walle if (!ret) { 4432f664823SMichael Walle priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 4442f664823SMichael Walle switch (strength) { 4452f664823SMichael Walle case AR803X_STRENGTH_FULL: 4462f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 4472f664823SMichael Walle break; 4482f664823SMichael Walle case AR803X_STRENGTH_HALF: 4492f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 4502f664823SMichael Walle break; 4512f664823SMichael Walle case AR803X_STRENGTH_QUARTER: 4522f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 4532f664823SMichael Walle break; 4542f664823SMichael Walle default: 4552f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-strength\n"); 4562f664823SMichael Walle return -EINVAL; 4572f664823SMichael Walle } 4582f664823SMichael Walle } 4592f664823SMichael Walle 460428061f7SMichael Walle /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 461428061f7SMichael Walle * options. 462428061f7SMichael Walle */ 4632f664823SMichael Walle if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 4642f664823SMichael Walle if (of_property_read_bool(node, "qca,keep-pll-enabled")) 4652f664823SMichael Walle priv->flags |= AT803X_KEEP_PLL_ENABLED; 4662f664823SMichael Walle 4672f664823SMichael Walle ret = at8031_register_regulators(phydev); 4682f664823SMichael Walle if (ret < 0) 4692f664823SMichael Walle return ret; 4702f664823SMichael Walle 4712f664823SMichael Walle priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 4722f664823SMichael Walle "vddio"); 4732f664823SMichael Walle if (IS_ERR(priv->vddio)) { 4742f664823SMichael Walle phydev_err(phydev, "failed to get VDDIO regulator\n"); 4752f664823SMichael Walle return PTR_ERR(priv->vddio); 4762f664823SMichael Walle } 4772f664823SMichael Walle 4782f664823SMichael Walle ret = regulator_enable(priv->vddio); 4792f664823SMichael Walle if (ret < 0) 4802f664823SMichael Walle return ret; 4812f664823SMichael Walle } 4822f664823SMichael Walle 4832f664823SMichael Walle return 0; 4842f664823SMichael Walle } 4852f664823SMichael Walle 4862f664823SMichael Walle static int at803x_probe(struct phy_device *phydev) 4872f664823SMichael Walle { 4882f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 4892f664823SMichael Walle struct at803x_priv *priv; 4902f664823SMichael Walle 4912f664823SMichael Walle priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 4922f664823SMichael Walle if (!priv) 4932f664823SMichael Walle return -ENOMEM; 4942f664823SMichael Walle 4952f664823SMichael Walle phydev->priv = priv; 4962f664823SMichael Walle 4972f664823SMichael Walle return at803x_parse_dt(phydev); 4982f664823SMichael Walle } 4992f664823SMichael Walle 5002318ca8aSMichael Walle static void at803x_remove(struct phy_device *phydev) 5012318ca8aSMichael Walle { 5022318ca8aSMichael Walle struct at803x_priv *priv = phydev->priv; 5032318ca8aSMichael Walle 5042318ca8aSMichael Walle if (priv->vddio) 5052318ca8aSMichael Walle regulator_disable(priv->vddio); 5062318ca8aSMichael Walle } 5072318ca8aSMichael Walle 5082f664823SMichael Walle static int at803x_clk_out_config(struct phy_device *phydev) 5092f664823SMichael Walle { 5102f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 5112f664823SMichael Walle int val; 5122f664823SMichael Walle 5132f664823SMichael Walle if (!priv->clk_25m_mask) 5142f664823SMichael Walle return 0; 5152f664823SMichael Walle 5162f664823SMichael Walle val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M); 5172f664823SMichael Walle if (val < 0) 5182f664823SMichael Walle return val; 5192f664823SMichael Walle 5202f664823SMichael Walle val &= ~priv->clk_25m_mask; 5212f664823SMichael Walle val |= priv->clk_25m_reg; 5222f664823SMichael Walle 5232f664823SMichael Walle return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val); 5242f664823SMichael Walle } 5252f664823SMichael Walle 5262f664823SMichael Walle static int at8031_pll_config(struct phy_device *phydev) 5272f664823SMichael Walle { 5282f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 5292f664823SMichael Walle 5302f664823SMichael Walle /* The default after hardware reset is PLL OFF. After a soft reset, the 5312f664823SMichael Walle * values are retained. 5322f664823SMichael Walle */ 5332f664823SMichael Walle if (priv->flags & AT803X_KEEP_PLL_ENABLED) 5342f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 5352f664823SMichael Walle 0, AT803X_DEBUG_PLL_ON); 5362f664823SMichael Walle else 5372f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 5382f664823SMichael Walle AT803X_DEBUG_PLL_ON, 0); 5392f664823SMichael Walle } 5402f664823SMichael Walle 5410ca7111aSMatus Ujhelyi static int at803x_config_init(struct phy_device *phydev) 5420ca7111aSMatus Ujhelyi { 5431ca6d1b1SMugunthan V N int ret; 5440ca7111aSMatus Ujhelyi 5456d4cd041SVinod Koul /* The RX and TX delay default is: 5466d4cd041SVinod Koul * after HW reset: RX delay enabled and TX delay disabled 5476d4cd041SVinod Koul * after SW reset: RX delay enabled, while TX delay retains the 5486d4cd041SVinod Koul * value before reset. 5496d4cd041SVinod Koul */ 550bb0ce4c1SAndré Draszik if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 551bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 552bb0ce4c1SAndré Draszik ret = at803x_enable_rx_delay(phydev); 553bb0ce4c1SAndré Draszik else 554cd28d1d6SVinod Koul ret = at803x_disable_rx_delay(phydev); 5552e5f9f28SMartin Blumenstingl if (ret < 0) 5561ca6d1b1SMugunthan V N return ret; 5576d4cd041SVinod Koul 5586d4cd041SVinod Koul if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 559bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 5606d4cd041SVinod Koul ret = at803x_enable_tx_delay(phydev); 561bb0ce4c1SAndré Draszik else 562bb0ce4c1SAndré Draszik ret = at803x_disable_tx_delay(phydev); 5632f664823SMichael Walle if (ret < 0) 5646d4cd041SVinod Koul return ret; 5652f664823SMichael Walle 5662f664823SMichael Walle ret = at803x_clk_out_config(phydev); 5672f664823SMichael Walle if (ret < 0) 5682f664823SMichael Walle return ret; 5692f664823SMichael Walle 5702f664823SMichael Walle if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { 5712f664823SMichael Walle ret = at8031_pll_config(phydev); 5722f664823SMichael Walle if (ret < 0) 5732f664823SMichael Walle return ret; 5742f664823SMichael Walle } 5752f664823SMichael Walle 5762f664823SMichael Walle return 0; 5770ca7111aSMatus Ujhelyi } 5780ca7111aSMatus Ujhelyi 57977a99394SZhao Qiang static int at803x_ack_interrupt(struct phy_device *phydev) 58077a99394SZhao Qiang { 58177a99394SZhao Qiang int err; 58277a99394SZhao Qiang 583a46bd63bSMartin Blumenstingl err = phy_read(phydev, AT803X_INTR_STATUS); 58477a99394SZhao Qiang 58577a99394SZhao Qiang return (err < 0) ? err : 0; 58677a99394SZhao Qiang } 58777a99394SZhao Qiang 58877a99394SZhao Qiang static int at803x_config_intr(struct phy_device *phydev) 58977a99394SZhao Qiang { 59077a99394SZhao Qiang int err; 59177a99394SZhao Qiang int value; 59277a99394SZhao Qiang 593a46bd63bSMartin Blumenstingl value = phy_read(phydev, AT803X_INTR_ENABLE); 59477a99394SZhao Qiang 595e6e4a556SMartin Blumenstingl if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 596e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 597e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 598e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 599e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_FAIL; 600e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 601e6e4a556SMartin Blumenstingl 602e6e4a556SMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, value); 603e6e4a556SMartin Blumenstingl } 60477a99394SZhao Qiang else 605a46bd63bSMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 60677a99394SZhao Qiang 60777a99394SZhao Qiang return err; 60877a99394SZhao Qiang } 60977a99394SZhao Qiang 61013a56b44SDaniel Mack static void at803x_link_change_notify(struct phy_device *phydev) 61113a56b44SDaniel Mack { 61213a56b44SDaniel Mack /* 61313a56b44SDaniel Mack * Conduct a hardware reset for AT8030 every time a link loss is 61413a56b44SDaniel Mack * signalled. This is necessary to circumvent a hardware bug that 61513a56b44SDaniel Mack * occurs when the cable is unplugged while TX packets are pending 61613a56b44SDaniel Mack * in the FIFO. In such cases, the FIFO enters an error mode it 61713a56b44SDaniel Mack * cannot recover from by software. 61813a56b44SDaniel Mack */ 6196110ed2dSDavid Bauer if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 62013a56b44SDaniel Mack struct at803x_context context; 62113a56b44SDaniel Mack 62213a56b44SDaniel Mack at803x_context_save(phydev, &context); 62313a56b44SDaniel Mack 624bafbdd52SSergei Shtylyov phy_device_reset(phydev, 1); 62513a56b44SDaniel Mack msleep(1); 626bafbdd52SSergei Shtylyov phy_device_reset(phydev, 0); 627d57019d1SSergei Shtylyov msleep(1); 62813a56b44SDaniel Mack 62913a56b44SDaniel Mack at803x_context_restore(phydev, &context); 63013a56b44SDaniel Mack 6315c5f626bSHeiner Kallweit phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 63213a56b44SDaniel Mack } 63313a56b44SDaniel Mack } 63413a56b44SDaniel Mack 635f62265b5SZefir Kurtisi static int at803x_aneg_done(struct phy_device *phydev) 636f62265b5SZefir Kurtisi { 637f62265b5SZefir Kurtisi int ccr; 638f62265b5SZefir Kurtisi 639f62265b5SZefir Kurtisi int aneg_done = genphy_aneg_done(phydev); 640f62265b5SZefir Kurtisi if (aneg_done != BMSR_ANEGCOMPLETE) 641f62265b5SZefir Kurtisi return aneg_done; 642f62265b5SZefir Kurtisi 643f62265b5SZefir Kurtisi /* 644f62265b5SZefir Kurtisi * in SGMII mode, if copper side autoneg is successful, 645f62265b5SZefir Kurtisi * also check SGMII side autoneg result 646f62265b5SZefir Kurtisi */ 647f62265b5SZefir Kurtisi ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 648f62265b5SZefir Kurtisi if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII) 649f62265b5SZefir Kurtisi return aneg_done; 650f62265b5SZefir Kurtisi 651f62265b5SZefir Kurtisi /* switch to SGMII/fiber page */ 652f62265b5SZefir Kurtisi phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL); 653f62265b5SZefir Kurtisi 654f62265b5SZefir Kurtisi /* check if the SGMII link is OK. */ 655f62265b5SZefir Kurtisi if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { 656ab2a605fSAndrew Lunn phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); 657f62265b5SZefir Kurtisi aneg_done = 0; 658f62265b5SZefir Kurtisi } 659f62265b5SZefir Kurtisi /* switch back to copper page */ 660f62265b5SZefir Kurtisi phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); 661f62265b5SZefir Kurtisi 662f62265b5SZefir Kurtisi return aneg_done; 663f62265b5SZefir Kurtisi } 664f62265b5SZefir Kurtisi 66506d5f344SRussell King static int at803x_read_status(struct phy_device *phydev) 66606d5f344SRussell King { 66706d5f344SRussell King int ss, err, old_link = phydev->link; 66806d5f344SRussell King 66906d5f344SRussell King /* Update the link, but return if there was an error */ 67006d5f344SRussell King err = genphy_update_link(phydev); 67106d5f344SRussell King if (err) 67206d5f344SRussell King return err; 67306d5f344SRussell King 67406d5f344SRussell King /* why bother the PHY if nothing can have changed */ 67506d5f344SRussell King if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 67606d5f344SRussell King return 0; 67706d5f344SRussell King 67806d5f344SRussell King phydev->speed = SPEED_UNKNOWN; 67906d5f344SRussell King phydev->duplex = DUPLEX_UNKNOWN; 68006d5f344SRussell King phydev->pause = 0; 68106d5f344SRussell King phydev->asym_pause = 0; 68206d5f344SRussell King 68306d5f344SRussell King err = genphy_read_lpa(phydev); 68406d5f344SRussell King if (err < 0) 68506d5f344SRussell King return err; 68606d5f344SRussell King 68706d5f344SRussell King /* Read the AT8035 PHY-Specific Status register, which indicates the 68806d5f344SRussell King * speed and duplex that the PHY is actually using, irrespective of 68906d5f344SRussell King * whether we are in autoneg mode or not. 69006d5f344SRussell King */ 69106d5f344SRussell King ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 69206d5f344SRussell King if (ss < 0) 69306d5f344SRussell King return ss; 69406d5f344SRussell King 69506d5f344SRussell King if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 69606d5f344SRussell King switch (ss & AT803X_SS_SPEED_MASK) { 69706d5f344SRussell King case AT803X_SS_SPEED_10: 69806d5f344SRussell King phydev->speed = SPEED_10; 69906d5f344SRussell King break; 70006d5f344SRussell King case AT803X_SS_SPEED_100: 70106d5f344SRussell King phydev->speed = SPEED_100; 70206d5f344SRussell King break; 70306d5f344SRussell King case AT803X_SS_SPEED_1000: 70406d5f344SRussell King phydev->speed = SPEED_1000; 70506d5f344SRussell King break; 70606d5f344SRussell King } 70706d5f344SRussell King if (ss & AT803X_SS_DUPLEX) 70806d5f344SRussell King phydev->duplex = DUPLEX_FULL; 70906d5f344SRussell King else 71006d5f344SRussell King phydev->duplex = DUPLEX_HALF; 71106d5f344SRussell King if (ss & AT803X_SS_MDIX) 71206d5f344SRussell King phydev->mdix = ETH_TP_MDI_X; 71306d5f344SRussell King else 71406d5f344SRussell King phydev->mdix = ETH_TP_MDI; 71506d5f344SRussell King } 71606d5f344SRussell King 71706d5f344SRussell King if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 71806d5f344SRussell King phy_resolve_aneg_pause(phydev); 71906d5f344SRussell King 72006d5f344SRussell King return 0; 72106d5f344SRussell King } 72206d5f344SRussell King 723cde0f4f8SMichael Walle static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 724cde0f4f8SMichael Walle { 725cde0f4f8SMichael Walle int val; 726cde0f4f8SMichael Walle 727cde0f4f8SMichael Walle val = phy_read(phydev, AT803X_SMART_SPEED); 728cde0f4f8SMichael Walle if (val < 0) 729cde0f4f8SMichael Walle return val; 730cde0f4f8SMichael Walle 731cde0f4f8SMichael Walle if (val & AT803X_SMART_SPEED_ENABLE) 732cde0f4f8SMichael Walle *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 733cde0f4f8SMichael Walle else 734cde0f4f8SMichael Walle *d = DOWNSHIFT_DEV_DISABLE; 735cde0f4f8SMichael Walle 736cde0f4f8SMichael Walle return 0; 737cde0f4f8SMichael Walle } 738cde0f4f8SMichael Walle 739cde0f4f8SMichael Walle static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 740cde0f4f8SMichael Walle { 741cde0f4f8SMichael Walle u16 mask, set; 742cde0f4f8SMichael Walle int ret; 743cde0f4f8SMichael Walle 744cde0f4f8SMichael Walle switch (cnt) { 745cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DEFAULT_COUNT: 746cde0f4f8SMichael Walle cnt = AT803X_DEFAULT_DOWNSHIFT; 747cde0f4f8SMichael Walle fallthrough; 748cde0f4f8SMichael Walle case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 749cde0f4f8SMichael Walle set = AT803X_SMART_SPEED_ENABLE | 750cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER | 751cde0f4f8SMichael Walle FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 752cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 753cde0f4f8SMichael Walle break; 754cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DISABLE: 755cde0f4f8SMichael Walle set = 0; 756cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_ENABLE | 757cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER; 758cde0f4f8SMichael Walle break; 759cde0f4f8SMichael Walle default: 760cde0f4f8SMichael Walle return -EINVAL; 761cde0f4f8SMichael Walle } 762cde0f4f8SMichael Walle 763cde0f4f8SMichael Walle ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 764cde0f4f8SMichael Walle 765cde0f4f8SMichael Walle /* After changing the smart speed settings, we need to perform a 766cde0f4f8SMichael Walle * software reset, use phy_init_hw() to make sure we set the 767cde0f4f8SMichael Walle * reapply any values which might got lost during software reset. 768cde0f4f8SMichael Walle */ 769cde0f4f8SMichael Walle if (ret == 1) 770cde0f4f8SMichael Walle ret = phy_init_hw(phydev); 771cde0f4f8SMichael Walle 772cde0f4f8SMichael Walle return ret; 773cde0f4f8SMichael Walle } 774cde0f4f8SMichael Walle 775cde0f4f8SMichael Walle static int at803x_get_tunable(struct phy_device *phydev, 776cde0f4f8SMichael Walle struct ethtool_tunable *tuna, void *data) 777cde0f4f8SMichael Walle { 778cde0f4f8SMichael Walle switch (tuna->id) { 779cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 780cde0f4f8SMichael Walle return at803x_get_downshift(phydev, data); 781cde0f4f8SMichael Walle default: 782cde0f4f8SMichael Walle return -EOPNOTSUPP; 783cde0f4f8SMichael Walle } 784cde0f4f8SMichael Walle } 785cde0f4f8SMichael Walle 786cde0f4f8SMichael Walle static int at803x_set_tunable(struct phy_device *phydev, 787cde0f4f8SMichael Walle struct ethtool_tunable *tuna, const void *data) 788cde0f4f8SMichael Walle { 789cde0f4f8SMichael Walle switch (tuna->id) { 790cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 791cde0f4f8SMichael Walle return at803x_set_downshift(phydev, *(const u8 *)data); 792cde0f4f8SMichael Walle default: 793cde0f4f8SMichael Walle return -EOPNOTSUPP; 794cde0f4f8SMichael Walle } 795cde0f4f8SMichael Walle } 796cde0f4f8SMichael Walle 797317420abSMugunthan V N static struct phy_driver at803x_driver[] = { 798317420abSMugunthan V N { 79996c36712SMichael Walle /* Qualcomm Atheros AR8035 */ 800bd8ca17fSDaniel Mack .phy_id = ATH8035_PHY_ID, 80196c36712SMichael Walle .name = "Qualcomm Atheros AR8035", 80258effd71SFabio Estevam .phy_id_mask = AT803X_PHY_ID_MASK, 8032f664823SMichael Walle .probe = at803x_probe, 8042318ca8aSMichael Walle .remove = at803x_remove, 8050ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 806cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 807ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 808ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 8096229ed1fSDaniel Mack .suspend = at803x_suspend, 8106229ed1fSDaniel Mack .resume = at803x_resume, 811dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 81206d5f344SRussell King .read_status = at803x_read_status, 8130eae5982SMåns Rullgård .ack_interrupt = at803x_ack_interrupt, 8140eae5982SMåns Rullgård .config_intr = at803x_config_intr, 815cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 816cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 817317420abSMugunthan V N }, { 81896c36712SMichael Walle /* Qualcomm Atheros AR8030 */ 819bd8ca17fSDaniel Mack .phy_id = ATH8030_PHY_ID, 82096c36712SMichael Walle .name = "Qualcomm Atheros AR8030", 82158effd71SFabio Estevam .phy_id_mask = AT803X_PHY_ID_MASK, 8222f664823SMichael Walle .probe = at803x_probe, 8232318ca8aSMichael Walle .remove = at803x_remove, 8240ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 82513a56b44SDaniel Mack .link_change_notify = at803x_link_change_notify, 826ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 827ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 8286229ed1fSDaniel Mack .suspend = at803x_suspend, 8296229ed1fSDaniel Mack .resume = at803x_resume, 830dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 8310eae5982SMåns Rullgård .ack_interrupt = at803x_ack_interrupt, 8320eae5982SMåns Rullgård .config_intr = at803x_config_intr, 83305d7cce8SMugunthan V N }, { 83496c36712SMichael Walle /* Qualcomm Atheros AR8031/AR8033 */ 835bd8ca17fSDaniel Mack .phy_id = ATH8031_PHY_ID, 83696c36712SMichael Walle .name = "Qualcomm Atheros AR8031/AR8033", 83758effd71SFabio Estevam .phy_id_mask = AT803X_PHY_ID_MASK, 8382f664823SMichael Walle .probe = at803x_probe, 8392318ca8aSMichael Walle .remove = at803x_remove, 84005d7cce8SMugunthan V N .config_init = at803x_config_init, 841cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 84205d7cce8SMugunthan V N .set_wol = at803x_set_wol, 84305d7cce8SMugunthan V N .get_wol = at803x_get_wol, 8446229ed1fSDaniel Mack .suspend = at803x_suspend, 8456229ed1fSDaniel Mack .resume = at803x_resume, 846dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 84706d5f344SRussell King .read_status = at803x_read_status, 848f62265b5SZefir Kurtisi .aneg_done = at803x_aneg_done, 84977a99394SZhao Qiang .ack_interrupt = &at803x_ack_interrupt, 85077a99394SZhao Qiang .config_intr = &at803x_config_intr, 851cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 852cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 8537908d2ceSOleksij Rempel }, { 8545800091aSDavid Bauer /* Qualcomm Atheros AR8032 */ 8555800091aSDavid Bauer PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 8565800091aSDavid Bauer .name = "Qualcomm Atheros AR8032", 8575800091aSDavid Bauer .probe = at803x_probe, 8585800091aSDavid Bauer .remove = at803x_remove, 8595800091aSDavid Bauer .config_init = at803x_config_init, 8605800091aSDavid Bauer .link_change_notify = at803x_link_change_notify, 8615800091aSDavid Bauer .set_wol = at803x_set_wol, 8625800091aSDavid Bauer .get_wol = at803x_get_wol, 8635800091aSDavid Bauer .suspend = at803x_suspend, 8645800091aSDavid Bauer .resume = at803x_resume, 8655800091aSDavid Bauer /* PHY_BASIC_FEATURES */ 8665800091aSDavid Bauer .ack_interrupt = at803x_ack_interrupt, 8675800091aSDavid Bauer .config_intr = at803x_config_intr, 8685800091aSDavid Bauer }, { 8697908d2ceSOleksij Rempel /* ATHEROS AR9331 */ 8707908d2ceSOleksij Rempel PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 87196c36712SMichael Walle .name = "Qualcomm Atheros AR9331 built-in PHY", 8727908d2ceSOleksij Rempel .suspend = at803x_suspend, 8737908d2ceSOleksij Rempel .resume = at803x_resume, 8747908d2ceSOleksij Rempel /* PHY_BASIC_FEATURES */ 8757908d2ceSOleksij Rempel .ack_interrupt = &at803x_ack_interrupt, 8767908d2ceSOleksij Rempel .config_intr = &at803x_config_intr, 877317420abSMugunthan V N } }; 8780ca7111aSMatus Ujhelyi 87950fd7150SJohan Hovold module_phy_driver(at803x_driver); 8800ca7111aSMatus Ujhelyi 8810ca7111aSMatus Ujhelyi static struct mdio_device_id __maybe_unused atheros_tbl[] = { 88258effd71SFabio Estevam { ATH8030_PHY_ID, AT803X_PHY_ID_MASK }, 88358effd71SFabio Estevam { ATH8031_PHY_ID, AT803X_PHY_ID_MASK }, 8845800091aSDavid Bauer { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 88558effd71SFabio Estevam { ATH8035_PHY_ID, AT803X_PHY_ID_MASK }, 8867908d2ceSOleksij Rempel { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 8870ca7111aSMatus Ujhelyi { } 8880ca7111aSMatus Ujhelyi }; 8890ca7111aSMatus Ujhelyi 8900ca7111aSMatus Ujhelyi MODULE_DEVICE_TABLE(mdio, atheros_tbl); 891