1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 20ca7111aSMatus Ujhelyi /* 30ca7111aSMatus Ujhelyi * drivers/net/phy/at803x.c 40ca7111aSMatus Ujhelyi * 596c36712SMichael Walle * Driver for Qualcomm Atheros AR803x PHY 60ca7111aSMatus Ujhelyi * 70ca7111aSMatus Ujhelyi * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 80ca7111aSMatus Ujhelyi */ 90ca7111aSMatus Ujhelyi 100ca7111aSMatus Ujhelyi #include <linux/phy.h> 110ca7111aSMatus Ujhelyi #include <linux/module.h> 120ca7111aSMatus Ujhelyi #include <linux/string.h> 130ca7111aSMatus Ujhelyi #include <linux/netdevice.h> 140ca7111aSMatus Ujhelyi #include <linux/etherdevice.h> 156cb75767SMichael Walle #include <linux/ethtool_netlink.h> 162f664823SMichael Walle #include <linux/bitfield.h> 172f664823SMichael Walle #include <linux/regulator/of_regulator.h> 182f664823SMichael Walle #include <linux/regulator/driver.h> 192f664823SMichael Walle #include <linux/regulator/consumer.h> 20*a593a2fcSAndy Shevchenko #include <linux/of.h> 21dc4d5fccSRobert Hancock #include <linux/phylink.h> 22dc4d5fccSRobert Hancock #include <linux/sfp.h> 232f664823SMichael Walle #include <dt-bindings/net/qca-ar803x.h> 240ca7111aSMatus Ujhelyi 257dce80c2SOleksij Rempel #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 267dce80c2SOleksij Rempel #define AT803X_SFC_ASSERT_CRS BIT(11) 277dce80c2SOleksij Rempel #define AT803X_SFC_FORCE_LINK BIT(10) 287dce80c2SOleksij Rempel #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 297dce80c2SOleksij Rempel #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 307dce80c2SOleksij Rempel #define AT803X_SFC_MANUAL_MDIX 0x1 317dce80c2SOleksij Rempel #define AT803X_SFC_MANUAL_MDI 0x0 327dce80c2SOleksij Rempel #define AT803X_SFC_SQE_TEST BIT(2) 337dce80c2SOleksij Rempel #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 347dce80c2SOleksij Rempel #define AT803X_SFC_DISABLE_JABBER BIT(0) 357dce80c2SOleksij Rempel 3606d5f344SRussell King #define AT803X_SPECIFIC_STATUS 0x11 379540cddaSLuo Jie #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 389540cddaSLuo Jie #define AT803X_SS_SPEED_1000 2 399540cddaSLuo Jie #define AT803X_SS_SPEED_100 1 409540cddaSLuo Jie #define AT803X_SS_SPEED_10 0 4106d5f344SRussell King #define AT803X_SS_DUPLEX BIT(13) 4206d5f344SRussell King #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 4306d5f344SRussell King #define AT803X_SS_MDIX BIT(6) 4406d5f344SRussell King 4579c7bc05SLuo Jie #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 4679c7bc05SLuo Jie #define QCA808X_SS_SPEED_2500 4 4779c7bc05SLuo Jie 480ca7111aSMatus Ujhelyi #define AT803X_INTR_ENABLE 0x12 49e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 50e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 51e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 52e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 53e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 54e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 553265f421SRobert Hancock #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 563265f421SRobert Hancock #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 57e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 58e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 59e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WOL BIT(0) 60e6e4a556SMartin Blumenstingl 610ca7111aSMatus Ujhelyi #define AT803X_INTR_STATUS 0x13 62a46bd63bSMartin Blumenstingl 6313a56b44SDaniel Mack #define AT803X_SMART_SPEED 0x14 64cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_ENABLE BIT(5) 65cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 66cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 676cb75767SMichael Walle #define AT803X_CDT 0x16 686cb75767SMichael Walle #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 696cb75767SMichael Walle #define AT803X_CDT_ENABLE_TEST BIT(0) 706cb75767SMichael Walle #define AT803X_CDT_STATUS 0x1c 716cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_NORMAL 0 726cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_SHORT 1 736cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_OPEN 2 746cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_FAIL 3 756cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 766cb75767SMichael Walle #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 7713a56b44SDaniel Mack #define AT803X_LED_CONTROL 0x18 78a46bd63bSMartin Blumenstingl 797beecaf7SLuo Jie #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 807beecaf7SLuo Jie #define AT803X_WOL_EN BIT(5) 810ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 820ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 830ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 84f62265b5SZefir Kurtisi #define AT803X_REG_CHIP_CONFIG 0x1f 85f62265b5SZefir Kurtisi #define AT803X_BT_BX_REG_SEL 0x8000 86a46bd63bSMartin Blumenstingl 871ca6d1b1SMugunthan V N #define AT803X_DEBUG_ADDR 0x1D 881ca6d1b1SMugunthan V N #define AT803X_DEBUG_DATA 0x1E 89a46bd63bSMartin Blumenstingl 90f62265b5SZefir Kurtisi #define AT803X_MODE_CFG_MASK 0x0F 913265f421SRobert Hancock #define AT803X_MODE_CFG_BASET_RGMII 0x00 923265f421SRobert Hancock #define AT803X_MODE_CFG_BASET_SGMII 0x01 933265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 943265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 953265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 963265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 973265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 983265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 993265f421SRobert Hancock #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 1003265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 1013265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 102f62265b5SZefir Kurtisi 103f62265b5SZefir Kurtisi #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 104f62265b5SZefir Kurtisi #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 105f62265b5SZefir Kurtisi 10667999555SAnsuel Smith #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 1071ca83119SAnsuel Smith #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 1081ca83119SAnsuel Smith #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 1092e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 110a46bd63bSMartin Blumenstingl 11167999555SAnsuel Smith #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 1122e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 1130ca7111aSMatus Ujhelyi 114ba3c01eeSAnsuel Smith #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 115ba3c01eeSAnsuel Smith #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 116ba3c01eeSAnsuel Smith #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 1179ecf0401SWei Fang #define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15) 118ba3c01eeSAnsuel Smith 119272833b9SAnsuel Smith #define AT803X_DEBUG_REG_3C 0x3C 120272833b9SAnsuel Smith 12167999555SAnsuel Smith #define AT803X_DEBUG_REG_GREEN 0x3D 122ba3c01eeSAnsuel Smith #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 123272833b9SAnsuel Smith 1242f664823SMichael Walle #define AT803X_DEBUG_REG_1F 0x1F 1252f664823SMichael Walle #define AT803X_DEBUG_PLL_ON BIT(2) 1262f664823SMichael Walle #define AT803X_DEBUG_RGMII_1V8 BIT(3) 1272f664823SMichael Walle 128272833b9SAnsuel Smith #define MDIO_AZ_DEBUG 0x800D 129272833b9SAnsuel Smith 1302f664823SMichael Walle /* AT803x supports either the XTAL input pad, an internal PLL or the 1312f664823SMichael Walle * DSP as clock reference for the clock output pad. The XTAL reference 1322f664823SMichael Walle * is only used for 25 MHz output, all other frequencies need the PLL. 1332f664823SMichael Walle * The DSP as a clock reference is used in synchronous ethernet 1342f664823SMichael Walle * applications. 1352f664823SMichael Walle * 1362f664823SMichael Walle * By default the PLL is only enabled if there is a link. Otherwise 1372f664823SMichael Walle * the PHY will go into low power state and disabled the PLL. You can 1382f664823SMichael Walle * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 1392f664823SMichael Walle * enabled. 1402f664823SMichael Walle */ 1412f664823SMichael Walle #define AT803X_MMD7_CLK25M 0x8016 1422f664823SMichael Walle #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 1432f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_XTAL 0 1442f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_DSP 1 1452f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_PLL 2 1462f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_DSP 3 1472f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_PLL 4 1482f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_DSP 5 1492f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_PLL 6 1502f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_DSP 7 1512f664823SMichael Walle 152428061f7SMichael Walle /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 153428061f7SMichael Walle * but doesn't support choosing between XTAL/PLL and DSP. 1542f664823SMichael Walle */ 1552f664823SMichael Walle #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 1562f664823SMichael Walle 1572f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 1582f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_FULL 0 1592f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_HALF 1 1602f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 1612f664823SMichael Walle 162cde0f4f8SMichael Walle #define AT803X_DEFAULT_DOWNSHIFT 5 163cde0f4f8SMichael Walle #define AT803X_MIN_DOWNSHIFT 2 164cde0f4f8SMichael Walle #define AT803X_MAX_DOWNSHIFT 9 165cde0f4f8SMichael Walle 166390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 167390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 168390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 169390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 170390b4cadSRussell King 1717908d2ceSOleksij Rempel #define ATH9331_PHY_ID 0x004dd041 172bd8ca17fSDaniel Mack #define ATH8030_PHY_ID 0x004dd076 173bd8ca17fSDaniel Mack #define ATH8031_PHY_ID 0x004dd074 1745800091aSDavid Bauer #define ATH8032_PHY_ID 0x004dd023 175bd8ca17fSDaniel Mack #define ATH8035_PHY_ID 0x004dd072 1760465d8f8SMichael Walle #define AT8030_PHY_ID_MASK 0xffffffef 177bd8ca17fSDaniel Mack 178daf61732SLuo Jie #define QCA8081_PHY_ID 0x004dd101 179daf61732SLuo Jie 180b4df02b5SAnsuel Smith #define QCA8327_A_PHY_ID 0x004dd033 181b4df02b5SAnsuel Smith #define QCA8327_B_PHY_ID 0x004dd034 182272833b9SAnsuel Smith #define QCA8337_PHY_ID 0x004dd036 183fada2ce0SDavid Bauer #define QCA9561_PHY_ID 0x004dd042 184272833b9SAnsuel Smith #define QCA8K_PHY_ID_MASK 0xffffffff 185272833b9SAnsuel Smith 186272833b9SAnsuel Smith #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 187272833b9SAnsuel Smith 188c329e5afSDavid Bauer #define AT803X_PAGE_FIBER 0 189c329e5afSDavid Bauer #define AT803X_PAGE_COPPER 1 190c329e5afSDavid Bauer 191d0e13fd5SAnsuel Smith /* don't turn off internal PLL */ 192d0e13fd5SAnsuel Smith #define AT803X_KEEP_PLL_ENABLED BIT(0) 193d0e13fd5SAnsuel Smith #define AT803X_DISABLE_SMARTEEE BIT(1) 194d0e13fd5SAnsuel Smith 1959ecf0401SWei Fang /* disable hibernation mode */ 1969ecf0401SWei Fang #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) 1979ecf0401SWei Fang 1982acdd43fSLuo Jie /* ADC threshold */ 1992acdd43fSLuo Jie #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 2002acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 2012acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_80MV 0 2022acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_100MV 0xf0 2032acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_200MV 0x0f 2042acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_300MV 0xff 2052acdd43fSLuo Jie 2062acdd43fSLuo Jie /* CLD control */ 2072acdd43fSLuo Jie #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 2082acdd43fSLuo Jie #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 2092acdd43fSLuo Jie #define QCA808X_8023AZ_AFE_EN 0x90 2102acdd43fSLuo Jie 2112acdd43fSLuo Jie /* AZ control */ 2122acdd43fSLuo Jie #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 2132acdd43fSLuo Jie #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 2142acdd43fSLuo Jie 2152acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 2162acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 2172acdd43fSLuo Jie 2182acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 2192acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 2202acdd43fSLuo Jie 2212acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 2222acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 2232acdd43fSLuo Jie 2242acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 2252acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 2262acdd43fSLuo Jie 2272acdd43fSLuo Jie #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 2282acdd43fSLuo Jie #define QCA808X_TOP_OPTION1_DATA 0x0 2292acdd43fSLuo Jie 2302acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 2312acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 2322acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 2332acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 2342acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 2352acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 2362acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 2372acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 2382acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 2392acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 2402acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 2412acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 2422acdd43fSLuo Jie 2439d4dae29SLuo Jie /* master/slave seed config */ 2449d4dae29SLuo Jie #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 2459d4dae29SLuo Jie #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 2469d4dae29SLuo Jie #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 2479d4dae29SLuo Jie #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 2489d4dae29SLuo Jie 2498c84d752SLuo Jie /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 2508c84d752SLuo Jie * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 2518c84d752SLuo Jie */ 2528c84d752SLuo Jie #define QCA808X_DBG_AN_TEST 0xb 2538c84d752SLuo Jie #define QCA808X_HIBERNATION_EN BIT(15) 2548c84d752SLuo Jie 2558c84d752SLuo Jie #define QCA808X_CDT_ENABLE_TEST BIT(15) 2568c84d752SLuo Jie #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 2578c84d752SLuo Jie #define QCA808X_CDT_LENGTH_UNIT BIT(10) 2588c84d752SLuo Jie 2598c84d752SLuo Jie #define QCA808X_MMD3_CDT_STATUS 0x8064 2608c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 2618c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 2628c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 2638c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 2648c84d752SLuo Jie #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 2658c84d752SLuo Jie 2668c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 2678c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 2688c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 2698c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 2708c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_FAIL 0 2718c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_NORMAL 1 2728c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_OPEN 2 2738c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_SHORT 3 2748c84d752SLuo Jie 275daf61732SLuo Jie MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 2760ca7111aSMatus Ujhelyi MODULE_AUTHOR("Matus Ujhelyi"); 2770ca7111aSMatus Ujhelyi MODULE_LICENSE("GPL"); 2780ca7111aSMatus Ujhelyi 279272833b9SAnsuel Smith enum stat_access_type { 280272833b9SAnsuel Smith PHY, 281272833b9SAnsuel Smith MMD 282272833b9SAnsuel Smith }; 283272833b9SAnsuel Smith 284272833b9SAnsuel Smith struct at803x_hw_stat { 285272833b9SAnsuel Smith const char *string; 286272833b9SAnsuel Smith u8 reg; 287272833b9SAnsuel Smith u32 mask; 288272833b9SAnsuel Smith enum stat_access_type access_type; 289272833b9SAnsuel Smith }; 290272833b9SAnsuel Smith 291272833b9SAnsuel Smith static struct at803x_hw_stat at803x_hw_stats[] = { 292272833b9SAnsuel Smith { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 293272833b9SAnsuel Smith { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 294272833b9SAnsuel Smith { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 295272833b9SAnsuel Smith }; 296272833b9SAnsuel Smith 2972f664823SMichael Walle struct at803x_priv { 2982f664823SMichael Walle int flags; 2992f664823SMichael Walle u16 clk_25m_reg; 3002f664823SMichael Walle u16 clk_25m_mask; 301390b4cadSRussell King u8 smarteee_lpi_tw_1g; 302390b4cadSRussell King u8 smarteee_lpi_tw_100m; 3033265f421SRobert Hancock bool is_fiber; 3043265f421SRobert Hancock bool is_1000basex; 3052f664823SMichael Walle struct regulator_dev *vddio_rdev; 3062f664823SMichael Walle struct regulator_dev *vddh_rdev; 3072f664823SMichael Walle struct regulator *vddio; 308272833b9SAnsuel Smith u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 3092f664823SMichael Walle }; 3102f664823SMichael Walle 31113a56b44SDaniel Mack struct at803x_context { 31213a56b44SDaniel Mack u16 bmcr; 31313a56b44SDaniel Mack u16 advertise; 31413a56b44SDaniel Mack u16 control1000; 31513a56b44SDaniel Mack u16 int_enable; 31613a56b44SDaniel Mack u16 smart_speed; 31713a56b44SDaniel Mack u16 led_control; 31813a56b44SDaniel Mack }; 31913a56b44SDaniel Mack 320272833b9SAnsuel Smith static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 321272833b9SAnsuel Smith { 322272833b9SAnsuel Smith int ret; 323272833b9SAnsuel Smith 324272833b9SAnsuel Smith ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 325272833b9SAnsuel Smith if (ret < 0) 326272833b9SAnsuel Smith return ret; 327272833b9SAnsuel Smith 328272833b9SAnsuel Smith return phy_write(phydev, AT803X_DEBUG_DATA, data); 329272833b9SAnsuel Smith } 330272833b9SAnsuel Smith 3312e5f9f28SMartin Blumenstingl static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 3322e5f9f28SMartin Blumenstingl { 3332e5f9f28SMartin Blumenstingl int ret; 3342e5f9f28SMartin Blumenstingl 3352e5f9f28SMartin Blumenstingl ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 3362e5f9f28SMartin Blumenstingl if (ret < 0) 3372e5f9f28SMartin Blumenstingl return ret; 3382e5f9f28SMartin Blumenstingl 3392e5f9f28SMartin Blumenstingl return phy_read(phydev, AT803X_DEBUG_DATA); 3402e5f9f28SMartin Blumenstingl } 3412e5f9f28SMartin Blumenstingl 3422e5f9f28SMartin Blumenstingl static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 3432e5f9f28SMartin Blumenstingl u16 clear, u16 set) 3442e5f9f28SMartin Blumenstingl { 3452e5f9f28SMartin Blumenstingl u16 val; 3462e5f9f28SMartin Blumenstingl int ret; 3472e5f9f28SMartin Blumenstingl 3482e5f9f28SMartin Blumenstingl ret = at803x_debug_reg_read(phydev, reg); 3492e5f9f28SMartin Blumenstingl if (ret < 0) 3502e5f9f28SMartin Blumenstingl return ret; 3512e5f9f28SMartin Blumenstingl 3522e5f9f28SMartin Blumenstingl val = ret & 0xffff; 3532e5f9f28SMartin Blumenstingl val &= ~clear; 3542e5f9f28SMartin Blumenstingl val |= set; 3552e5f9f28SMartin Blumenstingl 3562e5f9f28SMartin Blumenstingl return phy_write(phydev, AT803X_DEBUG_DATA, val); 3572e5f9f28SMartin Blumenstingl } 3582e5f9f28SMartin Blumenstingl 359c329e5afSDavid Bauer static int at803x_write_page(struct phy_device *phydev, int page) 360c329e5afSDavid Bauer { 361c329e5afSDavid Bauer int mask; 362c329e5afSDavid Bauer int set; 363c329e5afSDavid Bauer 364c329e5afSDavid Bauer if (page == AT803X_PAGE_COPPER) { 365c329e5afSDavid Bauer set = AT803X_BT_BX_REG_SEL; 366c329e5afSDavid Bauer mask = 0; 367c329e5afSDavid Bauer } else { 368c329e5afSDavid Bauer set = 0; 369c329e5afSDavid Bauer mask = AT803X_BT_BX_REG_SEL; 370c329e5afSDavid Bauer } 371c329e5afSDavid Bauer 372c329e5afSDavid Bauer return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 373c329e5afSDavid Bauer } 374c329e5afSDavid Bauer 375c329e5afSDavid Bauer static int at803x_read_page(struct phy_device *phydev) 376c329e5afSDavid Bauer { 377c329e5afSDavid Bauer int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 378c329e5afSDavid Bauer 379c329e5afSDavid Bauer if (ccr < 0) 380c329e5afSDavid Bauer return ccr; 381c329e5afSDavid Bauer 382c329e5afSDavid Bauer if (ccr & AT803X_BT_BX_REG_SEL) 383c329e5afSDavid Bauer return AT803X_PAGE_COPPER; 384c329e5afSDavid Bauer 385c329e5afSDavid Bauer return AT803X_PAGE_FIBER; 386c329e5afSDavid Bauer } 387c329e5afSDavid Bauer 3886d4cd041SVinod Koul static int at803x_enable_rx_delay(struct phy_device *phydev) 3896d4cd041SVinod Koul { 39067999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 3916d4cd041SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN); 3926d4cd041SVinod Koul } 3936d4cd041SVinod Koul 3946d4cd041SVinod Koul static int at803x_enable_tx_delay(struct phy_device *phydev) 3956d4cd041SVinod Koul { 39667999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 3976d4cd041SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN); 3986d4cd041SVinod Koul } 3996d4cd041SVinod Koul 40043f2ebd5SVinod Koul static int at803x_disable_rx_delay(struct phy_device *phydev) 4012e5f9f28SMartin Blumenstingl { 40267999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 403cd28d1d6SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN, 0); 4042e5f9f28SMartin Blumenstingl } 4052e5f9f28SMartin Blumenstingl 40643f2ebd5SVinod Koul static int at803x_disable_tx_delay(struct phy_device *phydev) 4072e5f9f28SMartin Blumenstingl { 40867999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 409cd28d1d6SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN, 0); 4102e5f9f28SMartin Blumenstingl } 4112e5f9f28SMartin Blumenstingl 41213a56b44SDaniel Mack /* save relevant PHY registers to private copy */ 41313a56b44SDaniel Mack static void at803x_context_save(struct phy_device *phydev, 41413a56b44SDaniel Mack struct at803x_context *context) 41513a56b44SDaniel Mack { 41613a56b44SDaniel Mack context->bmcr = phy_read(phydev, MII_BMCR); 41713a56b44SDaniel Mack context->advertise = phy_read(phydev, MII_ADVERTISE); 41813a56b44SDaniel Mack context->control1000 = phy_read(phydev, MII_CTRL1000); 41913a56b44SDaniel Mack context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 42013a56b44SDaniel Mack context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 42113a56b44SDaniel Mack context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 42213a56b44SDaniel Mack } 42313a56b44SDaniel Mack 42413a56b44SDaniel Mack /* restore relevant PHY registers from private copy */ 42513a56b44SDaniel Mack static void at803x_context_restore(struct phy_device *phydev, 42613a56b44SDaniel Mack const struct at803x_context *context) 42713a56b44SDaniel Mack { 42813a56b44SDaniel Mack phy_write(phydev, MII_BMCR, context->bmcr); 42913a56b44SDaniel Mack phy_write(phydev, MII_ADVERTISE, context->advertise); 43013a56b44SDaniel Mack phy_write(phydev, MII_CTRL1000, context->control1000); 43113a56b44SDaniel Mack phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 43213a56b44SDaniel Mack phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 43313a56b44SDaniel Mack phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 43413a56b44SDaniel Mack } 43513a56b44SDaniel Mack 436ea13c9eeSMugunthan V N static int at803x_set_wol(struct phy_device *phydev, 437ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 4380ca7111aSMatus Ujhelyi { 439d7cd5e06SViorel Suman int ret, irq_enabled; 440d7cd5e06SViorel Suman 441d7cd5e06SViorel Suman if (wol->wolopts & WAKE_MAGIC) { 4420ca7111aSMatus Ujhelyi struct net_device *ndev = phydev->attached_dev; 4430ca7111aSMatus Ujhelyi const u8 *mac; 444c0f0b563SLuo Jie unsigned int i; 445edcb501eSColin Ian King static const unsigned int offsets[] = { 4460ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_32_47_OFFSET, 4470ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_16_31_OFFSET, 4480ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_0_15_OFFSET, 4490ca7111aSMatus Ujhelyi }; 4500ca7111aSMatus Ujhelyi 4510ca7111aSMatus Ujhelyi if (!ndev) 452ea13c9eeSMugunthan V N return -ENODEV; 4530ca7111aSMatus Ujhelyi 4540ca7111aSMatus Ujhelyi mac = (const u8 *) ndev->dev_addr; 4550ca7111aSMatus Ujhelyi 4560ca7111aSMatus Ujhelyi if (!is_valid_ether_addr(mac)) 457fc755687SDan Murphy return -EINVAL; 4580ca7111aSMatus Ujhelyi 4590e021396SCarlo Caione for (i = 0; i < 3; i++) 460c0f0b563SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 4610ca7111aSMatus Ujhelyi mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 462ea13c9eeSMugunthan V N 4637beecaf7SLuo Jie /* Enable WOL function */ 4647beecaf7SLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 4657beecaf7SLuo Jie 0, AT803X_WOL_EN); 4667beecaf7SLuo Jie if (ret) 4677beecaf7SLuo Jie return ret; 4687beecaf7SLuo Jie /* Enable WOL interrupt */ 4692d4284e8SLuo Jie ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 470ea13c9eeSMugunthan V N if (ret) 471ea13c9eeSMugunthan V N return ret; 472ea13c9eeSMugunthan V N } else { 4737beecaf7SLuo Jie /* Disable WoL function */ 4747beecaf7SLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 4757beecaf7SLuo Jie AT803X_WOL_EN, 0); 4767beecaf7SLuo Jie if (ret) 4777beecaf7SLuo Jie return ret; 4787beecaf7SLuo Jie /* Disable WOL interrupt */ 4792d4284e8SLuo Jie ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 480ea13c9eeSMugunthan V N if (ret) 481ea13c9eeSMugunthan V N return ret; 482ea13c9eeSMugunthan V N } 483ea13c9eeSMugunthan V N 4847beecaf7SLuo Jie /* Clear WOL status */ 4857beecaf7SLuo Jie ret = phy_read(phydev, AT803X_INTR_STATUS); 4867beecaf7SLuo Jie if (ret < 0) 487ea13c9eeSMugunthan V N return ret; 4887beecaf7SLuo Jie 4897beecaf7SLuo Jie /* Check if there are other interrupts except for WOL triggered when PHY is 4907beecaf7SLuo Jie * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 4917beecaf7SLuo Jie * be passed up to the interrupt PIN. 4927beecaf7SLuo Jie */ 4937beecaf7SLuo Jie irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 4947beecaf7SLuo Jie if (irq_enabled < 0) 4957beecaf7SLuo Jie return irq_enabled; 4967beecaf7SLuo Jie 4977beecaf7SLuo Jie irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 4987beecaf7SLuo Jie if (ret & irq_enabled && !phy_polling_mode(phydev)) 4997beecaf7SLuo Jie phy_trigger_machine(phydev); 5007beecaf7SLuo Jie 5017beecaf7SLuo Jie return 0; 502ea13c9eeSMugunthan V N } 503ea13c9eeSMugunthan V N 504ea13c9eeSMugunthan V N static void at803x_get_wol(struct phy_device *phydev, 505ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 506ea13c9eeSMugunthan V N { 507911e3a46SJiapeng Chong int value; 508ea13c9eeSMugunthan V N 509ea13c9eeSMugunthan V N wol->supported = WAKE_MAGIC; 510ea13c9eeSMugunthan V N wol->wolopts = 0; 511ea13c9eeSMugunthan V N 5127beecaf7SLuo Jie value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 5137beecaf7SLuo Jie if (value < 0) 5147beecaf7SLuo Jie return; 5157beecaf7SLuo Jie 5167beecaf7SLuo Jie if (value & AT803X_WOL_EN) 517ea13c9eeSMugunthan V N wol->wolopts |= WAKE_MAGIC; 5180ca7111aSMatus Ujhelyi } 5190ca7111aSMatus Ujhelyi 520272833b9SAnsuel Smith static int at803x_get_sset_count(struct phy_device *phydev) 521272833b9SAnsuel Smith { 522272833b9SAnsuel Smith return ARRAY_SIZE(at803x_hw_stats); 523272833b9SAnsuel Smith } 524272833b9SAnsuel Smith 525272833b9SAnsuel Smith static void at803x_get_strings(struct phy_device *phydev, u8 *data) 526272833b9SAnsuel Smith { 527272833b9SAnsuel Smith int i; 528272833b9SAnsuel Smith 529272833b9SAnsuel Smith for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 530272833b9SAnsuel Smith strscpy(data + i * ETH_GSTRING_LEN, 531272833b9SAnsuel Smith at803x_hw_stats[i].string, ETH_GSTRING_LEN); 532272833b9SAnsuel Smith } 533272833b9SAnsuel Smith } 534272833b9SAnsuel Smith 535272833b9SAnsuel Smith static u64 at803x_get_stat(struct phy_device *phydev, int i) 536272833b9SAnsuel Smith { 537272833b9SAnsuel Smith struct at803x_hw_stat stat = at803x_hw_stats[i]; 538272833b9SAnsuel Smith struct at803x_priv *priv = phydev->priv; 539272833b9SAnsuel Smith int val; 540272833b9SAnsuel Smith u64 ret; 541272833b9SAnsuel Smith 542272833b9SAnsuel Smith if (stat.access_type == MMD) 543272833b9SAnsuel Smith val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 544272833b9SAnsuel Smith else 545272833b9SAnsuel Smith val = phy_read(phydev, stat.reg); 546272833b9SAnsuel Smith 547272833b9SAnsuel Smith if (val < 0) { 548272833b9SAnsuel Smith ret = U64_MAX; 549272833b9SAnsuel Smith } else { 550272833b9SAnsuel Smith val = val & stat.mask; 551272833b9SAnsuel Smith priv->stats[i] += val; 552272833b9SAnsuel Smith ret = priv->stats[i]; 553272833b9SAnsuel Smith } 554272833b9SAnsuel Smith 555272833b9SAnsuel Smith return ret; 556272833b9SAnsuel Smith } 557272833b9SAnsuel Smith 558272833b9SAnsuel Smith static void at803x_get_stats(struct phy_device *phydev, 559272833b9SAnsuel Smith struct ethtool_stats *stats, u64 *data) 560272833b9SAnsuel Smith { 561272833b9SAnsuel Smith int i; 562272833b9SAnsuel Smith 563272833b9SAnsuel Smith for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 564272833b9SAnsuel Smith data[i] = at803x_get_stat(phydev, i); 565272833b9SAnsuel Smith } 566272833b9SAnsuel Smith 5676229ed1fSDaniel Mack static int at803x_suspend(struct phy_device *phydev) 5686229ed1fSDaniel Mack { 5696229ed1fSDaniel Mack int value; 5706229ed1fSDaniel Mack int wol_enabled; 5716229ed1fSDaniel Mack 5726229ed1fSDaniel Mack value = phy_read(phydev, AT803X_INTR_ENABLE); 573e6e4a556SMartin Blumenstingl wol_enabled = value & AT803X_INTR_ENABLE_WOL; 5746229ed1fSDaniel Mack 5756229ed1fSDaniel Mack if (wol_enabled) 576fea23fb5SRussell King value = BMCR_ISOLATE; 5776229ed1fSDaniel Mack else 578fea23fb5SRussell King value = BMCR_PDOWN; 5796229ed1fSDaniel Mack 580fea23fb5SRussell King phy_modify(phydev, MII_BMCR, 0, value); 5816229ed1fSDaniel Mack 5826229ed1fSDaniel Mack return 0; 5836229ed1fSDaniel Mack } 5846229ed1fSDaniel Mack 5856229ed1fSDaniel Mack static int at803x_resume(struct phy_device *phydev) 5866229ed1fSDaniel Mack { 587f102852fSRussell King return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 5886229ed1fSDaniel Mack } 5896229ed1fSDaniel Mack 5902f664823SMichael Walle static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 5912f664823SMichael Walle unsigned int selector) 5922f664823SMichael Walle { 5932f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 5942f664823SMichael Walle 5952f664823SMichael Walle if (selector) 5962f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 5972f664823SMichael Walle 0, AT803X_DEBUG_RGMII_1V8); 5982f664823SMichael Walle else 5992f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 6002f664823SMichael Walle AT803X_DEBUG_RGMII_1V8, 0); 6012f664823SMichael Walle } 6022f664823SMichael Walle 6032f664823SMichael Walle static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 6042f664823SMichael Walle { 6052f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 6062f664823SMichael Walle int val; 6072f664823SMichael Walle 6082f664823SMichael Walle val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 6092f664823SMichael Walle if (val < 0) 6102f664823SMichael Walle return val; 6112f664823SMichael Walle 6122f664823SMichael Walle return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 6132f664823SMichael Walle } 6142f664823SMichael Walle 6153faaf539SRikard Falkeborn static const struct regulator_ops vddio_regulator_ops = { 6162f664823SMichael Walle .list_voltage = regulator_list_voltage_table, 6172f664823SMichael Walle .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 6182f664823SMichael Walle .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 6192f664823SMichael Walle }; 6202f664823SMichael Walle 6212f664823SMichael Walle static const unsigned int vddio_voltage_table[] = { 6222f664823SMichael Walle 1500000, 6232f664823SMichael Walle 1800000, 6242f664823SMichael Walle }; 6252f664823SMichael Walle 6262f664823SMichael Walle static const struct regulator_desc vddio_desc = { 6272f664823SMichael Walle .name = "vddio", 6282f664823SMichael Walle .of_match = of_match_ptr("vddio-regulator"), 6292f664823SMichael Walle .n_voltages = ARRAY_SIZE(vddio_voltage_table), 6302f664823SMichael Walle .volt_table = vddio_voltage_table, 6312f664823SMichael Walle .ops = &vddio_regulator_ops, 6322f664823SMichael Walle .type = REGULATOR_VOLTAGE, 6332f664823SMichael Walle .owner = THIS_MODULE, 6342f664823SMichael Walle }; 6352f664823SMichael Walle 6363faaf539SRikard Falkeborn static const struct regulator_ops vddh_regulator_ops = { 6372f664823SMichael Walle }; 6382f664823SMichael Walle 6392f664823SMichael Walle static const struct regulator_desc vddh_desc = { 6402f664823SMichael Walle .name = "vddh", 6412f664823SMichael Walle .of_match = of_match_ptr("vddh-regulator"), 6422f664823SMichael Walle .n_voltages = 1, 6432f664823SMichael Walle .fixed_uV = 2500000, 6442f664823SMichael Walle .ops = &vddh_regulator_ops, 6452f664823SMichael Walle .type = REGULATOR_VOLTAGE, 6462f664823SMichael Walle .owner = THIS_MODULE, 6472f664823SMichael Walle }; 6482f664823SMichael Walle 6492f664823SMichael Walle static int at8031_register_regulators(struct phy_device *phydev) 6502f664823SMichael Walle { 6512f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 6522f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 6532f664823SMichael Walle struct regulator_config config = { }; 6542f664823SMichael Walle 6552f664823SMichael Walle config.dev = dev; 6562f664823SMichael Walle config.driver_data = phydev; 6572f664823SMichael Walle 6582f664823SMichael Walle priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 6592f664823SMichael Walle if (IS_ERR(priv->vddio_rdev)) { 6602f664823SMichael Walle phydev_err(phydev, "failed to register VDDIO regulator\n"); 6612f664823SMichael Walle return PTR_ERR(priv->vddio_rdev); 6622f664823SMichael Walle } 6632f664823SMichael Walle 6642f664823SMichael Walle priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 6652f664823SMichael Walle if (IS_ERR(priv->vddh_rdev)) { 6662f664823SMichael Walle phydev_err(phydev, "failed to register VDDH regulator\n"); 6672f664823SMichael Walle return PTR_ERR(priv->vddh_rdev); 6682f664823SMichael Walle } 6692f664823SMichael Walle 6702f664823SMichael Walle return 0; 6712f664823SMichael Walle } 6722f664823SMichael Walle 673dc4d5fccSRobert Hancock static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) 674dc4d5fccSRobert Hancock { 675dc4d5fccSRobert Hancock struct phy_device *phydev = upstream; 676dc4d5fccSRobert Hancock __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); 677dc4d5fccSRobert Hancock __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); 678fd580c98SRussell King DECLARE_PHY_INTERFACE_MASK(interfaces); 679dc4d5fccSRobert Hancock phy_interface_t iface; 680dc4d5fccSRobert Hancock 681dc4d5fccSRobert Hancock linkmode_zero(phy_support); 682dc4d5fccSRobert Hancock phylink_set(phy_support, 1000baseX_Full); 683dc4d5fccSRobert Hancock phylink_set(phy_support, 1000baseT_Full); 684dc4d5fccSRobert Hancock phylink_set(phy_support, Autoneg); 685dc4d5fccSRobert Hancock phylink_set(phy_support, Pause); 686dc4d5fccSRobert Hancock phylink_set(phy_support, Asym_Pause); 687dc4d5fccSRobert Hancock 688dc4d5fccSRobert Hancock linkmode_zero(sfp_support); 689fd580c98SRussell King sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces); 690dc4d5fccSRobert Hancock /* Some modules support 10G modes as well as others we support. 691dc4d5fccSRobert Hancock * Mask out non-supported modes so the correct interface is picked. 692dc4d5fccSRobert Hancock */ 693dc4d5fccSRobert Hancock linkmode_and(sfp_support, phy_support, sfp_support); 694dc4d5fccSRobert Hancock 695dc4d5fccSRobert Hancock if (linkmode_empty(sfp_support)) { 696dc4d5fccSRobert Hancock dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); 697dc4d5fccSRobert Hancock return -EINVAL; 698dc4d5fccSRobert Hancock } 699dc4d5fccSRobert Hancock 700dc4d5fccSRobert Hancock iface = sfp_select_interface(phydev->sfp_bus, sfp_support); 701dc4d5fccSRobert Hancock 702dc4d5fccSRobert Hancock /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes 703dc4d5fccSRobert Hancock * interface for use with SFP modules. 704dc4d5fccSRobert Hancock * However, some copper modules detected as having a preferred SGMII 705dc4d5fccSRobert Hancock * interface do default to and function in 1000Base-X mode, so just 706dc4d5fccSRobert Hancock * print a warning and allow such modules, as they may have some chance 707dc4d5fccSRobert Hancock * of working. 708dc4d5fccSRobert Hancock */ 709dc4d5fccSRobert Hancock if (iface == PHY_INTERFACE_MODE_SGMII) 710dc4d5fccSRobert Hancock dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); 711dc4d5fccSRobert Hancock else if (iface != PHY_INTERFACE_MODE_1000BASEX) 712dc4d5fccSRobert Hancock return -EINVAL; 713dc4d5fccSRobert Hancock 714dc4d5fccSRobert Hancock return 0; 715dc4d5fccSRobert Hancock } 716dc4d5fccSRobert Hancock 717dc4d5fccSRobert Hancock static const struct sfp_upstream_ops at803x_sfp_ops = { 718dc4d5fccSRobert Hancock .attach = phy_sfp_attach, 719dc4d5fccSRobert Hancock .detach = phy_sfp_detach, 720dc4d5fccSRobert Hancock .module_insert = at803x_sfp_insert, 721dc4d5fccSRobert Hancock }; 722dc4d5fccSRobert Hancock 7232f664823SMichael Walle static int at803x_parse_dt(struct phy_device *phydev) 7242f664823SMichael Walle { 7252f664823SMichael Walle struct device_node *node = phydev->mdio.dev.of_node; 7262f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 727390b4cadSRussell King u32 freq, strength, tw; 7283f2edd30SAndrew Lunn unsigned int sel; 7292f664823SMichael Walle int ret; 7302f664823SMichael Walle 7312f664823SMichael Walle if (!IS_ENABLED(CONFIG_OF_MDIO)) 7322f664823SMichael Walle return 0; 7332f664823SMichael Walle 734390b4cadSRussell King if (of_property_read_bool(node, "qca,disable-smarteee")) 735390b4cadSRussell King priv->flags |= AT803X_DISABLE_SMARTEEE; 736390b4cadSRussell King 7379ecf0401SWei Fang if (of_property_read_bool(node, "qca,disable-hibernation-mode")) 7389ecf0401SWei Fang priv->flags |= AT803X_DISABLE_HIBERNATION_MODE; 7399ecf0401SWei Fang 740390b4cadSRussell King if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 741390b4cadSRussell King if (!tw || tw > 255) { 742390b4cadSRussell King phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 743390b4cadSRussell King return -EINVAL; 744390b4cadSRussell King } 745390b4cadSRussell King priv->smarteee_lpi_tw_1g = tw; 746390b4cadSRussell King } 747390b4cadSRussell King 748390b4cadSRussell King if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 749390b4cadSRussell King if (!tw || tw > 255) { 750390b4cadSRussell King phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 751390b4cadSRussell King return -EINVAL; 752390b4cadSRussell King } 753390b4cadSRussell King priv->smarteee_lpi_tw_100m = tw; 754390b4cadSRussell King } 755390b4cadSRussell King 7562f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 7572f664823SMichael Walle if (!ret) { 7582f664823SMichael Walle switch (freq) { 7592f664823SMichael Walle case 25000000: 7602f664823SMichael Walle sel = AT803X_CLK_OUT_25MHZ_XTAL; 7612f664823SMichael Walle break; 7622f664823SMichael Walle case 50000000: 7632f664823SMichael Walle sel = AT803X_CLK_OUT_50MHZ_PLL; 7642f664823SMichael Walle break; 7652f664823SMichael Walle case 62500000: 7662f664823SMichael Walle sel = AT803X_CLK_OUT_62_5MHZ_PLL; 7672f664823SMichael Walle break; 7682f664823SMichael Walle case 125000000: 7692f664823SMichael Walle sel = AT803X_CLK_OUT_125MHZ_PLL; 7702f664823SMichael Walle break; 7712f664823SMichael Walle default: 7722f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 7732f664823SMichael Walle return -EINVAL; 7742f664823SMichael Walle } 7752f664823SMichael Walle 7763f2edd30SAndrew Lunn priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 7773f2edd30SAndrew Lunn priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 7782f664823SMichael Walle 7792f664823SMichael Walle /* Fixup for the AR8030/AR8035. This chip has another mask and 7802f664823SMichael Walle * doesn't support the DSP reference. Eg. the lowest bit of the 7812f664823SMichael Walle * mask. The upper two bits select the same frequencies. Mask 7822f664823SMichael Walle * the lowest bit here. 7832f664823SMichael Walle * 7842f664823SMichael Walle * Warning: 7852f664823SMichael Walle * There was no datasheet for the AR8030 available so this is 7862f664823SMichael Walle * just a guess. But the AR8035 is listed as pin compatible 7872f664823SMichael Walle * to the AR8030 so there might be a good chance it works on 7882f664823SMichael Walle * the AR8030 too. 7892f664823SMichael Walle */ 7908887ca54SRussell King if (phydev->drv->phy_id == ATH8030_PHY_ID || 7918887ca54SRussell King phydev->drv->phy_id == ATH8035_PHY_ID) { 792b1f4c209SOleksij Rempel priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 793b1f4c209SOleksij Rempel priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 7942f664823SMichael Walle } 7952f664823SMichael Walle } 7962f664823SMichael Walle 7972f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 7982f664823SMichael Walle if (!ret) { 7992f664823SMichael Walle priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 8002f664823SMichael Walle switch (strength) { 8012f664823SMichael Walle case AR803X_STRENGTH_FULL: 8022f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 8032f664823SMichael Walle break; 8042f664823SMichael Walle case AR803X_STRENGTH_HALF: 8052f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 8062f664823SMichael Walle break; 8072f664823SMichael Walle case AR803X_STRENGTH_QUARTER: 8082f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 8092f664823SMichael Walle break; 8102f664823SMichael Walle default: 8112f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-strength\n"); 8122f664823SMichael Walle return -EINVAL; 8132f664823SMichael Walle } 8142f664823SMichael Walle } 8152f664823SMichael Walle 816428061f7SMichael Walle /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 817428061f7SMichael Walle * options. 818428061f7SMichael Walle */ 8198887ca54SRussell King if (phydev->drv->phy_id == ATH8031_PHY_ID) { 8202f664823SMichael Walle if (of_property_read_bool(node, "qca,keep-pll-enabled")) 8212f664823SMichael Walle priv->flags |= AT803X_KEEP_PLL_ENABLED; 8222f664823SMichael Walle 8232f664823SMichael Walle ret = at8031_register_regulators(phydev); 8242f664823SMichael Walle if (ret < 0) 8252f664823SMichael Walle return ret; 8262f664823SMichael Walle 8272f664823SMichael Walle priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 8282f664823SMichael Walle "vddio"); 8292f664823SMichael Walle if (IS_ERR(priv->vddio)) { 8302f664823SMichael Walle phydev_err(phydev, "failed to get VDDIO regulator\n"); 8312f664823SMichael Walle return PTR_ERR(priv->vddio); 8322f664823SMichael Walle } 833dc4d5fccSRobert Hancock 834dc4d5fccSRobert Hancock /* Only AR8031/8033 support 1000Base-X for SFP modules */ 835dc4d5fccSRobert Hancock ret = phy_sfp_probe(phydev, &at803x_sfp_ops); 836dc4d5fccSRobert Hancock if (ret < 0) 837dc4d5fccSRobert Hancock return ret; 8382f664823SMichael Walle } 8392f664823SMichael Walle 8402f664823SMichael Walle return 0; 8412f664823SMichael Walle } 8422f664823SMichael Walle 8432f664823SMichael Walle static int at803x_probe(struct phy_device *phydev) 8442f664823SMichael Walle { 8452f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 8462f664823SMichael Walle struct at803x_priv *priv; 847c329e5afSDavid Bauer int ret; 8482f664823SMichael Walle 8492f664823SMichael Walle priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 8502f664823SMichael Walle if (!priv) 8512f664823SMichael Walle return -ENOMEM; 8522f664823SMichael Walle 8532f664823SMichael Walle phydev->priv = priv; 8542f664823SMichael Walle 855c329e5afSDavid Bauer ret = at803x_parse_dt(phydev); 856c329e5afSDavid Bauer if (ret) 857c329e5afSDavid Bauer return ret; 858c329e5afSDavid Bauer 8598f7e8762SMichael Walle if (priv->vddio) { 8608f7e8762SMichael Walle ret = regulator_enable(priv->vddio); 8618f7e8762SMichael Walle if (ret < 0) 8628f7e8762SMichael Walle return ret; 8638f7e8762SMichael Walle } 8648f7e8762SMichael Walle 8653265f421SRobert Hancock if (phydev->drv->phy_id == ATH8031_PHY_ID) { 8663265f421SRobert Hancock int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 8673265f421SRobert Hancock int mode_cfg; 868d7cd5e06SViorel Suman struct ethtool_wolinfo wol = { 869d7cd5e06SViorel Suman .wolopts = 0, 870d7cd5e06SViorel Suman }; 8713265f421SRobert Hancock 8721f0dd412SWei Yongjun if (ccr < 0) { 8731f0dd412SWei Yongjun ret = ccr; 8743265f421SRobert Hancock goto err; 8751f0dd412SWei Yongjun } 8763265f421SRobert Hancock mode_cfg = ccr & AT803X_MODE_CFG_MASK; 8773265f421SRobert Hancock 8783265f421SRobert Hancock switch (mode_cfg) { 8793265f421SRobert Hancock case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 8803265f421SRobert Hancock case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 8813265f421SRobert Hancock priv->is_1000basex = true; 8823265f421SRobert Hancock fallthrough; 8833265f421SRobert Hancock case AT803X_MODE_CFG_FX100_RGMII_50OHM: 8843265f421SRobert Hancock case AT803X_MODE_CFG_FX100_RGMII_75OHM: 8853265f421SRobert Hancock priv->is_fiber = true; 8863265f421SRobert Hancock break; 8873265f421SRobert Hancock } 888d7cd5e06SViorel Suman 889d7cd5e06SViorel Suman /* Disable WOL by default */ 890d7cd5e06SViorel Suman ret = at803x_set_wol(phydev, &wol); 891d7cd5e06SViorel Suman if (ret < 0) { 892d7cd5e06SViorel Suman phydev_err(phydev, "failed to disable WOL on probe: %d\n", ret); 893d7cd5e06SViorel Suman goto err; 894d7cd5e06SViorel Suman } 8953265f421SRobert Hancock } 8963265f421SRobert Hancock 8978f7e8762SMichael Walle return 0; 8983265f421SRobert Hancock 8993265f421SRobert Hancock err: 9003265f421SRobert Hancock if (priv->vddio) 9013265f421SRobert Hancock regulator_disable(priv->vddio); 9023265f421SRobert Hancock 9033265f421SRobert Hancock return ret; 9042f664823SMichael Walle } 9052f664823SMichael Walle 9062318ca8aSMichael Walle static void at803x_remove(struct phy_device *phydev) 9072318ca8aSMichael Walle { 9082318ca8aSMichael Walle struct at803x_priv *priv = phydev->priv; 9092318ca8aSMichael Walle 9102318ca8aSMichael Walle if (priv->vddio) 9112318ca8aSMichael Walle regulator_disable(priv->vddio); 9122318ca8aSMichael Walle } 9132318ca8aSMichael Walle 914b856150cSDavid Bauer static int at803x_get_features(struct phy_device *phydev) 915b856150cSDavid Bauer { 9163265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 917b856150cSDavid Bauer int err; 918b856150cSDavid Bauer 919b856150cSDavid Bauer err = genphy_read_abilities(phydev); 920b856150cSDavid Bauer if (err) 921b856150cSDavid Bauer return err; 922b856150cSDavid Bauer 923765c22aaSLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) { 924765c22aaSLuo Jie err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); 925765c22aaSLuo Jie if (err < 0) 926765c22aaSLuo Jie return err; 927765c22aaSLuo Jie 928765c22aaSLuo Jie linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 929765c22aaSLuo Jie err & MDIO_PMA_NG_EXTABLE_2_5GBT); 930765c22aaSLuo Jie } 931765c22aaSLuo Jie 932f5621a01SVladimir Oltean if (phydev->drv->phy_id != ATH8031_PHY_ID) 933b856150cSDavid Bauer return 0; 934b856150cSDavid Bauer 935b856150cSDavid Bauer /* AR8031/AR8033 have different status registers 936b856150cSDavid Bauer * for copper and fiber operation. However, the 937b856150cSDavid Bauer * extended status register is the same for both 938b856150cSDavid Bauer * operation modes. 939b856150cSDavid Bauer * 940b856150cSDavid Bauer * As a result of that, ESTATUS_1000_XFULL is set 941b856150cSDavid Bauer * to 1 even when operating in copper TP mode. 942b856150cSDavid Bauer * 9433265f421SRobert Hancock * Remove this mode from the supported link modes 9443265f421SRobert Hancock * when not operating in 1000BaseX mode. 945b856150cSDavid Bauer */ 9463265f421SRobert Hancock if (!priv->is_1000basex) 947b856150cSDavid Bauer linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 948b856150cSDavid Bauer phydev->supported); 9493265f421SRobert Hancock 950b856150cSDavid Bauer return 0; 951b856150cSDavid Bauer } 952b856150cSDavid Bauer 953390b4cadSRussell King static int at803x_smarteee_config(struct phy_device *phydev) 954390b4cadSRussell King { 955390b4cadSRussell King struct at803x_priv *priv = phydev->priv; 956390b4cadSRussell King u16 mask = 0, val = 0; 957390b4cadSRussell King int ret; 958390b4cadSRussell King 959390b4cadSRussell King if (priv->flags & AT803X_DISABLE_SMARTEEE) 960390b4cadSRussell King return phy_modify_mmd(phydev, MDIO_MMD_PCS, 961390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3, 962390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 963390b4cadSRussell King 964390b4cadSRussell King if (priv->smarteee_lpi_tw_1g) { 965390b4cadSRussell King mask |= 0xff00; 966390b4cadSRussell King val |= priv->smarteee_lpi_tw_1g << 8; 967390b4cadSRussell King } 968390b4cadSRussell King if (priv->smarteee_lpi_tw_100m) { 969390b4cadSRussell King mask |= 0x00ff; 970390b4cadSRussell King val |= priv->smarteee_lpi_tw_100m; 971390b4cadSRussell King } 972390b4cadSRussell King if (!mask) 973390b4cadSRussell King return 0; 974390b4cadSRussell King 975390b4cadSRussell King ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 976390b4cadSRussell King mask, val); 977390b4cadSRussell King if (ret) 978390b4cadSRussell King return ret; 979390b4cadSRussell King 980390b4cadSRussell King return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 981390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 982390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 983390b4cadSRussell King } 984390b4cadSRussell King 9852f664823SMichael Walle static int at803x_clk_out_config(struct phy_device *phydev) 9862f664823SMichael Walle { 9872f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 9882f664823SMichael Walle 9892f664823SMichael Walle if (!priv->clk_25m_mask) 9902f664823SMichael Walle return 0; 9912f664823SMichael Walle 992a45c1c10SRussell King return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 993a45c1c10SRussell King priv->clk_25m_mask, priv->clk_25m_reg); 9942f664823SMichael Walle } 9952f664823SMichael Walle 9962f664823SMichael Walle static int at8031_pll_config(struct phy_device *phydev) 9972f664823SMichael Walle { 9982f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 9992f664823SMichael Walle 10002f664823SMichael Walle /* The default after hardware reset is PLL OFF. After a soft reset, the 10012f664823SMichael Walle * values are retained. 10022f664823SMichael Walle */ 10032f664823SMichael Walle if (priv->flags & AT803X_KEEP_PLL_ENABLED) 10042f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 10052f664823SMichael Walle 0, AT803X_DEBUG_PLL_ON); 10062f664823SMichael Walle else 10072f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 10082f664823SMichael Walle AT803X_DEBUG_PLL_ON, 0); 10092f664823SMichael Walle } 10102f664823SMichael Walle 10119ecf0401SWei Fang static int at803x_hibernation_mode_config(struct phy_device *phydev) 10129ecf0401SWei Fang { 10139ecf0401SWei Fang struct at803x_priv *priv = phydev->priv; 10149ecf0401SWei Fang 10159ecf0401SWei Fang /* The default after hardware reset is hibernation mode enabled. After 10169ecf0401SWei Fang * software reset, the value is retained. 10179ecf0401SWei Fang */ 10189ecf0401SWei Fang if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) 10199ecf0401SWei Fang return 0; 10209ecf0401SWei Fang 10219ecf0401SWei Fang return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 10229ecf0401SWei Fang AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0); 10239ecf0401SWei Fang } 10249ecf0401SWei Fang 10250ca7111aSMatus Ujhelyi static int at803x_config_init(struct phy_device *phydev) 10260ca7111aSMatus Ujhelyi { 10273265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 10281ca6d1b1SMugunthan V N int ret; 10290ca7111aSMatus Ujhelyi 10304f3a00c7SRobert Hancock if (phydev->drv->phy_id == ATH8031_PHY_ID) { 10314f3a00c7SRobert Hancock /* Some bootloaders leave the fiber page selected. 10323265f421SRobert Hancock * Switch to the appropriate page (fiber or copper), as otherwise we 10333265f421SRobert Hancock * read the PHY capabilities from the wrong page. 10344f3a00c7SRobert Hancock */ 10354f3a00c7SRobert Hancock phy_lock_mdio_bus(phydev); 10363265f421SRobert Hancock ret = at803x_write_page(phydev, 10373265f421SRobert Hancock priv->is_fiber ? AT803X_PAGE_FIBER : 10383265f421SRobert Hancock AT803X_PAGE_COPPER); 10394f3a00c7SRobert Hancock phy_unlock_mdio_bus(phydev); 10404f3a00c7SRobert Hancock if (ret) 10414f3a00c7SRobert Hancock return ret; 10424f3a00c7SRobert Hancock 10434f3a00c7SRobert Hancock ret = at8031_pll_config(phydev); 10444f3a00c7SRobert Hancock if (ret < 0) 10454f3a00c7SRobert Hancock return ret; 10464f3a00c7SRobert Hancock } 10474f3a00c7SRobert Hancock 10486d4cd041SVinod Koul /* The RX and TX delay default is: 10496d4cd041SVinod Koul * after HW reset: RX delay enabled and TX delay disabled 10506d4cd041SVinod Koul * after SW reset: RX delay enabled, while TX delay retains the 10516d4cd041SVinod Koul * value before reset. 10526d4cd041SVinod Koul */ 1053bb0ce4c1SAndré Draszik if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1054bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1055bb0ce4c1SAndré Draszik ret = at803x_enable_rx_delay(phydev); 1056bb0ce4c1SAndré Draszik else 1057cd28d1d6SVinod Koul ret = at803x_disable_rx_delay(phydev); 10582e5f9f28SMartin Blumenstingl if (ret < 0) 10591ca6d1b1SMugunthan V N return ret; 10606d4cd041SVinod Koul 10616d4cd041SVinod Koul if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 1062bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 10636d4cd041SVinod Koul ret = at803x_enable_tx_delay(phydev); 1064bb0ce4c1SAndré Draszik else 1065bb0ce4c1SAndré Draszik ret = at803x_disable_tx_delay(phydev); 10662f664823SMichael Walle if (ret < 0) 10676d4cd041SVinod Koul return ret; 10682f664823SMichael Walle 1069390b4cadSRussell King ret = at803x_smarteee_config(phydev); 1070390b4cadSRussell King if (ret < 0) 1071390b4cadSRussell King return ret; 1072390b4cadSRussell King 10732f664823SMichael Walle ret = at803x_clk_out_config(phydev); 10742f664823SMichael Walle if (ret < 0) 10752f664823SMichael Walle return ret; 10762f664823SMichael Walle 10779ecf0401SWei Fang ret = at803x_hibernation_mode_config(phydev); 10789ecf0401SWei Fang if (ret < 0) 10799ecf0401SWei Fang return ret; 10809ecf0401SWei Fang 10813c51fa5dSRussell King /* Ar803x extended next page bit is enabled by default. Cisco 10823c51fa5dSRussell King * multigig switches read this bit and attempt to negotiate 10Gbps 10833c51fa5dSRussell King * rates even if the next page bit is disabled. This is incorrect 10843c51fa5dSRussell King * behaviour but we still need to accommodate it. XNP is only needed 10853c51fa5dSRussell King * for 10Gbps support, so disable XNP. 10863c51fa5dSRussell King */ 10873c51fa5dSRussell King return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 10880ca7111aSMatus Ujhelyi } 10890ca7111aSMatus Ujhelyi 109077a99394SZhao Qiang static int at803x_ack_interrupt(struct phy_device *phydev) 109177a99394SZhao Qiang { 109277a99394SZhao Qiang int err; 109377a99394SZhao Qiang 1094a46bd63bSMartin Blumenstingl err = phy_read(phydev, AT803X_INTR_STATUS); 109577a99394SZhao Qiang 109677a99394SZhao Qiang return (err < 0) ? err : 0; 109777a99394SZhao Qiang } 109877a99394SZhao Qiang 109977a99394SZhao Qiang static int at803x_config_intr(struct phy_device *phydev) 110077a99394SZhao Qiang { 11013265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 110277a99394SZhao Qiang int err; 110377a99394SZhao Qiang int value; 110477a99394SZhao Qiang 1105a46bd63bSMartin Blumenstingl value = phy_read(phydev, AT803X_INTR_ENABLE); 110677a99394SZhao Qiang 1107e6e4a556SMartin Blumenstingl if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1108a3417885SIoana Ciornei /* Clear any pending interrupts */ 1109a3417885SIoana Ciornei err = at803x_ack_interrupt(phydev); 1110a3417885SIoana Ciornei if (err) 1111a3417885SIoana Ciornei return err; 1112a3417885SIoana Ciornei 1113e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 1114e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 1115e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 1116e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_FAIL; 1117e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 11183265f421SRobert Hancock if (priv->is_fiber) { 11193265f421SRobert Hancock value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 11203265f421SRobert Hancock value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 11213265f421SRobert Hancock } 1122e6e4a556SMartin Blumenstingl 1123e6e4a556SMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, value); 1124a3417885SIoana Ciornei } else { 1125a46bd63bSMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 1126a3417885SIoana Ciornei if (err) 1127a3417885SIoana Ciornei return err; 1128a3417885SIoana Ciornei 1129a3417885SIoana Ciornei /* Clear any pending interrupts */ 1130a3417885SIoana Ciornei err = at803x_ack_interrupt(phydev); 1131a3417885SIoana Ciornei } 113277a99394SZhao Qiang 113377a99394SZhao Qiang return err; 113477a99394SZhao Qiang } 113577a99394SZhao Qiang 113629773097SIoana Ciornei static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 113729773097SIoana Ciornei { 113829773097SIoana Ciornei int irq_status, int_enabled; 113929773097SIoana Ciornei 114029773097SIoana Ciornei irq_status = phy_read(phydev, AT803X_INTR_STATUS); 114129773097SIoana Ciornei if (irq_status < 0) { 114229773097SIoana Ciornei phy_error(phydev); 114329773097SIoana Ciornei return IRQ_NONE; 114429773097SIoana Ciornei } 114529773097SIoana Ciornei 114629773097SIoana Ciornei /* Read the current enabled interrupts */ 114729773097SIoana Ciornei int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 114829773097SIoana Ciornei if (int_enabled < 0) { 114929773097SIoana Ciornei phy_error(phydev); 115029773097SIoana Ciornei return IRQ_NONE; 115129773097SIoana Ciornei } 115229773097SIoana Ciornei 115329773097SIoana Ciornei /* See if this was one of our enabled interrupts */ 115429773097SIoana Ciornei if (!(irq_status & int_enabled)) 115529773097SIoana Ciornei return IRQ_NONE; 115629773097SIoana Ciornei 115729773097SIoana Ciornei phy_trigger_machine(phydev); 115829773097SIoana Ciornei 115929773097SIoana Ciornei return IRQ_HANDLED; 116029773097SIoana Ciornei } 116129773097SIoana Ciornei 116213a56b44SDaniel Mack static void at803x_link_change_notify(struct phy_device *phydev) 116313a56b44SDaniel Mack { 116413a56b44SDaniel Mack /* 116513a56b44SDaniel Mack * Conduct a hardware reset for AT8030 every time a link loss is 116613a56b44SDaniel Mack * signalled. This is necessary to circumvent a hardware bug that 116713a56b44SDaniel Mack * occurs when the cable is unplugged while TX packets are pending 116813a56b44SDaniel Mack * in the FIFO. In such cases, the FIFO enters an error mode it 116913a56b44SDaniel Mack * cannot recover from by software. 117013a56b44SDaniel Mack */ 11716110ed2dSDavid Bauer if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 117213a56b44SDaniel Mack struct at803x_context context; 117313a56b44SDaniel Mack 117413a56b44SDaniel Mack at803x_context_save(phydev, &context); 117513a56b44SDaniel Mack 1176bafbdd52SSergei Shtylyov phy_device_reset(phydev, 1); 117713a56b44SDaniel Mack msleep(1); 1178bafbdd52SSergei Shtylyov phy_device_reset(phydev, 0); 1179d57019d1SSergei Shtylyov msleep(1); 118013a56b44SDaniel Mack 118113a56b44SDaniel Mack at803x_context_restore(phydev, &context); 118213a56b44SDaniel Mack 11835c5f626bSHeiner Kallweit phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 118413a56b44SDaniel Mack } 118513a56b44SDaniel Mack } 118613a56b44SDaniel Mack 118779c7bc05SLuo Jie static int at803x_read_specific_status(struct phy_device *phydev) 118806d5f344SRussell King { 118979c7bc05SLuo Jie int ss; 119006d5f344SRussell King 119106d5f344SRussell King /* Read the AT8035 PHY-Specific Status register, which indicates the 119206d5f344SRussell King * speed and duplex that the PHY is actually using, irrespective of 119306d5f344SRussell King * whether we are in autoneg mode or not. 119406d5f344SRussell King */ 119506d5f344SRussell King ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 119606d5f344SRussell King if (ss < 0) 119706d5f344SRussell King return ss; 119806d5f344SRussell King 119906d5f344SRussell King if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 120079c7bc05SLuo Jie int sfc, speed; 12017dce80c2SOleksij Rempel 12027dce80c2SOleksij Rempel sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 12037dce80c2SOleksij Rempel if (sfc < 0) 12047dce80c2SOleksij Rempel return sfc; 12057dce80c2SOleksij Rempel 120679c7bc05SLuo Jie /* qca8081 takes the different bits for speed value from at803x */ 120779c7bc05SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) 120879c7bc05SLuo Jie speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 120979c7bc05SLuo Jie else 121079c7bc05SLuo Jie speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 121179c7bc05SLuo Jie 121279c7bc05SLuo Jie switch (speed) { 121306d5f344SRussell King case AT803X_SS_SPEED_10: 121406d5f344SRussell King phydev->speed = SPEED_10; 121506d5f344SRussell King break; 121606d5f344SRussell King case AT803X_SS_SPEED_100: 121706d5f344SRussell King phydev->speed = SPEED_100; 121806d5f344SRussell King break; 121906d5f344SRussell King case AT803X_SS_SPEED_1000: 122006d5f344SRussell King phydev->speed = SPEED_1000; 122106d5f344SRussell King break; 122279c7bc05SLuo Jie case QCA808X_SS_SPEED_2500: 122379c7bc05SLuo Jie phydev->speed = SPEED_2500; 122479c7bc05SLuo Jie break; 122506d5f344SRussell King } 122606d5f344SRussell King if (ss & AT803X_SS_DUPLEX) 122706d5f344SRussell King phydev->duplex = DUPLEX_FULL; 122806d5f344SRussell King else 122906d5f344SRussell King phydev->duplex = DUPLEX_HALF; 12307dce80c2SOleksij Rempel 123106d5f344SRussell King if (ss & AT803X_SS_MDIX) 123206d5f344SRussell King phydev->mdix = ETH_TP_MDI_X; 123306d5f344SRussell King else 123406d5f344SRussell King phydev->mdix = ETH_TP_MDI; 12357dce80c2SOleksij Rempel 12367dce80c2SOleksij Rempel switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 12377dce80c2SOleksij Rempel case AT803X_SFC_MANUAL_MDI: 12387dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI; 12397dce80c2SOleksij Rempel break; 12407dce80c2SOleksij Rempel case AT803X_SFC_MANUAL_MDIX: 12417dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_X; 12427dce80c2SOleksij Rempel break; 12437dce80c2SOleksij Rempel case AT803X_SFC_AUTOMATIC_CROSSOVER: 12447dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 12457dce80c2SOleksij Rempel break; 12467dce80c2SOleksij Rempel } 124706d5f344SRussell King } 124806d5f344SRussell King 124979c7bc05SLuo Jie return 0; 125079c7bc05SLuo Jie } 125179c7bc05SLuo Jie 125279c7bc05SLuo Jie static int at803x_read_status(struct phy_device *phydev) 125379c7bc05SLuo Jie { 12543265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 125579c7bc05SLuo Jie int err, old_link = phydev->link; 125679c7bc05SLuo Jie 12573265f421SRobert Hancock if (priv->is_1000basex) 12583265f421SRobert Hancock return genphy_c37_read_status(phydev); 12593265f421SRobert Hancock 126079c7bc05SLuo Jie /* Update the link, but return if there was an error */ 126179c7bc05SLuo Jie err = genphy_update_link(phydev); 126279c7bc05SLuo Jie if (err) 126379c7bc05SLuo Jie return err; 126479c7bc05SLuo Jie 126579c7bc05SLuo Jie /* why bother the PHY if nothing can have changed */ 126679c7bc05SLuo Jie if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 126779c7bc05SLuo Jie return 0; 126879c7bc05SLuo Jie 126979c7bc05SLuo Jie phydev->speed = SPEED_UNKNOWN; 127079c7bc05SLuo Jie phydev->duplex = DUPLEX_UNKNOWN; 127179c7bc05SLuo Jie phydev->pause = 0; 127279c7bc05SLuo Jie phydev->asym_pause = 0; 127379c7bc05SLuo Jie 127479c7bc05SLuo Jie err = genphy_read_lpa(phydev); 127579c7bc05SLuo Jie if (err < 0) 127679c7bc05SLuo Jie return err; 127779c7bc05SLuo Jie 127879c7bc05SLuo Jie err = at803x_read_specific_status(phydev); 127979c7bc05SLuo Jie if (err < 0) 128079c7bc05SLuo Jie return err; 128179c7bc05SLuo Jie 128206d5f344SRussell King if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 128306d5f344SRussell King phy_resolve_aneg_pause(phydev); 128406d5f344SRussell King 128506d5f344SRussell King return 0; 128606d5f344SRussell King } 128706d5f344SRussell King 12887dce80c2SOleksij Rempel static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 12897dce80c2SOleksij Rempel { 12907dce80c2SOleksij Rempel u16 val; 12917dce80c2SOleksij Rempel 12927dce80c2SOleksij Rempel switch (ctrl) { 12937dce80c2SOleksij Rempel case ETH_TP_MDI: 12947dce80c2SOleksij Rempel val = AT803X_SFC_MANUAL_MDI; 12957dce80c2SOleksij Rempel break; 12967dce80c2SOleksij Rempel case ETH_TP_MDI_X: 12977dce80c2SOleksij Rempel val = AT803X_SFC_MANUAL_MDIX; 12987dce80c2SOleksij Rempel break; 12997dce80c2SOleksij Rempel case ETH_TP_MDI_AUTO: 13007dce80c2SOleksij Rempel val = AT803X_SFC_AUTOMATIC_CROSSOVER; 13017dce80c2SOleksij Rempel break; 13027dce80c2SOleksij Rempel default: 13037dce80c2SOleksij Rempel return 0; 13047dce80c2SOleksij Rempel } 13057dce80c2SOleksij Rempel 13067dce80c2SOleksij Rempel return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 13077dce80c2SOleksij Rempel AT803X_SFC_MDI_CROSSOVER_MODE_M, 13087dce80c2SOleksij Rempel FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 13097dce80c2SOleksij Rempel } 13107dce80c2SOleksij Rempel 13117dce80c2SOleksij Rempel static int at803x_config_aneg(struct phy_device *phydev) 13127dce80c2SOleksij Rempel { 13133265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 13147dce80c2SOleksij Rempel int ret; 13157dce80c2SOleksij Rempel 13167dce80c2SOleksij Rempel ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 13177dce80c2SOleksij Rempel if (ret < 0) 13187dce80c2SOleksij Rempel return ret; 13197dce80c2SOleksij Rempel 13207dce80c2SOleksij Rempel /* Changes of the midx bits are disruptive to the normal operation; 13217dce80c2SOleksij Rempel * therefore any changes to these registers must be followed by a 13227dce80c2SOleksij Rempel * software reset to take effect. 13237dce80c2SOleksij Rempel */ 13247dce80c2SOleksij Rempel if (ret == 1) { 13257dce80c2SOleksij Rempel ret = genphy_soft_reset(phydev); 13267dce80c2SOleksij Rempel if (ret < 0) 13277dce80c2SOleksij Rempel return ret; 13287dce80c2SOleksij Rempel } 13297dce80c2SOleksij Rempel 13303265f421SRobert Hancock if (priv->is_1000basex) 13313265f421SRobert Hancock return genphy_c37_config_aneg(phydev); 13323265f421SRobert Hancock 1333f884d449SLuo Jie /* Do not restart auto-negotiation by setting ret to 0 defautly, 1334f884d449SLuo Jie * when calling __genphy_config_aneg later. 1335f884d449SLuo Jie */ 1336f884d449SLuo Jie ret = 0; 1337f884d449SLuo Jie 1338f884d449SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1339f884d449SLuo Jie int phy_ctrl = 0; 1340f884d449SLuo Jie 1341f884d449SLuo Jie /* The reg MII_BMCR also needs to be configured for force mode, the 1342f884d449SLuo Jie * genphy_config_aneg is also needed. 1343f884d449SLuo Jie */ 1344f884d449SLuo Jie if (phydev->autoneg == AUTONEG_DISABLE) 1345f884d449SLuo Jie genphy_c45_pma_setup_forced(phydev); 1346f884d449SLuo Jie 1347f884d449SLuo Jie if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1348f884d449SLuo Jie phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1349f884d449SLuo Jie 1350f884d449SLuo Jie ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1351f884d449SLuo Jie MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1352f884d449SLuo Jie if (ret < 0) 1353f884d449SLuo Jie return ret; 1354f884d449SLuo Jie } 1355f884d449SLuo Jie 1356f884d449SLuo Jie return __genphy_config_aneg(phydev, ret); 13577dce80c2SOleksij Rempel } 13587dce80c2SOleksij Rempel 1359cde0f4f8SMichael Walle static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1360cde0f4f8SMichael Walle { 1361cde0f4f8SMichael Walle int val; 1362cde0f4f8SMichael Walle 1363cde0f4f8SMichael Walle val = phy_read(phydev, AT803X_SMART_SPEED); 1364cde0f4f8SMichael Walle if (val < 0) 1365cde0f4f8SMichael Walle return val; 1366cde0f4f8SMichael Walle 1367cde0f4f8SMichael Walle if (val & AT803X_SMART_SPEED_ENABLE) 1368cde0f4f8SMichael Walle *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1369cde0f4f8SMichael Walle else 1370cde0f4f8SMichael Walle *d = DOWNSHIFT_DEV_DISABLE; 1371cde0f4f8SMichael Walle 1372cde0f4f8SMichael Walle return 0; 1373cde0f4f8SMichael Walle } 1374cde0f4f8SMichael Walle 1375cde0f4f8SMichael Walle static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1376cde0f4f8SMichael Walle { 1377cde0f4f8SMichael Walle u16 mask, set; 1378cde0f4f8SMichael Walle int ret; 1379cde0f4f8SMichael Walle 1380cde0f4f8SMichael Walle switch (cnt) { 1381cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DEFAULT_COUNT: 1382cde0f4f8SMichael Walle cnt = AT803X_DEFAULT_DOWNSHIFT; 1383cde0f4f8SMichael Walle fallthrough; 1384cde0f4f8SMichael Walle case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1385cde0f4f8SMichael Walle set = AT803X_SMART_SPEED_ENABLE | 1386cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER | 1387cde0f4f8SMichael Walle FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1388cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1389cde0f4f8SMichael Walle break; 1390cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DISABLE: 1391cde0f4f8SMichael Walle set = 0; 1392cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_ENABLE | 1393cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER; 1394cde0f4f8SMichael Walle break; 1395cde0f4f8SMichael Walle default: 1396cde0f4f8SMichael Walle return -EINVAL; 1397cde0f4f8SMichael Walle } 1398cde0f4f8SMichael Walle 1399cde0f4f8SMichael Walle ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1400cde0f4f8SMichael Walle 1401cde0f4f8SMichael Walle /* After changing the smart speed settings, we need to perform a 1402cde0f4f8SMichael Walle * software reset, use phy_init_hw() to make sure we set the 1403cde0f4f8SMichael Walle * reapply any values which might got lost during software reset. 1404cde0f4f8SMichael Walle */ 1405cde0f4f8SMichael Walle if (ret == 1) 1406cde0f4f8SMichael Walle ret = phy_init_hw(phydev); 1407cde0f4f8SMichael Walle 1408cde0f4f8SMichael Walle return ret; 1409cde0f4f8SMichael Walle } 1410cde0f4f8SMichael Walle 1411cde0f4f8SMichael Walle static int at803x_get_tunable(struct phy_device *phydev, 1412cde0f4f8SMichael Walle struct ethtool_tunable *tuna, void *data) 1413cde0f4f8SMichael Walle { 1414cde0f4f8SMichael Walle switch (tuna->id) { 1415cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 1416cde0f4f8SMichael Walle return at803x_get_downshift(phydev, data); 1417cde0f4f8SMichael Walle default: 1418cde0f4f8SMichael Walle return -EOPNOTSUPP; 1419cde0f4f8SMichael Walle } 1420cde0f4f8SMichael Walle } 1421cde0f4f8SMichael Walle 1422cde0f4f8SMichael Walle static int at803x_set_tunable(struct phy_device *phydev, 1423cde0f4f8SMichael Walle struct ethtool_tunable *tuna, const void *data) 1424cde0f4f8SMichael Walle { 1425cde0f4f8SMichael Walle switch (tuna->id) { 1426cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 1427cde0f4f8SMichael Walle return at803x_set_downshift(phydev, *(const u8 *)data); 1428cde0f4f8SMichael Walle default: 1429cde0f4f8SMichael Walle return -EOPNOTSUPP; 1430cde0f4f8SMichael Walle } 1431cde0f4f8SMichael Walle } 1432cde0f4f8SMichael Walle 14336cb75767SMichael Walle static int at803x_cable_test_result_trans(u16 status) 14346cb75767SMichael Walle { 14356cb75767SMichael Walle switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 14366cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_NORMAL: 14376cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_OK; 14386cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_SHORT: 14396cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 14406cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_OPEN: 14416cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 14426cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_FAIL: 14436cb75767SMichael Walle default: 14446cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 14456cb75767SMichael Walle } 14466cb75767SMichael Walle } 14476cb75767SMichael Walle 14486cb75767SMichael Walle static bool at803x_cdt_test_failed(u16 status) 14496cb75767SMichael Walle { 14506cb75767SMichael Walle return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 14516cb75767SMichael Walle AT803X_CDT_STATUS_STAT_FAIL; 14526cb75767SMichael Walle } 14536cb75767SMichael Walle 14546cb75767SMichael Walle static bool at803x_cdt_fault_length_valid(u16 status) 14556cb75767SMichael Walle { 14566cb75767SMichael Walle switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 14576cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_OPEN: 14586cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_SHORT: 14596cb75767SMichael Walle return true; 14606cb75767SMichael Walle } 14616cb75767SMichael Walle return false; 14626cb75767SMichael Walle } 14636cb75767SMichael Walle 14646cb75767SMichael Walle static int at803x_cdt_fault_length(u16 status) 14656cb75767SMichael Walle { 14666cb75767SMichael Walle int dt; 14676cb75767SMichael Walle 14686cb75767SMichael Walle /* According to the datasheet the distance to the fault is 14696cb75767SMichael Walle * DELTA_TIME * 0.824 meters. 14706cb75767SMichael Walle * 14716cb75767SMichael Walle * The author suspect the correct formula is: 14726cb75767SMichael Walle * 14736cb75767SMichael Walle * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 14746cb75767SMichael Walle * 14756cb75767SMichael Walle * where c is the speed of light, VF is the velocity factor of 14766cb75767SMichael Walle * the twisted pair cable, 125MHz the counter frequency and 14776cb75767SMichael Walle * we need to divide by 2 because the hardware will measure the 14786cb75767SMichael Walle * round trip time to the fault and back to the PHY. 14796cb75767SMichael Walle * 14806cb75767SMichael Walle * With a VF of 0.69 we get the factor 0.824 mentioned in the 14816cb75767SMichael Walle * datasheet. 14826cb75767SMichael Walle */ 14836cb75767SMichael Walle dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 14846cb75767SMichael Walle 14856cb75767SMichael Walle return (dt * 824) / 10; 14866cb75767SMichael Walle } 14876cb75767SMichael Walle 14886cb75767SMichael Walle static int at803x_cdt_start(struct phy_device *phydev, int pair) 14896cb75767SMichael Walle { 14906cb75767SMichael Walle u16 cdt; 14916cb75767SMichael Walle 14928c84d752SLuo Jie /* qca8081 takes the different bit 15 to enable CDT test */ 14938c84d752SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) 14948c84d752SLuo Jie cdt = QCA808X_CDT_ENABLE_TEST | 14958c84d752SLuo Jie QCA808X_CDT_LENGTH_UNIT | 14968c84d752SLuo Jie QCA808X_CDT_INTER_CHECK_DIS; 14978c84d752SLuo Jie else 14986cb75767SMichael Walle cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 14996cb75767SMichael Walle AT803X_CDT_ENABLE_TEST; 15006cb75767SMichael Walle 15016cb75767SMichael Walle return phy_write(phydev, AT803X_CDT, cdt); 15026cb75767SMichael Walle } 15036cb75767SMichael Walle 15046cb75767SMichael Walle static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 15056cb75767SMichael Walle { 15066cb75767SMichael Walle int val, ret; 15078c84d752SLuo Jie u16 cdt_en; 15088c84d752SLuo Jie 15098c84d752SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) 15108c84d752SLuo Jie cdt_en = QCA808X_CDT_ENABLE_TEST; 15118c84d752SLuo Jie else 15128c84d752SLuo Jie cdt_en = AT803X_CDT_ENABLE_TEST; 15136cb75767SMichael Walle 15146cb75767SMichael Walle /* One test run takes about 25ms */ 15156cb75767SMichael Walle ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 15168c84d752SLuo Jie !(val & cdt_en), 15176cb75767SMichael Walle 30000, 100000, true); 15186cb75767SMichael Walle 15196cb75767SMichael Walle return ret < 0 ? ret : 0; 15206cb75767SMichael Walle } 15216cb75767SMichael Walle 15226cb75767SMichael Walle static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 15236cb75767SMichael Walle { 15246cb75767SMichael Walle static const int ethtool_pair[] = { 15256cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_A, 15266cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_B, 15276cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_C, 15286cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_D, 15296cb75767SMichael Walle }; 15306cb75767SMichael Walle int ret, val; 15316cb75767SMichael Walle 15326cb75767SMichael Walle ret = at803x_cdt_start(phydev, pair); 15336cb75767SMichael Walle if (ret) 15346cb75767SMichael Walle return ret; 15356cb75767SMichael Walle 15366cb75767SMichael Walle ret = at803x_cdt_wait_for_completion(phydev); 15376cb75767SMichael Walle if (ret) 15386cb75767SMichael Walle return ret; 15396cb75767SMichael Walle 15406cb75767SMichael Walle val = phy_read(phydev, AT803X_CDT_STATUS); 15416cb75767SMichael Walle if (val < 0) 15426cb75767SMichael Walle return val; 15436cb75767SMichael Walle 15446cb75767SMichael Walle if (at803x_cdt_test_failed(val)) 15456cb75767SMichael Walle return 0; 15466cb75767SMichael Walle 15476cb75767SMichael Walle ethnl_cable_test_result(phydev, ethtool_pair[pair], 15486cb75767SMichael Walle at803x_cable_test_result_trans(val)); 15496cb75767SMichael Walle 15506cb75767SMichael Walle if (at803x_cdt_fault_length_valid(val)) 15516cb75767SMichael Walle ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 15526cb75767SMichael Walle at803x_cdt_fault_length(val)); 15536cb75767SMichael Walle 15546cb75767SMichael Walle return 1; 15556cb75767SMichael Walle } 15566cb75767SMichael Walle 15576cb75767SMichael Walle static int at803x_cable_test_get_status(struct phy_device *phydev, 15586cb75767SMichael Walle bool *finished) 15596cb75767SMichael Walle { 1560dc0f3ed1SOleksij Rempel unsigned long pair_mask; 15616cb75767SMichael Walle int retries = 20; 15626cb75767SMichael Walle int pair, ret; 15636cb75767SMichael Walle 1564dc0f3ed1SOleksij Rempel if (phydev->phy_id == ATH9331_PHY_ID || 1565fada2ce0SDavid Bauer phydev->phy_id == ATH8032_PHY_ID || 1566fada2ce0SDavid Bauer phydev->phy_id == QCA9561_PHY_ID) 1567dc0f3ed1SOleksij Rempel pair_mask = 0x3; 1568dc0f3ed1SOleksij Rempel else 1569dc0f3ed1SOleksij Rempel pair_mask = 0xf; 1570dc0f3ed1SOleksij Rempel 15716cb75767SMichael Walle *finished = false; 15726cb75767SMichael Walle 15736cb75767SMichael Walle /* According to the datasheet the CDT can be performed when 15746cb75767SMichael Walle * there is no link partner or when the link partner is 15756cb75767SMichael Walle * auto-negotiating. Starting the test will restart the AN 15766cb75767SMichael Walle * automatically. It seems that doing this repeatedly we will 15776cb75767SMichael Walle * get a slot where our link partner won't disturb our 15786cb75767SMichael Walle * measurement. 15796cb75767SMichael Walle */ 15806cb75767SMichael Walle while (pair_mask && retries--) { 15816cb75767SMichael Walle for_each_set_bit(pair, &pair_mask, 4) { 15826cb75767SMichael Walle ret = at803x_cable_test_one_pair(phydev, pair); 15836cb75767SMichael Walle if (ret < 0) 15846cb75767SMichael Walle return ret; 15856cb75767SMichael Walle if (ret) 15866cb75767SMichael Walle clear_bit(pair, &pair_mask); 15876cb75767SMichael Walle } 15886cb75767SMichael Walle if (pair_mask) 15896cb75767SMichael Walle msleep(250); 15906cb75767SMichael Walle } 15916cb75767SMichael Walle 15926cb75767SMichael Walle *finished = true; 15936cb75767SMichael Walle 15946cb75767SMichael Walle return 0; 15956cb75767SMichael Walle } 15966cb75767SMichael Walle 15976cb75767SMichael Walle static int at803x_cable_test_start(struct phy_device *phydev) 15986cb75767SMichael Walle { 15996cb75767SMichael Walle /* Enable auto-negotiation, but advertise no capabilities, no link 16006cb75767SMichael Walle * will be established. A restart of the auto-negotiation is not 16016cb75767SMichael Walle * required, because the cable test will automatically break the link. 16026cb75767SMichael Walle */ 16036cb75767SMichael Walle phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 16046cb75767SMichael Walle phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1605dc0f3ed1SOleksij Rempel if (phydev->phy_id != ATH9331_PHY_ID && 1606fada2ce0SDavid Bauer phydev->phy_id != ATH8032_PHY_ID && 1607fada2ce0SDavid Bauer phydev->phy_id != QCA9561_PHY_ID) 16086cb75767SMichael Walle phy_write(phydev, MII_CTRL1000, 0); 16096cb75767SMichael Walle 16106cb75767SMichael Walle /* we do all the (time consuming) work later */ 16116cb75767SMichael Walle return 0; 16126cb75767SMichael Walle } 16136cb75767SMichael Walle 1614272833b9SAnsuel Smith static int qca83xx_config_init(struct phy_device *phydev) 1615272833b9SAnsuel Smith { 1616272833b9SAnsuel Smith u8 switch_revision; 1617272833b9SAnsuel Smith 1618272833b9SAnsuel Smith switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1619272833b9SAnsuel Smith 1620272833b9SAnsuel Smith switch (switch_revision) { 1621272833b9SAnsuel Smith case 1: 1622272833b9SAnsuel Smith /* For 100M waveform */ 162367999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1624272833b9SAnsuel Smith /* Turn on Gigabit clock */ 162567999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1626272833b9SAnsuel Smith break; 1627272833b9SAnsuel Smith 1628272833b9SAnsuel Smith case 2: 1629272833b9SAnsuel Smith phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1630272833b9SAnsuel Smith fallthrough; 1631272833b9SAnsuel Smith case 4: 1632272833b9SAnsuel Smith phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 163367999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 163467999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1635272833b9SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1636272833b9SAnsuel Smith break; 1637272833b9SAnsuel Smith } 1638272833b9SAnsuel Smith 16391ca83119SAnsuel Smith /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 16401ca83119SAnsuel Smith * Disable on init and enable only with 100m speed following 16411ca83119SAnsuel Smith * qca original source code. 16421ca83119SAnsuel Smith */ 16431ca83119SAnsuel Smith if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 16441ca83119SAnsuel Smith phydev->drv->phy_id == QCA8327_B_PHY_ID) 164567999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 16461ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 0); 16471ca83119SAnsuel Smith 16489d1c29b4SAnsuel Smith /* Following original QCA sourcecode set port to prefer master */ 16499d1c29b4SAnsuel Smith phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 16509d1c29b4SAnsuel Smith 1651272833b9SAnsuel Smith return 0; 1652272833b9SAnsuel Smith } 1653272833b9SAnsuel Smith 16541ca83119SAnsuel Smith static void qca83xx_link_change_notify(struct phy_device *phydev) 16551ca83119SAnsuel Smith { 16561ca83119SAnsuel Smith /* QCA8337 doesn't require DAC Amplitude adjustement */ 16571ca83119SAnsuel Smith if (phydev->drv->phy_id == QCA8337_PHY_ID) 16581ca83119SAnsuel Smith return; 16591ca83119SAnsuel Smith 16601ca83119SAnsuel Smith /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 16611ca83119SAnsuel Smith if (phydev->state == PHY_RUNNING) { 16621ca83119SAnsuel Smith if (phydev->speed == SPEED_100) 166367999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 16641ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 16651ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN); 16661ca83119SAnsuel Smith } else { 16671ca83119SAnsuel Smith /* Reset DAC Amplitude adjustment */ 166867999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 16691ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 0); 16701ca83119SAnsuel Smith } 16711ca83119SAnsuel Smith } 16721ca83119SAnsuel Smith 1673ba3c01eeSAnsuel Smith static int qca83xx_resume(struct phy_device *phydev) 1674ba3c01eeSAnsuel Smith { 1675ba3c01eeSAnsuel Smith int ret, val; 1676ba3c01eeSAnsuel Smith 1677ba3c01eeSAnsuel Smith /* Skip reset if not suspended */ 1678ba3c01eeSAnsuel Smith if (!phydev->suspended) 1679ba3c01eeSAnsuel Smith return 0; 1680ba3c01eeSAnsuel Smith 1681ba3c01eeSAnsuel Smith /* Reinit the port, reset values set by suspend */ 1682ba3c01eeSAnsuel Smith qca83xx_config_init(phydev); 1683ba3c01eeSAnsuel Smith 1684ba3c01eeSAnsuel Smith /* Reset the port on port resume */ 1685ba3c01eeSAnsuel Smith phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1686ba3c01eeSAnsuel Smith 1687ba3c01eeSAnsuel Smith /* On resume from suspend the switch execute a reset and 1688ba3c01eeSAnsuel Smith * restart auto-negotiation. Wait for reset to complete. 1689ba3c01eeSAnsuel Smith */ 1690ba3c01eeSAnsuel Smith ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1691ba3c01eeSAnsuel Smith 50000, 600000, true); 1692ba3c01eeSAnsuel Smith if (ret) 1693ba3c01eeSAnsuel Smith return ret; 1694ba3c01eeSAnsuel Smith 1695ba3c01eeSAnsuel Smith msleep(1); 1696ba3c01eeSAnsuel Smith 1697ba3c01eeSAnsuel Smith return 0; 1698ba3c01eeSAnsuel Smith } 1699ba3c01eeSAnsuel Smith 1700ba3c01eeSAnsuel Smith static int qca83xx_suspend(struct phy_device *phydev) 1701ba3c01eeSAnsuel Smith { 1702ba3c01eeSAnsuel Smith u16 mask = 0; 1703ba3c01eeSAnsuel Smith 1704ba3c01eeSAnsuel Smith /* Only QCA8337 support actual suspend. 1705ba3c01eeSAnsuel Smith * QCA8327 cause port unreliability when phy suspend 1706ba3c01eeSAnsuel Smith * is set. 1707ba3c01eeSAnsuel Smith */ 1708ba3c01eeSAnsuel Smith if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1709ba3c01eeSAnsuel Smith genphy_suspend(phydev); 1710ba3c01eeSAnsuel Smith } else { 1711ba3c01eeSAnsuel Smith mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1712ba3c01eeSAnsuel Smith phy_modify(phydev, MII_BMCR, mask, 0); 1713ba3c01eeSAnsuel Smith } 1714ba3c01eeSAnsuel Smith 171567999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1716ba3c01eeSAnsuel Smith AT803X_DEBUG_GATE_CLK_IN1000, 0); 1717ba3c01eeSAnsuel Smith 1718ba3c01eeSAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1719ba3c01eeSAnsuel Smith AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1720ba3c01eeSAnsuel Smith AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1721ba3c01eeSAnsuel Smith 1722ba3c01eeSAnsuel Smith return 0; 1723ba3c01eeSAnsuel Smith } 1724ba3c01eeSAnsuel Smith 17252acdd43fSLuo Jie static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 17262acdd43fSLuo Jie { 17272acdd43fSLuo Jie int ret; 17282acdd43fSLuo Jie 17292acdd43fSLuo Jie /* Enable fast retrain */ 17302acdd43fSLuo Jie ret = genphy_c45_fast_retrain(phydev, true); 17312acdd43fSLuo Jie if (ret) 17322acdd43fSLuo Jie return ret; 17332acdd43fSLuo Jie 17342acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 17352acdd43fSLuo Jie QCA808X_TOP_OPTION1_DATA); 17362acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 17372acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_20DB_VALUE); 17382acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 17392acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_17DB_VALUE); 17402acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 17412acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_27DB_VALUE); 17422acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 17432acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_28DB_VALUE); 17442acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 17452acdd43fSLuo Jie QCA808X_MMD3_DEBUG_1_VALUE); 17462acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 17472acdd43fSLuo Jie QCA808X_MMD3_DEBUG_4_VALUE); 17482acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 17492acdd43fSLuo Jie QCA808X_MMD3_DEBUG_5_VALUE); 17502acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 17512acdd43fSLuo Jie QCA808X_MMD3_DEBUG_3_VALUE); 17522acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 17532acdd43fSLuo Jie QCA808X_MMD3_DEBUG_6_VALUE); 17542acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 17552acdd43fSLuo Jie QCA808X_MMD3_DEBUG_2_VALUE); 17562acdd43fSLuo Jie 17572acdd43fSLuo Jie return 0; 17582acdd43fSLuo Jie } 17592acdd43fSLuo Jie 17609d4dae29SLuo Jie static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) 17619d4dae29SLuo Jie { 17628032bf12SJason A. Donenfeld u16 seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE); 17639d4dae29SLuo Jie 17649d4dae29SLuo Jie return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 17659d4dae29SLuo Jie QCA808X_MASTER_SLAVE_SEED_CFG, 17669d4dae29SLuo Jie FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); 17679d4dae29SLuo Jie } 17689d4dae29SLuo Jie 17699d4dae29SLuo Jie static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 17709d4dae29SLuo Jie { 17719d4dae29SLuo Jie u16 seed_enable = 0; 17729d4dae29SLuo Jie 17739d4dae29SLuo Jie if (enable) 17749d4dae29SLuo Jie seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; 17759d4dae29SLuo Jie 17769d4dae29SLuo Jie return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 17779d4dae29SLuo Jie QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); 17789d4dae29SLuo Jie } 17799d4dae29SLuo Jie 17802acdd43fSLuo Jie static int qca808x_config_init(struct phy_device *phydev) 17812acdd43fSLuo Jie { 17822acdd43fSLuo Jie int ret; 17832acdd43fSLuo Jie 17842acdd43fSLuo Jie /* Active adc&vga on 802.3az for the link 1000M and 100M */ 17852acdd43fSLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 17862acdd43fSLuo Jie QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 17872acdd43fSLuo Jie if (ret) 17882acdd43fSLuo Jie return ret; 17892acdd43fSLuo Jie 17902acdd43fSLuo Jie /* Adjust the threshold on 802.3az for the link 1000M */ 17912acdd43fSLuo Jie ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 17922acdd43fSLuo Jie QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 17932acdd43fSLuo Jie if (ret) 17942acdd43fSLuo Jie return ret; 17952acdd43fSLuo Jie 17962acdd43fSLuo Jie /* Config the fast retrain for the link 2500M */ 17972acdd43fSLuo Jie ret = qca808x_phy_fast_retrain_config(phydev); 17982acdd43fSLuo Jie if (ret) 17992acdd43fSLuo Jie return ret; 18002acdd43fSLuo Jie 18019d4dae29SLuo Jie /* Configure lower ramdom seed to make phy linked as slave mode */ 18029d4dae29SLuo Jie ret = qca808x_phy_ms_random_seed_set(phydev); 18039d4dae29SLuo Jie if (ret) 18049d4dae29SLuo Jie return ret; 18059d4dae29SLuo Jie 18069d4dae29SLuo Jie /* Enable seed */ 18079d4dae29SLuo Jie ret = qca808x_phy_ms_seed_enable(phydev, true); 18089d4dae29SLuo Jie if (ret) 18099d4dae29SLuo Jie return ret; 18109d4dae29SLuo Jie 18112acdd43fSLuo Jie /* Configure adc threshold as 100mv for the link 10M */ 18122acdd43fSLuo Jie return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 18132acdd43fSLuo Jie QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 18142acdd43fSLuo Jie } 18152acdd43fSLuo Jie 181679c7bc05SLuo Jie static int qca808x_read_status(struct phy_device *phydev) 181779c7bc05SLuo Jie { 181879c7bc05SLuo Jie int ret; 181979c7bc05SLuo Jie 182079c7bc05SLuo Jie ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 182179c7bc05SLuo Jie if (ret < 0) 182279c7bc05SLuo Jie return ret; 182379c7bc05SLuo Jie 182479c7bc05SLuo Jie linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 182579c7bc05SLuo Jie ret & MDIO_AN_10GBT_STAT_LP2_5G); 182679c7bc05SLuo Jie 182779c7bc05SLuo Jie ret = genphy_read_status(phydev); 182879c7bc05SLuo Jie if (ret) 182979c7bc05SLuo Jie return ret; 183079c7bc05SLuo Jie 183179c7bc05SLuo Jie ret = at803x_read_specific_status(phydev); 183279c7bc05SLuo Jie if (ret < 0) 183379c7bc05SLuo Jie return ret; 183479c7bc05SLuo Jie 1835881cc731SJonathan McDowell if (phydev->link) { 1836881cc731SJonathan McDowell if (phydev->speed == SPEED_2500) 183779c7bc05SLuo Jie phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 183879c7bc05SLuo Jie else 1839881cc731SJonathan McDowell phydev->interface = PHY_INTERFACE_MODE_SGMII; 1840881cc731SJonathan McDowell } else { 18418bc1c543SLuo Jie /* generate seed as a lower random value to make PHY linked as SLAVE easily, 18428bc1c543SLuo Jie * except for master/slave configuration fault detected. 18438bc1c543SLuo Jie * the reason for not putting this code into the function link_change_notify is 18448bc1c543SLuo Jie * the corner case where the link partner is also the qca8081 PHY and the seed 18458bc1c543SLuo Jie * value is configured as the same value, the link can't be up and no link change 18468bc1c543SLuo Jie * occurs. 18478bc1c543SLuo Jie */ 18488bc1c543SLuo Jie if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { 18498bc1c543SLuo Jie qca808x_phy_ms_seed_enable(phydev, false); 18508bc1c543SLuo Jie } else { 18518bc1c543SLuo Jie qca808x_phy_ms_random_seed_set(phydev); 18528bc1c543SLuo Jie qca808x_phy_ms_seed_enable(phydev, true); 18538bc1c543SLuo Jie } 18548bc1c543SLuo Jie } 18558bc1c543SLuo Jie 185679c7bc05SLuo Jie return 0; 185779c7bc05SLuo Jie } 185879c7bc05SLuo Jie 18599d4dae29SLuo Jie static int qca808x_soft_reset(struct phy_device *phydev) 18609d4dae29SLuo Jie { 18619d4dae29SLuo Jie int ret; 18629d4dae29SLuo Jie 18639d4dae29SLuo Jie ret = genphy_soft_reset(phydev); 18649d4dae29SLuo Jie if (ret < 0) 18659d4dae29SLuo Jie return ret; 18669d4dae29SLuo Jie 18679d4dae29SLuo Jie return qca808x_phy_ms_seed_enable(phydev, true); 18689d4dae29SLuo Jie } 18699d4dae29SLuo Jie 18708c84d752SLuo Jie static bool qca808x_cdt_fault_length_valid(int cdt_code) 18718c84d752SLuo Jie { 18728c84d752SLuo Jie switch (cdt_code) { 18738c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_SHORT: 18748c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_OPEN: 18758c84d752SLuo Jie return true; 18768c84d752SLuo Jie default: 18778c84d752SLuo Jie return false; 18788c84d752SLuo Jie } 18798c84d752SLuo Jie } 18808c84d752SLuo Jie 18818c84d752SLuo Jie static int qca808x_cable_test_result_trans(int cdt_code) 18828c84d752SLuo Jie { 18838c84d752SLuo Jie switch (cdt_code) { 18848c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_NORMAL: 18858c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_OK; 18868c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_SHORT: 18878c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 18888c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_OPEN: 18898c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 18908c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_FAIL: 18918c84d752SLuo Jie default: 18928c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 18938c84d752SLuo Jie } 18948c84d752SLuo Jie } 18958c84d752SLuo Jie 18968c84d752SLuo Jie static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 18978c84d752SLuo Jie { 18988c84d752SLuo Jie int val; 18998c84d752SLuo Jie u32 cdt_length_reg = 0; 19008c84d752SLuo Jie 19018c84d752SLuo Jie switch (pair) { 19028c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_A: 19038c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 19048c84d752SLuo Jie break; 19058c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_B: 19068c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 19078c84d752SLuo Jie break; 19088c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_C: 19098c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 19108c84d752SLuo Jie break; 19118c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_D: 19128c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 19138c84d752SLuo Jie break; 19148c84d752SLuo Jie default: 19158c84d752SLuo Jie return -EINVAL; 19168c84d752SLuo Jie } 19178c84d752SLuo Jie 19188c84d752SLuo Jie val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 19198c84d752SLuo Jie if (val < 0) 19208c84d752SLuo Jie return val; 19218c84d752SLuo Jie 19228c84d752SLuo Jie return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 19238c84d752SLuo Jie } 19248c84d752SLuo Jie 19258c84d752SLuo Jie static int qca808x_cable_test_start(struct phy_device *phydev) 19268c84d752SLuo Jie { 19278c84d752SLuo Jie int ret; 19288c84d752SLuo Jie 19298c84d752SLuo Jie /* perform CDT with the following configs: 19308c84d752SLuo Jie * 1. disable hibernation. 19318c84d752SLuo Jie * 2. force PHY working in MDI mode. 19328c84d752SLuo Jie * 3. for PHY working in 1000BaseT. 19338c84d752SLuo Jie * 4. configure the threshold. 19348c84d752SLuo Jie */ 19358c84d752SLuo Jie 19368c84d752SLuo Jie ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 19378c84d752SLuo Jie if (ret < 0) 19388c84d752SLuo Jie return ret; 19398c84d752SLuo Jie 19408c84d752SLuo Jie ret = at803x_config_mdix(phydev, ETH_TP_MDI); 19418c84d752SLuo Jie if (ret < 0) 19428c84d752SLuo Jie return ret; 19438c84d752SLuo Jie 19448c84d752SLuo Jie /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 19458c84d752SLuo Jie phydev->duplex = DUPLEX_FULL; 19468c84d752SLuo Jie phydev->speed = SPEED_1000; 19478c84d752SLuo Jie ret = genphy_c45_pma_setup_forced(phydev); 19488c84d752SLuo Jie if (ret < 0) 19498c84d752SLuo Jie return ret; 19508c84d752SLuo Jie 19518c84d752SLuo Jie ret = genphy_setup_forced(phydev); 19528c84d752SLuo Jie if (ret < 0) 19538c84d752SLuo Jie return ret; 19548c84d752SLuo Jie 19558c84d752SLuo Jie /* configure the thresholds for open, short, pair ok test */ 19568c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 19578c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 19588c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 19598c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 19608c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 19618c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 19628c84d752SLuo Jie 19638c84d752SLuo Jie return 0; 19648c84d752SLuo Jie } 19658c84d752SLuo Jie 19668c84d752SLuo Jie static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 19678c84d752SLuo Jie { 19688c84d752SLuo Jie int ret, val; 19698c84d752SLuo Jie int pair_a, pair_b, pair_c, pair_d; 19708c84d752SLuo Jie 19718c84d752SLuo Jie *finished = false; 19728c84d752SLuo Jie 19738c84d752SLuo Jie ret = at803x_cdt_start(phydev, 0); 19748c84d752SLuo Jie if (ret) 19758c84d752SLuo Jie return ret; 19768c84d752SLuo Jie 19778c84d752SLuo Jie ret = at803x_cdt_wait_for_completion(phydev); 19788c84d752SLuo Jie if (ret) 19798c84d752SLuo Jie return ret; 19808c84d752SLuo Jie 19818c84d752SLuo Jie val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 19828c84d752SLuo Jie if (val < 0) 19838c84d752SLuo Jie return val; 19848c84d752SLuo Jie 19858c84d752SLuo Jie pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 19868c84d752SLuo Jie pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 19878c84d752SLuo Jie pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 19888c84d752SLuo Jie pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 19898c84d752SLuo Jie 19908c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 19918c84d752SLuo Jie qca808x_cable_test_result_trans(pair_a)); 19928c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 19938c84d752SLuo Jie qca808x_cable_test_result_trans(pair_b)); 19948c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 19958c84d752SLuo Jie qca808x_cable_test_result_trans(pair_c)); 19968c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 19978c84d752SLuo Jie qca808x_cable_test_result_trans(pair_d)); 19988c84d752SLuo Jie 19998c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_a)) 20008c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 20018c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 20028c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_b)) 20038c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 20048c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 20058c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_c)) 20068c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 20078c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 20088c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_d)) 20098c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 20108c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 20118c84d752SLuo Jie 20128c84d752SLuo Jie *finished = true; 20138c84d752SLuo Jie 20148c84d752SLuo Jie return 0; 20158c84d752SLuo Jie } 20168c84d752SLuo Jie 2017317420abSMugunthan V N static struct phy_driver at803x_driver[] = { 2018317420abSMugunthan V N { 201996c36712SMichael Walle /* Qualcomm Atheros AR8035 */ 20200465d8f8SMichael Walle PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 202196c36712SMichael Walle .name = "Qualcomm Atheros AR8035", 20226cb75767SMichael Walle .flags = PHY_POLL_CABLE_TEST, 20232f664823SMichael Walle .probe = at803x_probe, 20242318ca8aSMichael Walle .remove = at803x_remove, 20257dce80c2SOleksij Rempel .config_aneg = at803x_config_aneg, 20260ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 2027cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 2028ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 2029ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 20306229ed1fSDaniel Mack .suspend = at803x_suspend, 20316229ed1fSDaniel Mack .resume = at803x_resume, 2032dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 203306d5f344SRussell King .read_status = at803x_read_status, 20340eae5982SMåns Rullgård .config_intr = at803x_config_intr, 203529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 2036cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 2037cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 20386cb75767SMichael Walle .cable_test_start = at803x_cable_test_start, 20396cb75767SMichael Walle .cable_test_get_status = at803x_cable_test_get_status, 2040317420abSMugunthan V N }, { 204196c36712SMichael Walle /* Qualcomm Atheros AR8030 */ 2042bd8ca17fSDaniel Mack .phy_id = ATH8030_PHY_ID, 204396c36712SMichael Walle .name = "Qualcomm Atheros AR8030", 20440465d8f8SMichael Walle .phy_id_mask = AT8030_PHY_ID_MASK, 20452f664823SMichael Walle .probe = at803x_probe, 20462318ca8aSMichael Walle .remove = at803x_remove, 20470ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 204813a56b44SDaniel Mack .link_change_notify = at803x_link_change_notify, 2049ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 2050ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 20516229ed1fSDaniel Mack .suspend = at803x_suspend, 20526229ed1fSDaniel Mack .resume = at803x_resume, 2053dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 20540eae5982SMåns Rullgård .config_intr = at803x_config_intr, 205529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 205605d7cce8SMugunthan V N }, { 205796c36712SMichael Walle /* Qualcomm Atheros AR8031/AR8033 */ 20580465d8f8SMichael Walle PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 205996c36712SMichael Walle .name = "Qualcomm Atheros AR8031/AR8033", 20606cb75767SMichael Walle .flags = PHY_POLL_CABLE_TEST, 20612f664823SMichael Walle .probe = at803x_probe, 20622318ca8aSMichael Walle .remove = at803x_remove, 206305d7cce8SMugunthan V N .config_init = at803x_config_init, 206463477a5dSMichael Walle .config_aneg = at803x_config_aneg, 2065cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 206605d7cce8SMugunthan V N .set_wol = at803x_set_wol, 206705d7cce8SMugunthan V N .get_wol = at803x_get_wol, 20686229ed1fSDaniel Mack .suspend = at803x_suspend, 20696229ed1fSDaniel Mack .resume = at803x_resume, 2070c329e5afSDavid Bauer .read_page = at803x_read_page, 2071c329e5afSDavid Bauer .write_page = at803x_write_page, 2072b856150cSDavid Bauer .get_features = at803x_get_features, 207306d5f344SRussell King .read_status = at803x_read_status, 207477a99394SZhao Qiang .config_intr = &at803x_config_intr, 207529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 2076cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 2077cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 20786cb75767SMichael Walle .cable_test_start = at803x_cable_test_start, 20796cb75767SMichael Walle .cable_test_get_status = at803x_cable_test_get_status, 20807908d2ceSOleksij Rempel }, { 20815800091aSDavid Bauer /* Qualcomm Atheros AR8032 */ 20825800091aSDavid Bauer PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 20835800091aSDavid Bauer .name = "Qualcomm Atheros AR8032", 20845800091aSDavid Bauer .probe = at803x_probe, 20855800091aSDavid Bauer .remove = at803x_remove, 2086dc0f3ed1SOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 20875800091aSDavid Bauer .config_init = at803x_config_init, 20885800091aSDavid Bauer .link_change_notify = at803x_link_change_notify, 20895800091aSDavid Bauer .set_wol = at803x_set_wol, 20905800091aSDavid Bauer .get_wol = at803x_get_wol, 20915800091aSDavid Bauer .suspend = at803x_suspend, 20925800091aSDavid Bauer .resume = at803x_resume, 20935800091aSDavid Bauer /* PHY_BASIC_FEATURES */ 20945800091aSDavid Bauer .config_intr = at803x_config_intr, 209529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 2096dc0f3ed1SOleksij Rempel .cable_test_start = at803x_cable_test_start, 2097dc0f3ed1SOleksij Rempel .cable_test_get_status = at803x_cable_test_get_status, 20985800091aSDavid Bauer }, { 20997908d2ceSOleksij Rempel /* ATHEROS AR9331 */ 21007908d2ceSOleksij Rempel PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 210196c36712SMichael Walle .name = "Qualcomm Atheros AR9331 built-in PHY", 21029926de73SOleksij Rempel .probe = at803x_probe, 21039926de73SOleksij Rempel .remove = at803x_remove, 21047908d2ceSOleksij Rempel .suspend = at803x_suspend, 21057908d2ceSOleksij Rempel .resume = at803x_resume, 2106dc0f3ed1SOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 21077908d2ceSOleksij Rempel /* PHY_BASIC_FEATURES */ 21087908d2ceSOleksij Rempel .config_intr = &at803x_config_intr, 210929773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 2110dc0f3ed1SOleksij Rempel .cable_test_start = at803x_cable_test_start, 2111dc0f3ed1SOleksij Rempel .cable_test_get_status = at803x_cable_test_get_status, 21127dce80c2SOleksij Rempel .read_status = at803x_read_status, 21137dce80c2SOleksij Rempel .soft_reset = genphy_soft_reset, 21147dce80c2SOleksij Rempel .config_aneg = at803x_config_aneg, 2115272833b9SAnsuel Smith }, { 2116fada2ce0SDavid Bauer /* Qualcomm Atheros QCA9561 */ 2117fada2ce0SDavid Bauer PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 2118fada2ce0SDavid Bauer .name = "Qualcomm Atheros QCA9561 built-in PHY", 21199926de73SOleksij Rempel .probe = at803x_probe, 21209926de73SOleksij Rempel .remove = at803x_remove, 2121fada2ce0SDavid Bauer .suspend = at803x_suspend, 2122fada2ce0SDavid Bauer .resume = at803x_resume, 2123fada2ce0SDavid Bauer .flags = PHY_POLL_CABLE_TEST, 2124fada2ce0SDavid Bauer /* PHY_BASIC_FEATURES */ 2125fada2ce0SDavid Bauer .config_intr = &at803x_config_intr, 2126fada2ce0SDavid Bauer .handle_interrupt = at803x_handle_interrupt, 2127fada2ce0SDavid Bauer .cable_test_start = at803x_cable_test_start, 2128fada2ce0SDavid Bauer .cable_test_get_status = at803x_cable_test_get_status, 2129fada2ce0SDavid Bauer .read_status = at803x_read_status, 2130fada2ce0SDavid Bauer .soft_reset = genphy_soft_reset, 2131fada2ce0SDavid Bauer .config_aneg = at803x_config_aneg, 2132fada2ce0SDavid Bauer }, { 2133272833b9SAnsuel Smith /* QCA8337 */ 2134272833b9SAnsuel Smith .phy_id = QCA8337_PHY_ID, 2135272833b9SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 2136d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8337 internal PHY", 2137272833b9SAnsuel Smith /* PHY_GBIT_FEATURES */ 21381ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 2139272833b9SAnsuel Smith .probe = at803x_probe, 2140272833b9SAnsuel Smith .flags = PHY_IS_INTERNAL, 2141272833b9SAnsuel Smith .config_init = qca83xx_config_init, 2142272833b9SAnsuel Smith .soft_reset = genphy_soft_reset, 2143272833b9SAnsuel Smith .get_sset_count = at803x_get_sset_count, 2144272833b9SAnsuel Smith .get_strings = at803x_get_strings, 2145272833b9SAnsuel Smith .get_stats = at803x_get_stats, 2146ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 2147ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 21480ccf8511SAnsuel Smith }, { 2149b4df02b5SAnsuel Smith /* QCA8327-A from switch QCA8327-AL1A */ 2150b4df02b5SAnsuel Smith .phy_id = QCA8327_A_PHY_ID, 21510ccf8511SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 2152d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8327-A internal PHY", 2153b4df02b5SAnsuel Smith /* PHY_GBIT_FEATURES */ 21541ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 2155b4df02b5SAnsuel Smith .probe = at803x_probe, 2156b4df02b5SAnsuel Smith .flags = PHY_IS_INTERNAL, 2157b4df02b5SAnsuel Smith .config_init = qca83xx_config_init, 2158b4df02b5SAnsuel Smith .soft_reset = genphy_soft_reset, 2159b4df02b5SAnsuel Smith .get_sset_count = at803x_get_sset_count, 2160b4df02b5SAnsuel Smith .get_strings = at803x_get_strings, 2161b4df02b5SAnsuel Smith .get_stats = at803x_get_stats, 2162ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 2163ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 2164b4df02b5SAnsuel Smith }, { 2165b4df02b5SAnsuel Smith /* QCA8327-B from switch QCA8327-BL1A */ 2166b4df02b5SAnsuel Smith .phy_id = QCA8327_B_PHY_ID, 2167b4df02b5SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 2168d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8327-B internal PHY", 21690ccf8511SAnsuel Smith /* PHY_GBIT_FEATURES */ 21701ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 21710ccf8511SAnsuel Smith .probe = at803x_probe, 21720ccf8511SAnsuel Smith .flags = PHY_IS_INTERNAL, 21730ccf8511SAnsuel Smith .config_init = qca83xx_config_init, 21740ccf8511SAnsuel Smith .soft_reset = genphy_soft_reset, 21750ccf8511SAnsuel Smith .get_sset_count = at803x_get_sset_count, 21760ccf8511SAnsuel Smith .get_strings = at803x_get_strings, 21770ccf8511SAnsuel Smith .get_stats = at803x_get_stats, 2178ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 2179ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 2180daf61732SLuo Jie }, { 2181daf61732SLuo Jie /* Qualcomm QCA8081 */ 2182daf61732SLuo Jie PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2183daf61732SLuo Jie .name = "Qualcomm QCA8081", 21848c84d752SLuo Jie .flags = PHY_POLL_CABLE_TEST, 21859926de73SOleksij Rempel .probe = at803x_probe, 21869926de73SOleksij Rempel .remove = at803x_remove, 2187daf61732SLuo Jie .config_intr = at803x_config_intr, 2188daf61732SLuo Jie .handle_interrupt = at803x_handle_interrupt, 2189daf61732SLuo Jie .get_tunable = at803x_get_tunable, 2190daf61732SLuo Jie .set_tunable = at803x_set_tunable, 2191daf61732SLuo Jie .set_wol = at803x_set_wol, 2192daf61732SLuo Jie .get_wol = at803x_get_wol, 2193765c22aaSLuo Jie .get_features = at803x_get_features, 2194f884d449SLuo Jie .config_aneg = at803x_config_aneg, 2195daf61732SLuo Jie .suspend = genphy_suspend, 2196daf61732SLuo Jie .resume = genphy_resume, 219779c7bc05SLuo Jie .read_status = qca808x_read_status, 21982acdd43fSLuo Jie .config_init = qca808x_config_init, 21999d4dae29SLuo Jie .soft_reset = qca808x_soft_reset, 22008c84d752SLuo Jie .cable_test_start = qca808x_cable_test_start, 22018c84d752SLuo Jie .cable_test_get_status = qca808x_cable_test_get_status, 2202272833b9SAnsuel Smith }, }; 22030ca7111aSMatus Ujhelyi 220450fd7150SJohan Hovold module_phy_driver(at803x_driver); 22050ca7111aSMatus Ujhelyi 22060ca7111aSMatus Ujhelyi static struct mdio_device_id __maybe_unused atheros_tbl[] = { 22070465d8f8SMichael Walle { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 22080465d8f8SMichael Walle { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 22095800091aSDavid Bauer { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 22100465d8f8SMichael Walle { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 22117908d2ceSOleksij Rempel { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 22120ccf8511SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2213b4df02b5SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2214b4df02b5SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2215fada2ce0SDavid Bauer { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2216daf61732SLuo Jie { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 22170ca7111aSMatus Ujhelyi { } 22180ca7111aSMatus Ujhelyi }; 22190ca7111aSMatus Ujhelyi 22200ca7111aSMatus Ujhelyi MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2221