1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 20ca7111aSMatus Ujhelyi /* 30ca7111aSMatus Ujhelyi * drivers/net/phy/at803x.c 40ca7111aSMatus Ujhelyi * 596c36712SMichael Walle * Driver for Qualcomm Atheros AR803x PHY 60ca7111aSMatus Ujhelyi * 70ca7111aSMatus Ujhelyi * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 80ca7111aSMatus Ujhelyi */ 90ca7111aSMatus Ujhelyi 100ca7111aSMatus Ujhelyi #include <linux/phy.h> 110ca7111aSMatus Ujhelyi #include <linux/module.h> 120ca7111aSMatus Ujhelyi #include <linux/string.h> 130ca7111aSMatus Ujhelyi #include <linux/netdevice.h> 140ca7111aSMatus Ujhelyi #include <linux/etherdevice.h> 156cb75767SMichael Walle #include <linux/ethtool_netlink.h> 1613a56b44SDaniel Mack #include <linux/of_gpio.h> 172f664823SMichael Walle #include <linux/bitfield.h> 1813a56b44SDaniel Mack #include <linux/gpio/consumer.h> 192f664823SMichael Walle #include <linux/regulator/of_regulator.h> 202f664823SMichael Walle #include <linux/regulator/driver.h> 212f664823SMichael Walle #include <linux/regulator/consumer.h> 222f664823SMichael Walle #include <dt-bindings/net/qca-ar803x.h> 230ca7111aSMatus Ujhelyi 247dce80c2SOleksij Rempel #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 257dce80c2SOleksij Rempel #define AT803X_SFC_ASSERT_CRS BIT(11) 267dce80c2SOleksij Rempel #define AT803X_SFC_FORCE_LINK BIT(10) 277dce80c2SOleksij Rempel #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 287dce80c2SOleksij Rempel #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 297dce80c2SOleksij Rempel #define AT803X_SFC_MANUAL_MDIX 0x1 307dce80c2SOleksij Rempel #define AT803X_SFC_MANUAL_MDI 0x0 317dce80c2SOleksij Rempel #define AT803X_SFC_SQE_TEST BIT(2) 327dce80c2SOleksij Rempel #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 337dce80c2SOleksij Rempel #define AT803X_SFC_DISABLE_JABBER BIT(0) 347dce80c2SOleksij Rempel 3506d5f344SRussell King #define AT803X_SPECIFIC_STATUS 0x11 369540cddaSLuo Jie #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 379540cddaSLuo Jie #define AT803X_SS_SPEED_1000 2 389540cddaSLuo Jie #define AT803X_SS_SPEED_100 1 399540cddaSLuo Jie #define AT803X_SS_SPEED_10 0 4006d5f344SRussell King #define AT803X_SS_DUPLEX BIT(13) 4106d5f344SRussell King #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 4206d5f344SRussell King #define AT803X_SS_MDIX BIT(6) 4306d5f344SRussell King 44*79c7bc05SLuo Jie #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 45*79c7bc05SLuo Jie #define QCA808X_SS_SPEED_2500 4 46*79c7bc05SLuo Jie 470ca7111aSMatus Ujhelyi #define AT803X_INTR_ENABLE 0x12 48e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 49e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 50e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 51e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 52e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 53e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 54e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 55e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 56e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WOL BIT(0) 57e6e4a556SMartin Blumenstingl 580ca7111aSMatus Ujhelyi #define AT803X_INTR_STATUS 0x13 59a46bd63bSMartin Blumenstingl 6013a56b44SDaniel Mack #define AT803X_SMART_SPEED 0x14 61cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_ENABLE BIT(5) 62cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 63cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 646cb75767SMichael Walle #define AT803X_CDT 0x16 656cb75767SMichael Walle #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 666cb75767SMichael Walle #define AT803X_CDT_ENABLE_TEST BIT(0) 676cb75767SMichael Walle #define AT803X_CDT_STATUS 0x1c 686cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_NORMAL 0 696cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_SHORT 1 706cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_OPEN 2 716cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_FAIL 3 726cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 736cb75767SMichael Walle #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 7413a56b44SDaniel Mack #define AT803X_LED_CONTROL 0x18 75a46bd63bSMartin Blumenstingl 767beecaf7SLuo Jie #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 777beecaf7SLuo Jie #define AT803X_WOL_EN BIT(5) 780ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 790ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 800ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 81f62265b5SZefir Kurtisi #define AT803X_REG_CHIP_CONFIG 0x1f 82f62265b5SZefir Kurtisi #define AT803X_BT_BX_REG_SEL 0x8000 83a46bd63bSMartin Blumenstingl 841ca6d1b1SMugunthan V N #define AT803X_DEBUG_ADDR 0x1D 851ca6d1b1SMugunthan V N #define AT803X_DEBUG_DATA 0x1E 86a46bd63bSMartin Blumenstingl 87f62265b5SZefir Kurtisi #define AT803X_MODE_CFG_MASK 0x0F 88f62265b5SZefir Kurtisi #define AT803X_MODE_CFG_SGMII 0x01 89f62265b5SZefir Kurtisi 90f62265b5SZefir Kurtisi #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 91f62265b5SZefir Kurtisi #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 92f62265b5SZefir Kurtisi 9367999555SAnsuel Smith #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 941ca83119SAnsuel Smith #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 951ca83119SAnsuel Smith #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 962e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 97a46bd63bSMartin Blumenstingl 9867999555SAnsuel Smith #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 992e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 1000ca7111aSMatus Ujhelyi 101ba3c01eeSAnsuel Smith #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 102ba3c01eeSAnsuel Smith #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 103ba3c01eeSAnsuel Smith #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 104ba3c01eeSAnsuel Smith 105272833b9SAnsuel Smith #define AT803X_DEBUG_REG_3C 0x3C 106272833b9SAnsuel Smith 10767999555SAnsuel Smith #define AT803X_DEBUG_REG_GREEN 0x3D 108ba3c01eeSAnsuel Smith #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 109272833b9SAnsuel Smith 1102f664823SMichael Walle #define AT803X_DEBUG_REG_1F 0x1F 1112f664823SMichael Walle #define AT803X_DEBUG_PLL_ON BIT(2) 1122f664823SMichael Walle #define AT803X_DEBUG_RGMII_1V8 BIT(3) 1132f664823SMichael Walle 114272833b9SAnsuel Smith #define MDIO_AZ_DEBUG 0x800D 115272833b9SAnsuel Smith 1162f664823SMichael Walle /* AT803x supports either the XTAL input pad, an internal PLL or the 1172f664823SMichael Walle * DSP as clock reference for the clock output pad. The XTAL reference 1182f664823SMichael Walle * is only used for 25 MHz output, all other frequencies need the PLL. 1192f664823SMichael Walle * The DSP as a clock reference is used in synchronous ethernet 1202f664823SMichael Walle * applications. 1212f664823SMichael Walle * 1222f664823SMichael Walle * By default the PLL is only enabled if there is a link. Otherwise 1232f664823SMichael Walle * the PHY will go into low power state and disabled the PLL. You can 1242f664823SMichael Walle * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 1252f664823SMichael Walle * enabled. 1262f664823SMichael Walle */ 1272f664823SMichael Walle #define AT803X_MMD7_CLK25M 0x8016 1282f664823SMichael Walle #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 1292f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_XTAL 0 1302f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_DSP 1 1312f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_PLL 2 1322f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_DSP 3 1332f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_PLL 4 1342f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_DSP 5 1352f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_PLL 6 1362f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_DSP 7 1372f664823SMichael Walle 138428061f7SMichael Walle /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 139428061f7SMichael Walle * but doesn't support choosing between XTAL/PLL and DSP. 1402f664823SMichael Walle */ 1412f664823SMichael Walle #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 1422f664823SMichael Walle 1432f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 1442f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_FULL 0 1452f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_HALF 1 1462f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 1472f664823SMichael Walle 148cde0f4f8SMichael Walle #define AT803X_DEFAULT_DOWNSHIFT 5 149cde0f4f8SMichael Walle #define AT803X_MIN_DOWNSHIFT 2 150cde0f4f8SMichael Walle #define AT803X_MAX_DOWNSHIFT 9 151cde0f4f8SMichael Walle 152390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 153390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 154390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 155390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 156390b4cadSRussell King 1577908d2ceSOleksij Rempel #define ATH9331_PHY_ID 0x004dd041 158bd8ca17fSDaniel Mack #define ATH8030_PHY_ID 0x004dd076 159bd8ca17fSDaniel Mack #define ATH8031_PHY_ID 0x004dd074 1605800091aSDavid Bauer #define ATH8032_PHY_ID 0x004dd023 161bd8ca17fSDaniel Mack #define ATH8035_PHY_ID 0x004dd072 1620465d8f8SMichael Walle #define AT8030_PHY_ID_MASK 0xffffffef 163bd8ca17fSDaniel Mack 164daf61732SLuo Jie #define QCA8081_PHY_ID 0x004dd101 165daf61732SLuo Jie 166b4df02b5SAnsuel Smith #define QCA8327_A_PHY_ID 0x004dd033 167b4df02b5SAnsuel Smith #define QCA8327_B_PHY_ID 0x004dd034 168272833b9SAnsuel Smith #define QCA8337_PHY_ID 0x004dd036 169fada2ce0SDavid Bauer #define QCA9561_PHY_ID 0x004dd042 170272833b9SAnsuel Smith #define QCA8K_PHY_ID_MASK 0xffffffff 171272833b9SAnsuel Smith 172272833b9SAnsuel Smith #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 173272833b9SAnsuel Smith 174c329e5afSDavid Bauer #define AT803X_PAGE_FIBER 0 175c329e5afSDavid Bauer #define AT803X_PAGE_COPPER 1 176c329e5afSDavid Bauer 177d0e13fd5SAnsuel Smith /* don't turn off internal PLL */ 178d0e13fd5SAnsuel Smith #define AT803X_KEEP_PLL_ENABLED BIT(0) 179d0e13fd5SAnsuel Smith #define AT803X_DISABLE_SMARTEEE BIT(1) 180d0e13fd5SAnsuel Smith 181daf61732SLuo Jie MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 1820ca7111aSMatus Ujhelyi MODULE_AUTHOR("Matus Ujhelyi"); 1830ca7111aSMatus Ujhelyi MODULE_LICENSE("GPL"); 1840ca7111aSMatus Ujhelyi 185272833b9SAnsuel Smith enum stat_access_type { 186272833b9SAnsuel Smith PHY, 187272833b9SAnsuel Smith MMD 188272833b9SAnsuel Smith }; 189272833b9SAnsuel Smith 190272833b9SAnsuel Smith struct at803x_hw_stat { 191272833b9SAnsuel Smith const char *string; 192272833b9SAnsuel Smith u8 reg; 193272833b9SAnsuel Smith u32 mask; 194272833b9SAnsuel Smith enum stat_access_type access_type; 195272833b9SAnsuel Smith }; 196272833b9SAnsuel Smith 197272833b9SAnsuel Smith static struct at803x_hw_stat at803x_hw_stats[] = { 198272833b9SAnsuel Smith { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 199272833b9SAnsuel Smith { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 200272833b9SAnsuel Smith { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 201272833b9SAnsuel Smith }; 202272833b9SAnsuel Smith 2032f664823SMichael Walle struct at803x_priv { 2042f664823SMichael Walle int flags; 2052f664823SMichael Walle u16 clk_25m_reg; 2062f664823SMichael Walle u16 clk_25m_mask; 207390b4cadSRussell King u8 smarteee_lpi_tw_1g; 208390b4cadSRussell King u8 smarteee_lpi_tw_100m; 2092f664823SMichael Walle struct regulator_dev *vddio_rdev; 2102f664823SMichael Walle struct regulator_dev *vddh_rdev; 2112f664823SMichael Walle struct regulator *vddio; 212272833b9SAnsuel Smith u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 2132f664823SMichael Walle }; 2142f664823SMichael Walle 21513a56b44SDaniel Mack struct at803x_context { 21613a56b44SDaniel Mack u16 bmcr; 21713a56b44SDaniel Mack u16 advertise; 21813a56b44SDaniel Mack u16 control1000; 21913a56b44SDaniel Mack u16 int_enable; 22013a56b44SDaniel Mack u16 smart_speed; 22113a56b44SDaniel Mack u16 led_control; 22213a56b44SDaniel Mack }; 22313a56b44SDaniel Mack 224272833b9SAnsuel Smith static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 225272833b9SAnsuel Smith { 226272833b9SAnsuel Smith int ret; 227272833b9SAnsuel Smith 228272833b9SAnsuel Smith ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 229272833b9SAnsuel Smith if (ret < 0) 230272833b9SAnsuel Smith return ret; 231272833b9SAnsuel Smith 232272833b9SAnsuel Smith return phy_write(phydev, AT803X_DEBUG_DATA, data); 233272833b9SAnsuel Smith } 234272833b9SAnsuel Smith 2352e5f9f28SMartin Blumenstingl static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 2362e5f9f28SMartin Blumenstingl { 2372e5f9f28SMartin Blumenstingl int ret; 2382e5f9f28SMartin Blumenstingl 2392e5f9f28SMartin Blumenstingl ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 2402e5f9f28SMartin Blumenstingl if (ret < 0) 2412e5f9f28SMartin Blumenstingl return ret; 2422e5f9f28SMartin Blumenstingl 2432e5f9f28SMartin Blumenstingl return phy_read(phydev, AT803X_DEBUG_DATA); 2442e5f9f28SMartin Blumenstingl } 2452e5f9f28SMartin Blumenstingl 2462e5f9f28SMartin Blumenstingl static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 2472e5f9f28SMartin Blumenstingl u16 clear, u16 set) 2482e5f9f28SMartin Blumenstingl { 2492e5f9f28SMartin Blumenstingl u16 val; 2502e5f9f28SMartin Blumenstingl int ret; 2512e5f9f28SMartin Blumenstingl 2522e5f9f28SMartin Blumenstingl ret = at803x_debug_reg_read(phydev, reg); 2532e5f9f28SMartin Blumenstingl if (ret < 0) 2542e5f9f28SMartin Blumenstingl return ret; 2552e5f9f28SMartin Blumenstingl 2562e5f9f28SMartin Blumenstingl val = ret & 0xffff; 2572e5f9f28SMartin Blumenstingl val &= ~clear; 2582e5f9f28SMartin Blumenstingl val |= set; 2592e5f9f28SMartin Blumenstingl 2602e5f9f28SMartin Blumenstingl return phy_write(phydev, AT803X_DEBUG_DATA, val); 2612e5f9f28SMartin Blumenstingl } 2622e5f9f28SMartin Blumenstingl 263c329e5afSDavid Bauer static int at803x_write_page(struct phy_device *phydev, int page) 264c329e5afSDavid Bauer { 265c329e5afSDavid Bauer int mask; 266c329e5afSDavid Bauer int set; 267c329e5afSDavid Bauer 268c329e5afSDavid Bauer if (page == AT803X_PAGE_COPPER) { 269c329e5afSDavid Bauer set = AT803X_BT_BX_REG_SEL; 270c329e5afSDavid Bauer mask = 0; 271c329e5afSDavid Bauer } else { 272c329e5afSDavid Bauer set = 0; 273c329e5afSDavid Bauer mask = AT803X_BT_BX_REG_SEL; 274c329e5afSDavid Bauer } 275c329e5afSDavid Bauer 276c329e5afSDavid Bauer return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 277c329e5afSDavid Bauer } 278c329e5afSDavid Bauer 279c329e5afSDavid Bauer static int at803x_read_page(struct phy_device *phydev) 280c329e5afSDavid Bauer { 281c329e5afSDavid Bauer int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 282c329e5afSDavid Bauer 283c329e5afSDavid Bauer if (ccr < 0) 284c329e5afSDavid Bauer return ccr; 285c329e5afSDavid Bauer 286c329e5afSDavid Bauer if (ccr & AT803X_BT_BX_REG_SEL) 287c329e5afSDavid Bauer return AT803X_PAGE_COPPER; 288c329e5afSDavid Bauer 289c329e5afSDavid Bauer return AT803X_PAGE_FIBER; 290c329e5afSDavid Bauer } 291c329e5afSDavid Bauer 2926d4cd041SVinod Koul static int at803x_enable_rx_delay(struct phy_device *phydev) 2936d4cd041SVinod Koul { 29467999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 2956d4cd041SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN); 2966d4cd041SVinod Koul } 2976d4cd041SVinod Koul 2986d4cd041SVinod Koul static int at803x_enable_tx_delay(struct phy_device *phydev) 2996d4cd041SVinod Koul { 30067999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 3016d4cd041SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN); 3026d4cd041SVinod Koul } 3036d4cd041SVinod Koul 30443f2ebd5SVinod Koul static int at803x_disable_rx_delay(struct phy_device *phydev) 3052e5f9f28SMartin Blumenstingl { 30667999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 307cd28d1d6SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN, 0); 3082e5f9f28SMartin Blumenstingl } 3092e5f9f28SMartin Blumenstingl 31043f2ebd5SVinod Koul static int at803x_disable_tx_delay(struct phy_device *phydev) 3112e5f9f28SMartin Blumenstingl { 31267999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 313cd28d1d6SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN, 0); 3142e5f9f28SMartin Blumenstingl } 3152e5f9f28SMartin Blumenstingl 31613a56b44SDaniel Mack /* save relevant PHY registers to private copy */ 31713a56b44SDaniel Mack static void at803x_context_save(struct phy_device *phydev, 31813a56b44SDaniel Mack struct at803x_context *context) 31913a56b44SDaniel Mack { 32013a56b44SDaniel Mack context->bmcr = phy_read(phydev, MII_BMCR); 32113a56b44SDaniel Mack context->advertise = phy_read(phydev, MII_ADVERTISE); 32213a56b44SDaniel Mack context->control1000 = phy_read(phydev, MII_CTRL1000); 32313a56b44SDaniel Mack context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 32413a56b44SDaniel Mack context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 32513a56b44SDaniel Mack context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 32613a56b44SDaniel Mack } 32713a56b44SDaniel Mack 32813a56b44SDaniel Mack /* restore relevant PHY registers from private copy */ 32913a56b44SDaniel Mack static void at803x_context_restore(struct phy_device *phydev, 33013a56b44SDaniel Mack const struct at803x_context *context) 33113a56b44SDaniel Mack { 33213a56b44SDaniel Mack phy_write(phydev, MII_BMCR, context->bmcr); 33313a56b44SDaniel Mack phy_write(phydev, MII_ADVERTISE, context->advertise); 33413a56b44SDaniel Mack phy_write(phydev, MII_CTRL1000, context->control1000); 33513a56b44SDaniel Mack phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 33613a56b44SDaniel Mack phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 33713a56b44SDaniel Mack phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 33813a56b44SDaniel Mack } 33913a56b44SDaniel Mack 340ea13c9eeSMugunthan V N static int at803x_set_wol(struct phy_device *phydev, 341ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 3420ca7111aSMatus Ujhelyi { 3430ca7111aSMatus Ujhelyi struct net_device *ndev = phydev->attached_dev; 3440ca7111aSMatus Ujhelyi const u8 *mac; 3457beecaf7SLuo Jie int ret, irq_enabled; 346c0f0b563SLuo Jie unsigned int i; 347c0f0b563SLuo Jie const unsigned int offsets[] = { 3480ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_32_47_OFFSET, 3490ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_16_31_OFFSET, 3500ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_0_15_OFFSET, 3510ca7111aSMatus Ujhelyi }; 3520ca7111aSMatus Ujhelyi 3530ca7111aSMatus Ujhelyi if (!ndev) 354ea13c9eeSMugunthan V N return -ENODEV; 3550ca7111aSMatus Ujhelyi 356ea13c9eeSMugunthan V N if (wol->wolopts & WAKE_MAGIC) { 3570ca7111aSMatus Ujhelyi mac = (const u8 *) ndev->dev_addr; 3580ca7111aSMatus Ujhelyi 3590ca7111aSMatus Ujhelyi if (!is_valid_ether_addr(mac)) 360fc755687SDan Murphy return -EINVAL; 3610ca7111aSMatus Ujhelyi 3620e021396SCarlo Caione for (i = 0; i < 3; i++) 363c0f0b563SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 3640ca7111aSMatus Ujhelyi mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 365ea13c9eeSMugunthan V N 3667beecaf7SLuo Jie /* Enable WOL function */ 3677beecaf7SLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 3687beecaf7SLuo Jie 0, AT803X_WOL_EN); 3697beecaf7SLuo Jie if (ret) 3707beecaf7SLuo Jie return ret; 3717beecaf7SLuo Jie /* Enable WOL interrupt */ 3722d4284e8SLuo Jie ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 373ea13c9eeSMugunthan V N if (ret) 374ea13c9eeSMugunthan V N return ret; 375ea13c9eeSMugunthan V N } else { 3767beecaf7SLuo Jie /* Disable WoL function */ 3777beecaf7SLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 3787beecaf7SLuo Jie AT803X_WOL_EN, 0); 3797beecaf7SLuo Jie if (ret) 3807beecaf7SLuo Jie return ret; 3817beecaf7SLuo Jie /* Disable WOL interrupt */ 3822d4284e8SLuo Jie ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 383ea13c9eeSMugunthan V N if (ret) 384ea13c9eeSMugunthan V N return ret; 385ea13c9eeSMugunthan V N } 386ea13c9eeSMugunthan V N 3877beecaf7SLuo Jie /* Clear WOL status */ 3887beecaf7SLuo Jie ret = phy_read(phydev, AT803X_INTR_STATUS); 3897beecaf7SLuo Jie if (ret < 0) 390ea13c9eeSMugunthan V N return ret; 3917beecaf7SLuo Jie 3927beecaf7SLuo Jie /* Check if there are other interrupts except for WOL triggered when PHY is 3937beecaf7SLuo Jie * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 3947beecaf7SLuo Jie * be passed up to the interrupt PIN. 3957beecaf7SLuo Jie */ 3967beecaf7SLuo Jie irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 3977beecaf7SLuo Jie if (irq_enabled < 0) 3987beecaf7SLuo Jie return irq_enabled; 3997beecaf7SLuo Jie 4007beecaf7SLuo Jie irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 4017beecaf7SLuo Jie if (ret & irq_enabled && !phy_polling_mode(phydev)) 4027beecaf7SLuo Jie phy_trigger_machine(phydev); 4037beecaf7SLuo Jie 4047beecaf7SLuo Jie return 0; 405ea13c9eeSMugunthan V N } 406ea13c9eeSMugunthan V N 407ea13c9eeSMugunthan V N static void at803x_get_wol(struct phy_device *phydev, 408ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 409ea13c9eeSMugunthan V N { 410ea13c9eeSMugunthan V N u32 value; 411ea13c9eeSMugunthan V N 412ea13c9eeSMugunthan V N wol->supported = WAKE_MAGIC; 413ea13c9eeSMugunthan V N wol->wolopts = 0; 414ea13c9eeSMugunthan V N 4157beecaf7SLuo Jie value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 4167beecaf7SLuo Jie if (value < 0) 4177beecaf7SLuo Jie return; 4187beecaf7SLuo Jie 4197beecaf7SLuo Jie if (value & AT803X_WOL_EN) 420ea13c9eeSMugunthan V N wol->wolopts |= WAKE_MAGIC; 4210ca7111aSMatus Ujhelyi } 4220ca7111aSMatus Ujhelyi 423272833b9SAnsuel Smith static int at803x_get_sset_count(struct phy_device *phydev) 424272833b9SAnsuel Smith { 425272833b9SAnsuel Smith return ARRAY_SIZE(at803x_hw_stats); 426272833b9SAnsuel Smith } 427272833b9SAnsuel Smith 428272833b9SAnsuel Smith static void at803x_get_strings(struct phy_device *phydev, u8 *data) 429272833b9SAnsuel Smith { 430272833b9SAnsuel Smith int i; 431272833b9SAnsuel Smith 432272833b9SAnsuel Smith for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 433272833b9SAnsuel Smith strscpy(data + i * ETH_GSTRING_LEN, 434272833b9SAnsuel Smith at803x_hw_stats[i].string, ETH_GSTRING_LEN); 435272833b9SAnsuel Smith } 436272833b9SAnsuel Smith } 437272833b9SAnsuel Smith 438272833b9SAnsuel Smith static u64 at803x_get_stat(struct phy_device *phydev, int i) 439272833b9SAnsuel Smith { 440272833b9SAnsuel Smith struct at803x_hw_stat stat = at803x_hw_stats[i]; 441272833b9SAnsuel Smith struct at803x_priv *priv = phydev->priv; 442272833b9SAnsuel Smith int val; 443272833b9SAnsuel Smith u64 ret; 444272833b9SAnsuel Smith 445272833b9SAnsuel Smith if (stat.access_type == MMD) 446272833b9SAnsuel Smith val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 447272833b9SAnsuel Smith else 448272833b9SAnsuel Smith val = phy_read(phydev, stat.reg); 449272833b9SAnsuel Smith 450272833b9SAnsuel Smith if (val < 0) { 451272833b9SAnsuel Smith ret = U64_MAX; 452272833b9SAnsuel Smith } else { 453272833b9SAnsuel Smith val = val & stat.mask; 454272833b9SAnsuel Smith priv->stats[i] += val; 455272833b9SAnsuel Smith ret = priv->stats[i]; 456272833b9SAnsuel Smith } 457272833b9SAnsuel Smith 458272833b9SAnsuel Smith return ret; 459272833b9SAnsuel Smith } 460272833b9SAnsuel Smith 461272833b9SAnsuel Smith static void at803x_get_stats(struct phy_device *phydev, 462272833b9SAnsuel Smith struct ethtool_stats *stats, u64 *data) 463272833b9SAnsuel Smith { 464272833b9SAnsuel Smith int i; 465272833b9SAnsuel Smith 466272833b9SAnsuel Smith for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 467272833b9SAnsuel Smith data[i] = at803x_get_stat(phydev, i); 468272833b9SAnsuel Smith } 469272833b9SAnsuel Smith 4706229ed1fSDaniel Mack static int at803x_suspend(struct phy_device *phydev) 4716229ed1fSDaniel Mack { 4726229ed1fSDaniel Mack int value; 4736229ed1fSDaniel Mack int wol_enabled; 4746229ed1fSDaniel Mack 4756229ed1fSDaniel Mack value = phy_read(phydev, AT803X_INTR_ENABLE); 476e6e4a556SMartin Blumenstingl wol_enabled = value & AT803X_INTR_ENABLE_WOL; 4776229ed1fSDaniel Mack 4786229ed1fSDaniel Mack if (wol_enabled) 479fea23fb5SRussell King value = BMCR_ISOLATE; 4806229ed1fSDaniel Mack else 481fea23fb5SRussell King value = BMCR_PDOWN; 4826229ed1fSDaniel Mack 483fea23fb5SRussell King phy_modify(phydev, MII_BMCR, 0, value); 4846229ed1fSDaniel Mack 4856229ed1fSDaniel Mack return 0; 4866229ed1fSDaniel Mack } 4876229ed1fSDaniel Mack 4886229ed1fSDaniel Mack static int at803x_resume(struct phy_device *phydev) 4896229ed1fSDaniel Mack { 490f102852fSRussell King return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 4916229ed1fSDaniel Mack } 4926229ed1fSDaniel Mack 4932f664823SMichael Walle static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 4942f664823SMichael Walle unsigned int selector) 4952f664823SMichael Walle { 4962f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 4972f664823SMichael Walle 4982f664823SMichael Walle if (selector) 4992f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 5002f664823SMichael Walle 0, AT803X_DEBUG_RGMII_1V8); 5012f664823SMichael Walle else 5022f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 5032f664823SMichael Walle AT803X_DEBUG_RGMII_1V8, 0); 5042f664823SMichael Walle } 5052f664823SMichael Walle 5062f664823SMichael Walle static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 5072f664823SMichael Walle { 5082f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 5092f664823SMichael Walle int val; 5102f664823SMichael Walle 5112f664823SMichael Walle val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 5122f664823SMichael Walle if (val < 0) 5132f664823SMichael Walle return val; 5142f664823SMichael Walle 5152f664823SMichael Walle return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 5162f664823SMichael Walle } 5172f664823SMichael Walle 5183faaf539SRikard Falkeborn static const struct regulator_ops vddio_regulator_ops = { 5192f664823SMichael Walle .list_voltage = regulator_list_voltage_table, 5202f664823SMichael Walle .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 5212f664823SMichael Walle .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 5222f664823SMichael Walle }; 5232f664823SMichael Walle 5242f664823SMichael Walle static const unsigned int vddio_voltage_table[] = { 5252f664823SMichael Walle 1500000, 5262f664823SMichael Walle 1800000, 5272f664823SMichael Walle }; 5282f664823SMichael Walle 5292f664823SMichael Walle static const struct regulator_desc vddio_desc = { 5302f664823SMichael Walle .name = "vddio", 5312f664823SMichael Walle .of_match = of_match_ptr("vddio-regulator"), 5322f664823SMichael Walle .n_voltages = ARRAY_SIZE(vddio_voltage_table), 5332f664823SMichael Walle .volt_table = vddio_voltage_table, 5342f664823SMichael Walle .ops = &vddio_regulator_ops, 5352f664823SMichael Walle .type = REGULATOR_VOLTAGE, 5362f664823SMichael Walle .owner = THIS_MODULE, 5372f664823SMichael Walle }; 5382f664823SMichael Walle 5393faaf539SRikard Falkeborn static const struct regulator_ops vddh_regulator_ops = { 5402f664823SMichael Walle }; 5412f664823SMichael Walle 5422f664823SMichael Walle static const struct regulator_desc vddh_desc = { 5432f664823SMichael Walle .name = "vddh", 5442f664823SMichael Walle .of_match = of_match_ptr("vddh-regulator"), 5452f664823SMichael Walle .n_voltages = 1, 5462f664823SMichael Walle .fixed_uV = 2500000, 5472f664823SMichael Walle .ops = &vddh_regulator_ops, 5482f664823SMichael Walle .type = REGULATOR_VOLTAGE, 5492f664823SMichael Walle .owner = THIS_MODULE, 5502f664823SMichael Walle }; 5512f664823SMichael Walle 5522f664823SMichael Walle static int at8031_register_regulators(struct phy_device *phydev) 5532f664823SMichael Walle { 5542f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 5552f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 5562f664823SMichael Walle struct regulator_config config = { }; 5572f664823SMichael Walle 5582f664823SMichael Walle config.dev = dev; 5592f664823SMichael Walle config.driver_data = phydev; 5602f664823SMichael Walle 5612f664823SMichael Walle priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 5622f664823SMichael Walle if (IS_ERR(priv->vddio_rdev)) { 5632f664823SMichael Walle phydev_err(phydev, "failed to register VDDIO regulator\n"); 5642f664823SMichael Walle return PTR_ERR(priv->vddio_rdev); 5652f664823SMichael Walle } 5662f664823SMichael Walle 5672f664823SMichael Walle priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 5682f664823SMichael Walle if (IS_ERR(priv->vddh_rdev)) { 5692f664823SMichael Walle phydev_err(phydev, "failed to register VDDH regulator\n"); 5702f664823SMichael Walle return PTR_ERR(priv->vddh_rdev); 5712f664823SMichael Walle } 5722f664823SMichael Walle 5732f664823SMichael Walle return 0; 5742f664823SMichael Walle } 5752f664823SMichael Walle 5762f664823SMichael Walle static int at803x_parse_dt(struct phy_device *phydev) 5772f664823SMichael Walle { 5782f664823SMichael Walle struct device_node *node = phydev->mdio.dev.of_node; 5792f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 580390b4cadSRussell King u32 freq, strength, tw; 5813f2edd30SAndrew Lunn unsigned int sel; 5822f664823SMichael Walle int ret; 5832f664823SMichael Walle 5842f664823SMichael Walle if (!IS_ENABLED(CONFIG_OF_MDIO)) 5852f664823SMichael Walle return 0; 5862f664823SMichael Walle 587390b4cadSRussell King if (of_property_read_bool(node, "qca,disable-smarteee")) 588390b4cadSRussell King priv->flags |= AT803X_DISABLE_SMARTEEE; 589390b4cadSRussell King 590390b4cadSRussell King if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 591390b4cadSRussell King if (!tw || tw > 255) { 592390b4cadSRussell King phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 593390b4cadSRussell King return -EINVAL; 594390b4cadSRussell King } 595390b4cadSRussell King priv->smarteee_lpi_tw_1g = tw; 596390b4cadSRussell King } 597390b4cadSRussell King 598390b4cadSRussell King if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 599390b4cadSRussell King if (!tw || tw > 255) { 600390b4cadSRussell King phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 601390b4cadSRussell King return -EINVAL; 602390b4cadSRussell King } 603390b4cadSRussell King priv->smarteee_lpi_tw_100m = tw; 604390b4cadSRussell King } 605390b4cadSRussell King 6062f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 6072f664823SMichael Walle if (!ret) { 6082f664823SMichael Walle switch (freq) { 6092f664823SMichael Walle case 25000000: 6102f664823SMichael Walle sel = AT803X_CLK_OUT_25MHZ_XTAL; 6112f664823SMichael Walle break; 6122f664823SMichael Walle case 50000000: 6132f664823SMichael Walle sel = AT803X_CLK_OUT_50MHZ_PLL; 6142f664823SMichael Walle break; 6152f664823SMichael Walle case 62500000: 6162f664823SMichael Walle sel = AT803X_CLK_OUT_62_5MHZ_PLL; 6172f664823SMichael Walle break; 6182f664823SMichael Walle case 125000000: 6192f664823SMichael Walle sel = AT803X_CLK_OUT_125MHZ_PLL; 6202f664823SMichael Walle break; 6212f664823SMichael Walle default: 6222f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 6232f664823SMichael Walle return -EINVAL; 6242f664823SMichael Walle } 6252f664823SMichael Walle 6263f2edd30SAndrew Lunn priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 6273f2edd30SAndrew Lunn priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 6282f664823SMichael Walle 6292f664823SMichael Walle /* Fixup for the AR8030/AR8035. This chip has another mask and 6302f664823SMichael Walle * doesn't support the DSP reference. Eg. the lowest bit of the 6312f664823SMichael Walle * mask. The upper two bits select the same frequencies. Mask 6322f664823SMichael Walle * the lowest bit here. 6332f664823SMichael Walle * 6342f664823SMichael Walle * Warning: 6352f664823SMichael Walle * There was no datasheet for the AR8030 available so this is 6362f664823SMichael Walle * just a guess. But the AR8035 is listed as pin compatible 6372f664823SMichael Walle * to the AR8030 so there might be a good chance it works on 6382f664823SMichael Walle * the AR8030 too. 6392f664823SMichael Walle */ 6408887ca54SRussell King if (phydev->drv->phy_id == ATH8030_PHY_ID || 6418887ca54SRussell King phydev->drv->phy_id == ATH8035_PHY_ID) { 642b1f4c209SOleksij Rempel priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 643b1f4c209SOleksij Rempel priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 6442f664823SMichael Walle } 6452f664823SMichael Walle } 6462f664823SMichael Walle 6472f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 6482f664823SMichael Walle if (!ret) { 6492f664823SMichael Walle priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 6502f664823SMichael Walle switch (strength) { 6512f664823SMichael Walle case AR803X_STRENGTH_FULL: 6522f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 6532f664823SMichael Walle break; 6542f664823SMichael Walle case AR803X_STRENGTH_HALF: 6552f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 6562f664823SMichael Walle break; 6572f664823SMichael Walle case AR803X_STRENGTH_QUARTER: 6582f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 6592f664823SMichael Walle break; 6602f664823SMichael Walle default: 6612f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-strength\n"); 6622f664823SMichael Walle return -EINVAL; 6632f664823SMichael Walle } 6642f664823SMichael Walle } 6652f664823SMichael Walle 666428061f7SMichael Walle /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 667428061f7SMichael Walle * options. 668428061f7SMichael Walle */ 6698887ca54SRussell King if (phydev->drv->phy_id == ATH8031_PHY_ID) { 6702f664823SMichael Walle if (of_property_read_bool(node, "qca,keep-pll-enabled")) 6712f664823SMichael Walle priv->flags |= AT803X_KEEP_PLL_ENABLED; 6722f664823SMichael Walle 6732f664823SMichael Walle ret = at8031_register_regulators(phydev); 6742f664823SMichael Walle if (ret < 0) 6752f664823SMichael Walle return ret; 6762f664823SMichael Walle 6772f664823SMichael Walle priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 6782f664823SMichael Walle "vddio"); 6792f664823SMichael Walle if (IS_ERR(priv->vddio)) { 6802f664823SMichael Walle phydev_err(phydev, "failed to get VDDIO regulator\n"); 6812f664823SMichael Walle return PTR_ERR(priv->vddio); 6822f664823SMichael Walle } 6832f664823SMichael Walle } 6842f664823SMichael Walle 6852f664823SMichael Walle return 0; 6862f664823SMichael Walle } 6872f664823SMichael Walle 6882f664823SMichael Walle static int at803x_probe(struct phy_device *phydev) 6892f664823SMichael Walle { 6902f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 6912f664823SMichael Walle struct at803x_priv *priv; 692c329e5afSDavid Bauer int ret; 6932f664823SMichael Walle 6942f664823SMichael Walle priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 6952f664823SMichael Walle if (!priv) 6962f664823SMichael Walle return -ENOMEM; 6972f664823SMichael Walle 6982f664823SMichael Walle phydev->priv = priv; 6992f664823SMichael Walle 700c329e5afSDavid Bauer ret = at803x_parse_dt(phydev); 701c329e5afSDavid Bauer if (ret) 702c329e5afSDavid Bauer return ret; 703c329e5afSDavid Bauer 7048f7e8762SMichael Walle if (priv->vddio) { 7058f7e8762SMichael Walle ret = regulator_enable(priv->vddio); 7068f7e8762SMichael Walle if (ret < 0) 7078f7e8762SMichael Walle return ret; 7088f7e8762SMichael Walle } 7098f7e8762SMichael Walle 710c329e5afSDavid Bauer /* Some bootloaders leave the fiber page selected. 711c329e5afSDavid Bauer * Switch to the copper page, as otherwise we read 712c329e5afSDavid Bauer * the PHY capabilities from the fiber side. 713c329e5afSDavid Bauer */ 7148887ca54SRussell King if (phydev->drv->phy_id == ATH8031_PHY_ID) { 7158f7e8762SMichael Walle phy_lock_mdio_bus(phydev); 7168f7e8762SMichael Walle ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); 7178f7e8762SMichael Walle phy_unlock_mdio_bus(phydev); 7188f7e8762SMichael Walle if (ret) 7198f7e8762SMichael Walle goto err; 720c329e5afSDavid Bauer } 721c329e5afSDavid Bauer 7228f7e8762SMichael Walle return 0; 7238f7e8762SMichael Walle 7248f7e8762SMichael Walle err: 7258f7e8762SMichael Walle if (priv->vddio) 7268f7e8762SMichael Walle regulator_disable(priv->vddio); 7278f7e8762SMichael Walle 728c329e5afSDavid Bauer return ret; 7292f664823SMichael Walle } 7302f664823SMichael Walle 7312318ca8aSMichael Walle static void at803x_remove(struct phy_device *phydev) 7322318ca8aSMichael Walle { 7332318ca8aSMichael Walle struct at803x_priv *priv = phydev->priv; 7342318ca8aSMichael Walle 7352318ca8aSMichael Walle if (priv->vddio) 7362318ca8aSMichael Walle regulator_disable(priv->vddio); 7372318ca8aSMichael Walle } 7382318ca8aSMichael Walle 739b856150cSDavid Bauer static int at803x_get_features(struct phy_device *phydev) 740b856150cSDavid Bauer { 741b856150cSDavid Bauer int err; 742b856150cSDavid Bauer 743b856150cSDavid Bauer err = genphy_read_abilities(phydev); 744b856150cSDavid Bauer if (err) 745b856150cSDavid Bauer return err; 746b856150cSDavid Bauer 747f5621a01SVladimir Oltean if (phydev->drv->phy_id != ATH8031_PHY_ID) 748b856150cSDavid Bauer return 0; 749b856150cSDavid Bauer 750b856150cSDavid Bauer /* AR8031/AR8033 have different status registers 751b856150cSDavid Bauer * for copper and fiber operation. However, the 752b856150cSDavid Bauer * extended status register is the same for both 753b856150cSDavid Bauer * operation modes. 754b856150cSDavid Bauer * 755b856150cSDavid Bauer * As a result of that, ESTATUS_1000_XFULL is set 756b856150cSDavid Bauer * to 1 even when operating in copper TP mode. 757b856150cSDavid Bauer * 758b856150cSDavid Bauer * Remove this mode from the supported link modes, 759b856150cSDavid Bauer * as this driver currently only supports copper 760b856150cSDavid Bauer * operation. 761b856150cSDavid Bauer */ 762b856150cSDavid Bauer linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 763b856150cSDavid Bauer phydev->supported); 764b856150cSDavid Bauer return 0; 765b856150cSDavid Bauer } 766b856150cSDavid Bauer 767390b4cadSRussell King static int at803x_smarteee_config(struct phy_device *phydev) 768390b4cadSRussell King { 769390b4cadSRussell King struct at803x_priv *priv = phydev->priv; 770390b4cadSRussell King u16 mask = 0, val = 0; 771390b4cadSRussell King int ret; 772390b4cadSRussell King 773390b4cadSRussell King if (priv->flags & AT803X_DISABLE_SMARTEEE) 774390b4cadSRussell King return phy_modify_mmd(phydev, MDIO_MMD_PCS, 775390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3, 776390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 777390b4cadSRussell King 778390b4cadSRussell King if (priv->smarteee_lpi_tw_1g) { 779390b4cadSRussell King mask |= 0xff00; 780390b4cadSRussell King val |= priv->smarteee_lpi_tw_1g << 8; 781390b4cadSRussell King } 782390b4cadSRussell King if (priv->smarteee_lpi_tw_100m) { 783390b4cadSRussell King mask |= 0x00ff; 784390b4cadSRussell King val |= priv->smarteee_lpi_tw_100m; 785390b4cadSRussell King } 786390b4cadSRussell King if (!mask) 787390b4cadSRussell King return 0; 788390b4cadSRussell King 789390b4cadSRussell King ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 790390b4cadSRussell King mask, val); 791390b4cadSRussell King if (ret) 792390b4cadSRussell King return ret; 793390b4cadSRussell King 794390b4cadSRussell King return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 795390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 796390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 797390b4cadSRussell King } 798390b4cadSRussell King 7992f664823SMichael Walle static int at803x_clk_out_config(struct phy_device *phydev) 8002f664823SMichael Walle { 8012f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 8022f664823SMichael Walle 8032f664823SMichael Walle if (!priv->clk_25m_mask) 8042f664823SMichael Walle return 0; 8052f664823SMichael Walle 806a45c1c10SRussell King return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 807a45c1c10SRussell King priv->clk_25m_mask, priv->clk_25m_reg); 8082f664823SMichael Walle } 8092f664823SMichael Walle 8102f664823SMichael Walle static int at8031_pll_config(struct phy_device *phydev) 8112f664823SMichael Walle { 8122f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 8132f664823SMichael Walle 8142f664823SMichael Walle /* The default after hardware reset is PLL OFF. After a soft reset, the 8152f664823SMichael Walle * values are retained. 8162f664823SMichael Walle */ 8172f664823SMichael Walle if (priv->flags & AT803X_KEEP_PLL_ENABLED) 8182f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 8192f664823SMichael Walle 0, AT803X_DEBUG_PLL_ON); 8202f664823SMichael Walle else 8212f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 8222f664823SMichael Walle AT803X_DEBUG_PLL_ON, 0); 8232f664823SMichael Walle } 8242f664823SMichael Walle 8250ca7111aSMatus Ujhelyi static int at803x_config_init(struct phy_device *phydev) 8260ca7111aSMatus Ujhelyi { 8271ca6d1b1SMugunthan V N int ret; 8280ca7111aSMatus Ujhelyi 8296d4cd041SVinod Koul /* The RX and TX delay default is: 8306d4cd041SVinod Koul * after HW reset: RX delay enabled and TX delay disabled 8316d4cd041SVinod Koul * after SW reset: RX delay enabled, while TX delay retains the 8326d4cd041SVinod Koul * value before reset. 8336d4cd041SVinod Koul */ 834bb0ce4c1SAndré Draszik if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 835bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 836bb0ce4c1SAndré Draszik ret = at803x_enable_rx_delay(phydev); 837bb0ce4c1SAndré Draszik else 838cd28d1d6SVinod Koul ret = at803x_disable_rx_delay(phydev); 8392e5f9f28SMartin Blumenstingl if (ret < 0) 8401ca6d1b1SMugunthan V N return ret; 8416d4cd041SVinod Koul 8426d4cd041SVinod Koul if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 843bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 8446d4cd041SVinod Koul ret = at803x_enable_tx_delay(phydev); 845bb0ce4c1SAndré Draszik else 846bb0ce4c1SAndré Draszik ret = at803x_disable_tx_delay(phydev); 8472f664823SMichael Walle if (ret < 0) 8486d4cd041SVinod Koul return ret; 8492f664823SMichael Walle 850390b4cadSRussell King ret = at803x_smarteee_config(phydev); 851390b4cadSRussell King if (ret < 0) 852390b4cadSRussell King return ret; 853390b4cadSRussell King 8542f664823SMichael Walle ret = at803x_clk_out_config(phydev); 8552f664823SMichael Walle if (ret < 0) 8562f664823SMichael Walle return ret; 8572f664823SMichael Walle 8588887ca54SRussell King if (phydev->drv->phy_id == ATH8031_PHY_ID) { 8592f664823SMichael Walle ret = at8031_pll_config(phydev); 8602f664823SMichael Walle if (ret < 0) 8612f664823SMichael Walle return ret; 8622f664823SMichael Walle } 8632f664823SMichael Walle 8643c51fa5dSRussell King /* Ar803x extended next page bit is enabled by default. Cisco 8653c51fa5dSRussell King * multigig switches read this bit and attempt to negotiate 10Gbps 8663c51fa5dSRussell King * rates even if the next page bit is disabled. This is incorrect 8673c51fa5dSRussell King * behaviour but we still need to accommodate it. XNP is only needed 8683c51fa5dSRussell King * for 10Gbps support, so disable XNP. 8693c51fa5dSRussell King */ 8703c51fa5dSRussell King return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 8710ca7111aSMatus Ujhelyi } 8720ca7111aSMatus Ujhelyi 87377a99394SZhao Qiang static int at803x_ack_interrupt(struct phy_device *phydev) 87477a99394SZhao Qiang { 87577a99394SZhao Qiang int err; 87677a99394SZhao Qiang 877a46bd63bSMartin Blumenstingl err = phy_read(phydev, AT803X_INTR_STATUS); 87877a99394SZhao Qiang 87977a99394SZhao Qiang return (err < 0) ? err : 0; 88077a99394SZhao Qiang } 88177a99394SZhao Qiang 88277a99394SZhao Qiang static int at803x_config_intr(struct phy_device *phydev) 88377a99394SZhao Qiang { 88477a99394SZhao Qiang int err; 88577a99394SZhao Qiang int value; 88677a99394SZhao Qiang 887a46bd63bSMartin Blumenstingl value = phy_read(phydev, AT803X_INTR_ENABLE); 88877a99394SZhao Qiang 889e6e4a556SMartin Blumenstingl if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 890a3417885SIoana Ciornei /* Clear any pending interrupts */ 891a3417885SIoana Ciornei err = at803x_ack_interrupt(phydev); 892a3417885SIoana Ciornei if (err) 893a3417885SIoana Ciornei return err; 894a3417885SIoana Ciornei 895e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 896e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 897e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 898e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_FAIL; 899e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 900e6e4a556SMartin Blumenstingl 901e6e4a556SMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, value); 902a3417885SIoana Ciornei } else { 903a46bd63bSMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 904a3417885SIoana Ciornei if (err) 905a3417885SIoana Ciornei return err; 906a3417885SIoana Ciornei 907a3417885SIoana Ciornei /* Clear any pending interrupts */ 908a3417885SIoana Ciornei err = at803x_ack_interrupt(phydev); 909a3417885SIoana Ciornei } 91077a99394SZhao Qiang 91177a99394SZhao Qiang return err; 91277a99394SZhao Qiang } 91377a99394SZhao Qiang 91429773097SIoana Ciornei static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 91529773097SIoana Ciornei { 91629773097SIoana Ciornei int irq_status, int_enabled; 91729773097SIoana Ciornei 91829773097SIoana Ciornei irq_status = phy_read(phydev, AT803X_INTR_STATUS); 91929773097SIoana Ciornei if (irq_status < 0) { 92029773097SIoana Ciornei phy_error(phydev); 92129773097SIoana Ciornei return IRQ_NONE; 92229773097SIoana Ciornei } 92329773097SIoana Ciornei 92429773097SIoana Ciornei /* Read the current enabled interrupts */ 92529773097SIoana Ciornei int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 92629773097SIoana Ciornei if (int_enabled < 0) { 92729773097SIoana Ciornei phy_error(phydev); 92829773097SIoana Ciornei return IRQ_NONE; 92929773097SIoana Ciornei } 93029773097SIoana Ciornei 93129773097SIoana Ciornei /* See if this was one of our enabled interrupts */ 93229773097SIoana Ciornei if (!(irq_status & int_enabled)) 93329773097SIoana Ciornei return IRQ_NONE; 93429773097SIoana Ciornei 93529773097SIoana Ciornei phy_trigger_machine(phydev); 93629773097SIoana Ciornei 93729773097SIoana Ciornei return IRQ_HANDLED; 93829773097SIoana Ciornei } 93929773097SIoana Ciornei 94013a56b44SDaniel Mack static void at803x_link_change_notify(struct phy_device *phydev) 94113a56b44SDaniel Mack { 94213a56b44SDaniel Mack /* 94313a56b44SDaniel Mack * Conduct a hardware reset for AT8030 every time a link loss is 94413a56b44SDaniel Mack * signalled. This is necessary to circumvent a hardware bug that 94513a56b44SDaniel Mack * occurs when the cable is unplugged while TX packets are pending 94613a56b44SDaniel Mack * in the FIFO. In such cases, the FIFO enters an error mode it 94713a56b44SDaniel Mack * cannot recover from by software. 94813a56b44SDaniel Mack */ 9496110ed2dSDavid Bauer if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 95013a56b44SDaniel Mack struct at803x_context context; 95113a56b44SDaniel Mack 95213a56b44SDaniel Mack at803x_context_save(phydev, &context); 95313a56b44SDaniel Mack 954bafbdd52SSergei Shtylyov phy_device_reset(phydev, 1); 95513a56b44SDaniel Mack msleep(1); 956bafbdd52SSergei Shtylyov phy_device_reset(phydev, 0); 957d57019d1SSergei Shtylyov msleep(1); 95813a56b44SDaniel Mack 95913a56b44SDaniel Mack at803x_context_restore(phydev, &context); 96013a56b44SDaniel Mack 9615c5f626bSHeiner Kallweit phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 96213a56b44SDaniel Mack } 96313a56b44SDaniel Mack } 96413a56b44SDaniel Mack 965*79c7bc05SLuo Jie static int at803x_read_specific_status(struct phy_device *phydev) 96606d5f344SRussell King { 967*79c7bc05SLuo Jie int ss; 96806d5f344SRussell King 96906d5f344SRussell King /* Read the AT8035 PHY-Specific Status register, which indicates the 97006d5f344SRussell King * speed and duplex that the PHY is actually using, irrespective of 97106d5f344SRussell King * whether we are in autoneg mode or not. 97206d5f344SRussell King */ 97306d5f344SRussell King ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 97406d5f344SRussell King if (ss < 0) 97506d5f344SRussell King return ss; 97606d5f344SRussell King 97706d5f344SRussell King if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 978*79c7bc05SLuo Jie int sfc, speed; 9797dce80c2SOleksij Rempel 9807dce80c2SOleksij Rempel sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 9817dce80c2SOleksij Rempel if (sfc < 0) 9827dce80c2SOleksij Rempel return sfc; 9837dce80c2SOleksij Rempel 984*79c7bc05SLuo Jie /* qca8081 takes the different bits for speed value from at803x */ 985*79c7bc05SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) 986*79c7bc05SLuo Jie speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 987*79c7bc05SLuo Jie else 988*79c7bc05SLuo Jie speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 989*79c7bc05SLuo Jie 990*79c7bc05SLuo Jie switch (speed) { 99106d5f344SRussell King case AT803X_SS_SPEED_10: 99206d5f344SRussell King phydev->speed = SPEED_10; 99306d5f344SRussell King break; 99406d5f344SRussell King case AT803X_SS_SPEED_100: 99506d5f344SRussell King phydev->speed = SPEED_100; 99606d5f344SRussell King break; 99706d5f344SRussell King case AT803X_SS_SPEED_1000: 99806d5f344SRussell King phydev->speed = SPEED_1000; 99906d5f344SRussell King break; 1000*79c7bc05SLuo Jie case QCA808X_SS_SPEED_2500: 1001*79c7bc05SLuo Jie phydev->speed = SPEED_2500; 1002*79c7bc05SLuo Jie break; 100306d5f344SRussell King } 100406d5f344SRussell King if (ss & AT803X_SS_DUPLEX) 100506d5f344SRussell King phydev->duplex = DUPLEX_FULL; 100606d5f344SRussell King else 100706d5f344SRussell King phydev->duplex = DUPLEX_HALF; 10087dce80c2SOleksij Rempel 100906d5f344SRussell King if (ss & AT803X_SS_MDIX) 101006d5f344SRussell King phydev->mdix = ETH_TP_MDI_X; 101106d5f344SRussell King else 101206d5f344SRussell King phydev->mdix = ETH_TP_MDI; 10137dce80c2SOleksij Rempel 10147dce80c2SOleksij Rempel switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 10157dce80c2SOleksij Rempel case AT803X_SFC_MANUAL_MDI: 10167dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI; 10177dce80c2SOleksij Rempel break; 10187dce80c2SOleksij Rempel case AT803X_SFC_MANUAL_MDIX: 10197dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_X; 10207dce80c2SOleksij Rempel break; 10217dce80c2SOleksij Rempel case AT803X_SFC_AUTOMATIC_CROSSOVER: 10227dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 10237dce80c2SOleksij Rempel break; 10247dce80c2SOleksij Rempel } 102506d5f344SRussell King } 102606d5f344SRussell King 1027*79c7bc05SLuo Jie return 0; 1028*79c7bc05SLuo Jie } 1029*79c7bc05SLuo Jie 1030*79c7bc05SLuo Jie static int at803x_read_status(struct phy_device *phydev) 1031*79c7bc05SLuo Jie { 1032*79c7bc05SLuo Jie int err, old_link = phydev->link; 1033*79c7bc05SLuo Jie 1034*79c7bc05SLuo Jie /* Update the link, but return if there was an error */ 1035*79c7bc05SLuo Jie err = genphy_update_link(phydev); 1036*79c7bc05SLuo Jie if (err) 1037*79c7bc05SLuo Jie return err; 1038*79c7bc05SLuo Jie 1039*79c7bc05SLuo Jie /* why bother the PHY if nothing can have changed */ 1040*79c7bc05SLuo Jie if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 1041*79c7bc05SLuo Jie return 0; 1042*79c7bc05SLuo Jie 1043*79c7bc05SLuo Jie phydev->speed = SPEED_UNKNOWN; 1044*79c7bc05SLuo Jie phydev->duplex = DUPLEX_UNKNOWN; 1045*79c7bc05SLuo Jie phydev->pause = 0; 1046*79c7bc05SLuo Jie phydev->asym_pause = 0; 1047*79c7bc05SLuo Jie 1048*79c7bc05SLuo Jie err = genphy_read_lpa(phydev); 1049*79c7bc05SLuo Jie if (err < 0) 1050*79c7bc05SLuo Jie return err; 1051*79c7bc05SLuo Jie 1052*79c7bc05SLuo Jie err = at803x_read_specific_status(phydev); 1053*79c7bc05SLuo Jie if (err < 0) 1054*79c7bc05SLuo Jie return err; 1055*79c7bc05SLuo Jie 105606d5f344SRussell King if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 105706d5f344SRussell King phy_resolve_aneg_pause(phydev); 105806d5f344SRussell King 105906d5f344SRussell King return 0; 106006d5f344SRussell King } 106106d5f344SRussell King 10627dce80c2SOleksij Rempel static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 10637dce80c2SOleksij Rempel { 10647dce80c2SOleksij Rempel u16 val; 10657dce80c2SOleksij Rempel 10667dce80c2SOleksij Rempel switch (ctrl) { 10677dce80c2SOleksij Rempel case ETH_TP_MDI: 10687dce80c2SOleksij Rempel val = AT803X_SFC_MANUAL_MDI; 10697dce80c2SOleksij Rempel break; 10707dce80c2SOleksij Rempel case ETH_TP_MDI_X: 10717dce80c2SOleksij Rempel val = AT803X_SFC_MANUAL_MDIX; 10727dce80c2SOleksij Rempel break; 10737dce80c2SOleksij Rempel case ETH_TP_MDI_AUTO: 10747dce80c2SOleksij Rempel val = AT803X_SFC_AUTOMATIC_CROSSOVER; 10757dce80c2SOleksij Rempel break; 10767dce80c2SOleksij Rempel default: 10777dce80c2SOleksij Rempel return 0; 10787dce80c2SOleksij Rempel } 10797dce80c2SOleksij Rempel 10807dce80c2SOleksij Rempel return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 10817dce80c2SOleksij Rempel AT803X_SFC_MDI_CROSSOVER_MODE_M, 10827dce80c2SOleksij Rempel FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 10837dce80c2SOleksij Rempel } 10847dce80c2SOleksij Rempel 10857dce80c2SOleksij Rempel static int at803x_config_aneg(struct phy_device *phydev) 10867dce80c2SOleksij Rempel { 10877dce80c2SOleksij Rempel int ret; 10887dce80c2SOleksij Rempel 10897dce80c2SOleksij Rempel ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 10907dce80c2SOleksij Rempel if (ret < 0) 10917dce80c2SOleksij Rempel return ret; 10927dce80c2SOleksij Rempel 10937dce80c2SOleksij Rempel /* Changes of the midx bits are disruptive to the normal operation; 10947dce80c2SOleksij Rempel * therefore any changes to these registers must be followed by a 10957dce80c2SOleksij Rempel * software reset to take effect. 10967dce80c2SOleksij Rempel */ 10977dce80c2SOleksij Rempel if (ret == 1) { 10987dce80c2SOleksij Rempel ret = genphy_soft_reset(phydev); 10997dce80c2SOleksij Rempel if (ret < 0) 11007dce80c2SOleksij Rempel return ret; 11017dce80c2SOleksij Rempel } 11027dce80c2SOleksij Rempel 11037dce80c2SOleksij Rempel return genphy_config_aneg(phydev); 11047dce80c2SOleksij Rempel } 11057dce80c2SOleksij Rempel 1106cde0f4f8SMichael Walle static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1107cde0f4f8SMichael Walle { 1108cde0f4f8SMichael Walle int val; 1109cde0f4f8SMichael Walle 1110cde0f4f8SMichael Walle val = phy_read(phydev, AT803X_SMART_SPEED); 1111cde0f4f8SMichael Walle if (val < 0) 1112cde0f4f8SMichael Walle return val; 1113cde0f4f8SMichael Walle 1114cde0f4f8SMichael Walle if (val & AT803X_SMART_SPEED_ENABLE) 1115cde0f4f8SMichael Walle *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1116cde0f4f8SMichael Walle else 1117cde0f4f8SMichael Walle *d = DOWNSHIFT_DEV_DISABLE; 1118cde0f4f8SMichael Walle 1119cde0f4f8SMichael Walle return 0; 1120cde0f4f8SMichael Walle } 1121cde0f4f8SMichael Walle 1122cde0f4f8SMichael Walle static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1123cde0f4f8SMichael Walle { 1124cde0f4f8SMichael Walle u16 mask, set; 1125cde0f4f8SMichael Walle int ret; 1126cde0f4f8SMichael Walle 1127cde0f4f8SMichael Walle switch (cnt) { 1128cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DEFAULT_COUNT: 1129cde0f4f8SMichael Walle cnt = AT803X_DEFAULT_DOWNSHIFT; 1130cde0f4f8SMichael Walle fallthrough; 1131cde0f4f8SMichael Walle case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1132cde0f4f8SMichael Walle set = AT803X_SMART_SPEED_ENABLE | 1133cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER | 1134cde0f4f8SMichael Walle FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1135cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1136cde0f4f8SMichael Walle break; 1137cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DISABLE: 1138cde0f4f8SMichael Walle set = 0; 1139cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_ENABLE | 1140cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER; 1141cde0f4f8SMichael Walle break; 1142cde0f4f8SMichael Walle default: 1143cde0f4f8SMichael Walle return -EINVAL; 1144cde0f4f8SMichael Walle } 1145cde0f4f8SMichael Walle 1146cde0f4f8SMichael Walle ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1147cde0f4f8SMichael Walle 1148cde0f4f8SMichael Walle /* After changing the smart speed settings, we need to perform a 1149cde0f4f8SMichael Walle * software reset, use phy_init_hw() to make sure we set the 1150cde0f4f8SMichael Walle * reapply any values which might got lost during software reset. 1151cde0f4f8SMichael Walle */ 1152cde0f4f8SMichael Walle if (ret == 1) 1153cde0f4f8SMichael Walle ret = phy_init_hw(phydev); 1154cde0f4f8SMichael Walle 1155cde0f4f8SMichael Walle return ret; 1156cde0f4f8SMichael Walle } 1157cde0f4f8SMichael Walle 1158cde0f4f8SMichael Walle static int at803x_get_tunable(struct phy_device *phydev, 1159cde0f4f8SMichael Walle struct ethtool_tunable *tuna, void *data) 1160cde0f4f8SMichael Walle { 1161cde0f4f8SMichael Walle switch (tuna->id) { 1162cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 1163cde0f4f8SMichael Walle return at803x_get_downshift(phydev, data); 1164cde0f4f8SMichael Walle default: 1165cde0f4f8SMichael Walle return -EOPNOTSUPP; 1166cde0f4f8SMichael Walle } 1167cde0f4f8SMichael Walle } 1168cde0f4f8SMichael Walle 1169cde0f4f8SMichael Walle static int at803x_set_tunable(struct phy_device *phydev, 1170cde0f4f8SMichael Walle struct ethtool_tunable *tuna, const void *data) 1171cde0f4f8SMichael Walle { 1172cde0f4f8SMichael Walle switch (tuna->id) { 1173cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 1174cde0f4f8SMichael Walle return at803x_set_downshift(phydev, *(const u8 *)data); 1175cde0f4f8SMichael Walle default: 1176cde0f4f8SMichael Walle return -EOPNOTSUPP; 1177cde0f4f8SMichael Walle } 1178cde0f4f8SMichael Walle } 1179cde0f4f8SMichael Walle 11806cb75767SMichael Walle static int at803x_cable_test_result_trans(u16 status) 11816cb75767SMichael Walle { 11826cb75767SMichael Walle switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 11836cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_NORMAL: 11846cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_OK; 11856cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_SHORT: 11866cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 11876cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_OPEN: 11886cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 11896cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_FAIL: 11906cb75767SMichael Walle default: 11916cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 11926cb75767SMichael Walle } 11936cb75767SMichael Walle } 11946cb75767SMichael Walle 11956cb75767SMichael Walle static bool at803x_cdt_test_failed(u16 status) 11966cb75767SMichael Walle { 11976cb75767SMichael Walle return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 11986cb75767SMichael Walle AT803X_CDT_STATUS_STAT_FAIL; 11996cb75767SMichael Walle } 12006cb75767SMichael Walle 12016cb75767SMichael Walle static bool at803x_cdt_fault_length_valid(u16 status) 12026cb75767SMichael Walle { 12036cb75767SMichael Walle switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 12046cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_OPEN: 12056cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_SHORT: 12066cb75767SMichael Walle return true; 12076cb75767SMichael Walle } 12086cb75767SMichael Walle return false; 12096cb75767SMichael Walle } 12106cb75767SMichael Walle 12116cb75767SMichael Walle static int at803x_cdt_fault_length(u16 status) 12126cb75767SMichael Walle { 12136cb75767SMichael Walle int dt; 12146cb75767SMichael Walle 12156cb75767SMichael Walle /* According to the datasheet the distance to the fault is 12166cb75767SMichael Walle * DELTA_TIME * 0.824 meters. 12176cb75767SMichael Walle * 12186cb75767SMichael Walle * The author suspect the correct formula is: 12196cb75767SMichael Walle * 12206cb75767SMichael Walle * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 12216cb75767SMichael Walle * 12226cb75767SMichael Walle * where c is the speed of light, VF is the velocity factor of 12236cb75767SMichael Walle * the twisted pair cable, 125MHz the counter frequency and 12246cb75767SMichael Walle * we need to divide by 2 because the hardware will measure the 12256cb75767SMichael Walle * round trip time to the fault and back to the PHY. 12266cb75767SMichael Walle * 12276cb75767SMichael Walle * With a VF of 0.69 we get the factor 0.824 mentioned in the 12286cb75767SMichael Walle * datasheet. 12296cb75767SMichael Walle */ 12306cb75767SMichael Walle dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 12316cb75767SMichael Walle 12326cb75767SMichael Walle return (dt * 824) / 10; 12336cb75767SMichael Walle } 12346cb75767SMichael Walle 12356cb75767SMichael Walle static int at803x_cdt_start(struct phy_device *phydev, int pair) 12366cb75767SMichael Walle { 12376cb75767SMichael Walle u16 cdt; 12386cb75767SMichael Walle 12396cb75767SMichael Walle cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 12406cb75767SMichael Walle AT803X_CDT_ENABLE_TEST; 12416cb75767SMichael Walle 12426cb75767SMichael Walle return phy_write(phydev, AT803X_CDT, cdt); 12436cb75767SMichael Walle } 12446cb75767SMichael Walle 12456cb75767SMichael Walle static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 12466cb75767SMichael Walle { 12476cb75767SMichael Walle int val, ret; 12486cb75767SMichael Walle 12496cb75767SMichael Walle /* One test run takes about 25ms */ 12506cb75767SMichael Walle ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 12516cb75767SMichael Walle !(val & AT803X_CDT_ENABLE_TEST), 12526cb75767SMichael Walle 30000, 100000, true); 12536cb75767SMichael Walle 12546cb75767SMichael Walle return ret < 0 ? ret : 0; 12556cb75767SMichael Walle } 12566cb75767SMichael Walle 12576cb75767SMichael Walle static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 12586cb75767SMichael Walle { 12596cb75767SMichael Walle static const int ethtool_pair[] = { 12606cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_A, 12616cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_B, 12626cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_C, 12636cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_D, 12646cb75767SMichael Walle }; 12656cb75767SMichael Walle int ret, val; 12666cb75767SMichael Walle 12676cb75767SMichael Walle ret = at803x_cdt_start(phydev, pair); 12686cb75767SMichael Walle if (ret) 12696cb75767SMichael Walle return ret; 12706cb75767SMichael Walle 12716cb75767SMichael Walle ret = at803x_cdt_wait_for_completion(phydev); 12726cb75767SMichael Walle if (ret) 12736cb75767SMichael Walle return ret; 12746cb75767SMichael Walle 12756cb75767SMichael Walle val = phy_read(phydev, AT803X_CDT_STATUS); 12766cb75767SMichael Walle if (val < 0) 12776cb75767SMichael Walle return val; 12786cb75767SMichael Walle 12796cb75767SMichael Walle if (at803x_cdt_test_failed(val)) 12806cb75767SMichael Walle return 0; 12816cb75767SMichael Walle 12826cb75767SMichael Walle ethnl_cable_test_result(phydev, ethtool_pair[pair], 12836cb75767SMichael Walle at803x_cable_test_result_trans(val)); 12846cb75767SMichael Walle 12856cb75767SMichael Walle if (at803x_cdt_fault_length_valid(val)) 12866cb75767SMichael Walle ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 12876cb75767SMichael Walle at803x_cdt_fault_length(val)); 12886cb75767SMichael Walle 12896cb75767SMichael Walle return 1; 12906cb75767SMichael Walle } 12916cb75767SMichael Walle 12926cb75767SMichael Walle static int at803x_cable_test_get_status(struct phy_device *phydev, 12936cb75767SMichael Walle bool *finished) 12946cb75767SMichael Walle { 1295dc0f3ed1SOleksij Rempel unsigned long pair_mask; 12966cb75767SMichael Walle int retries = 20; 12976cb75767SMichael Walle int pair, ret; 12986cb75767SMichael Walle 1299dc0f3ed1SOleksij Rempel if (phydev->phy_id == ATH9331_PHY_ID || 1300fada2ce0SDavid Bauer phydev->phy_id == ATH8032_PHY_ID || 1301fada2ce0SDavid Bauer phydev->phy_id == QCA9561_PHY_ID) 1302dc0f3ed1SOleksij Rempel pair_mask = 0x3; 1303dc0f3ed1SOleksij Rempel else 1304dc0f3ed1SOleksij Rempel pair_mask = 0xf; 1305dc0f3ed1SOleksij Rempel 13066cb75767SMichael Walle *finished = false; 13076cb75767SMichael Walle 13086cb75767SMichael Walle /* According to the datasheet the CDT can be performed when 13096cb75767SMichael Walle * there is no link partner or when the link partner is 13106cb75767SMichael Walle * auto-negotiating. Starting the test will restart the AN 13116cb75767SMichael Walle * automatically. It seems that doing this repeatedly we will 13126cb75767SMichael Walle * get a slot where our link partner won't disturb our 13136cb75767SMichael Walle * measurement. 13146cb75767SMichael Walle */ 13156cb75767SMichael Walle while (pair_mask && retries--) { 13166cb75767SMichael Walle for_each_set_bit(pair, &pair_mask, 4) { 13176cb75767SMichael Walle ret = at803x_cable_test_one_pair(phydev, pair); 13186cb75767SMichael Walle if (ret < 0) 13196cb75767SMichael Walle return ret; 13206cb75767SMichael Walle if (ret) 13216cb75767SMichael Walle clear_bit(pair, &pair_mask); 13226cb75767SMichael Walle } 13236cb75767SMichael Walle if (pair_mask) 13246cb75767SMichael Walle msleep(250); 13256cb75767SMichael Walle } 13266cb75767SMichael Walle 13276cb75767SMichael Walle *finished = true; 13286cb75767SMichael Walle 13296cb75767SMichael Walle return 0; 13306cb75767SMichael Walle } 13316cb75767SMichael Walle 13326cb75767SMichael Walle static int at803x_cable_test_start(struct phy_device *phydev) 13336cb75767SMichael Walle { 13346cb75767SMichael Walle /* Enable auto-negotiation, but advertise no capabilities, no link 13356cb75767SMichael Walle * will be established. A restart of the auto-negotiation is not 13366cb75767SMichael Walle * required, because the cable test will automatically break the link. 13376cb75767SMichael Walle */ 13386cb75767SMichael Walle phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 13396cb75767SMichael Walle phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1340dc0f3ed1SOleksij Rempel if (phydev->phy_id != ATH9331_PHY_ID && 1341fada2ce0SDavid Bauer phydev->phy_id != ATH8032_PHY_ID && 1342fada2ce0SDavid Bauer phydev->phy_id != QCA9561_PHY_ID) 13436cb75767SMichael Walle phy_write(phydev, MII_CTRL1000, 0); 13446cb75767SMichael Walle 13456cb75767SMichael Walle /* we do all the (time consuming) work later */ 13466cb75767SMichael Walle return 0; 13476cb75767SMichael Walle } 13486cb75767SMichael Walle 1349272833b9SAnsuel Smith static int qca83xx_config_init(struct phy_device *phydev) 1350272833b9SAnsuel Smith { 1351272833b9SAnsuel Smith u8 switch_revision; 1352272833b9SAnsuel Smith 1353272833b9SAnsuel Smith switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1354272833b9SAnsuel Smith 1355272833b9SAnsuel Smith switch (switch_revision) { 1356272833b9SAnsuel Smith case 1: 1357272833b9SAnsuel Smith /* For 100M waveform */ 135867999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1359272833b9SAnsuel Smith /* Turn on Gigabit clock */ 136067999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1361272833b9SAnsuel Smith break; 1362272833b9SAnsuel Smith 1363272833b9SAnsuel Smith case 2: 1364272833b9SAnsuel Smith phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1365272833b9SAnsuel Smith fallthrough; 1366272833b9SAnsuel Smith case 4: 1367272833b9SAnsuel Smith phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 136867999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 136967999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1370272833b9SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1371272833b9SAnsuel Smith break; 1372272833b9SAnsuel Smith } 1373272833b9SAnsuel Smith 13741ca83119SAnsuel Smith /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 13751ca83119SAnsuel Smith * Disable on init and enable only with 100m speed following 13761ca83119SAnsuel Smith * qca original source code. 13771ca83119SAnsuel Smith */ 13781ca83119SAnsuel Smith if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 13791ca83119SAnsuel Smith phydev->drv->phy_id == QCA8327_B_PHY_ID) 138067999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 13811ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 0); 13821ca83119SAnsuel Smith 13839d1c29b4SAnsuel Smith /* Following original QCA sourcecode set port to prefer master */ 13849d1c29b4SAnsuel Smith phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 13859d1c29b4SAnsuel Smith 1386272833b9SAnsuel Smith return 0; 1387272833b9SAnsuel Smith } 1388272833b9SAnsuel Smith 13891ca83119SAnsuel Smith static void qca83xx_link_change_notify(struct phy_device *phydev) 13901ca83119SAnsuel Smith { 13911ca83119SAnsuel Smith /* QCA8337 doesn't require DAC Amplitude adjustement */ 13921ca83119SAnsuel Smith if (phydev->drv->phy_id == QCA8337_PHY_ID) 13931ca83119SAnsuel Smith return; 13941ca83119SAnsuel Smith 13951ca83119SAnsuel Smith /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 13961ca83119SAnsuel Smith if (phydev->state == PHY_RUNNING) { 13971ca83119SAnsuel Smith if (phydev->speed == SPEED_100) 139867999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 13991ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 14001ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN); 14011ca83119SAnsuel Smith } else { 14021ca83119SAnsuel Smith /* Reset DAC Amplitude adjustment */ 140367999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 14041ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 0); 14051ca83119SAnsuel Smith } 14061ca83119SAnsuel Smith } 14071ca83119SAnsuel Smith 1408ba3c01eeSAnsuel Smith static int qca83xx_resume(struct phy_device *phydev) 1409ba3c01eeSAnsuel Smith { 1410ba3c01eeSAnsuel Smith int ret, val; 1411ba3c01eeSAnsuel Smith 1412ba3c01eeSAnsuel Smith /* Skip reset if not suspended */ 1413ba3c01eeSAnsuel Smith if (!phydev->suspended) 1414ba3c01eeSAnsuel Smith return 0; 1415ba3c01eeSAnsuel Smith 1416ba3c01eeSAnsuel Smith /* Reinit the port, reset values set by suspend */ 1417ba3c01eeSAnsuel Smith qca83xx_config_init(phydev); 1418ba3c01eeSAnsuel Smith 1419ba3c01eeSAnsuel Smith /* Reset the port on port resume */ 1420ba3c01eeSAnsuel Smith phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1421ba3c01eeSAnsuel Smith 1422ba3c01eeSAnsuel Smith /* On resume from suspend the switch execute a reset and 1423ba3c01eeSAnsuel Smith * restart auto-negotiation. Wait for reset to complete. 1424ba3c01eeSAnsuel Smith */ 1425ba3c01eeSAnsuel Smith ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1426ba3c01eeSAnsuel Smith 50000, 600000, true); 1427ba3c01eeSAnsuel Smith if (ret) 1428ba3c01eeSAnsuel Smith return ret; 1429ba3c01eeSAnsuel Smith 1430ba3c01eeSAnsuel Smith msleep(1); 1431ba3c01eeSAnsuel Smith 1432ba3c01eeSAnsuel Smith return 0; 1433ba3c01eeSAnsuel Smith } 1434ba3c01eeSAnsuel Smith 1435ba3c01eeSAnsuel Smith static int qca83xx_suspend(struct phy_device *phydev) 1436ba3c01eeSAnsuel Smith { 1437ba3c01eeSAnsuel Smith u16 mask = 0; 1438ba3c01eeSAnsuel Smith 1439ba3c01eeSAnsuel Smith /* Only QCA8337 support actual suspend. 1440ba3c01eeSAnsuel Smith * QCA8327 cause port unreliability when phy suspend 1441ba3c01eeSAnsuel Smith * is set. 1442ba3c01eeSAnsuel Smith */ 1443ba3c01eeSAnsuel Smith if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1444ba3c01eeSAnsuel Smith genphy_suspend(phydev); 1445ba3c01eeSAnsuel Smith } else { 1446ba3c01eeSAnsuel Smith mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1447ba3c01eeSAnsuel Smith phy_modify(phydev, MII_BMCR, mask, 0); 1448ba3c01eeSAnsuel Smith } 1449ba3c01eeSAnsuel Smith 145067999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1451ba3c01eeSAnsuel Smith AT803X_DEBUG_GATE_CLK_IN1000, 0); 1452ba3c01eeSAnsuel Smith 1453ba3c01eeSAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1454ba3c01eeSAnsuel Smith AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1455ba3c01eeSAnsuel Smith AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1456ba3c01eeSAnsuel Smith 1457ba3c01eeSAnsuel Smith return 0; 1458ba3c01eeSAnsuel Smith } 1459ba3c01eeSAnsuel Smith 1460*79c7bc05SLuo Jie static int qca808x_read_status(struct phy_device *phydev) 1461*79c7bc05SLuo Jie { 1462*79c7bc05SLuo Jie int ret; 1463*79c7bc05SLuo Jie 1464*79c7bc05SLuo Jie ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 1465*79c7bc05SLuo Jie if (ret < 0) 1466*79c7bc05SLuo Jie return ret; 1467*79c7bc05SLuo Jie 1468*79c7bc05SLuo Jie linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 1469*79c7bc05SLuo Jie ret & MDIO_AN_10GBT_STAT_LP2_5G); 1470*79c7bc05SLuo Jie 1471*79c7bc05SLuo Jie ret = genphy_read_status(phydev); 1472*79c7bc05SLuo Jie if (ret) 1473*79c7bc05SLuo Jie return ret; 1474*79c7bc05SLuo Jie 1475*79c7bc05SLuo Jie ret = at803x_read_specific_status(phydev); 1476*79c7bc05SLuo Jie if (ret < 0) 1477*79c7bc05SLuo Jie return ret; 1478*79c7bc05SLuo Jie 1479*79c7bc05SLuo Jie if (phydev->link && phydev->speed == SPEED_2500) 1480*79c7bc05SLuo Jie phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 1481*79c7bc05SLuo Jie else 1482*79c7bc05SLuo Jie phydev->interface = PHY_INTERFACE_MODE_SMII; 1483*79c7bc05SLuo Jie 1484*79c7bc05SLuo Jie return 0; 1485*79c7bc05SLuo Jie } 1486*79c7bc05SLuo Jie 1487317420abSMugunthan V N static struct phy_driver at803x_driver[] = { 1488317420abSMugunthan V N { 148996c36712SMichael Walle /* Qualcomm Atheros AR8035 */ 14900465d8f8SMichael Walle PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 149196c36712SMichael Walle .name = "Qualcomm Atheros AR8035", 14926cb75767SMichael Walle .flags = PHY_POLL_CABLE_TEST, 14932f664823SMichael Walle .probe = at803x_probe, 14942318ca8aSMichael Walle .remove = at803x_remove, 14957dce80c2SOleksij Rempel .config_aneg = at803x_config_aneg, 14960ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 1497cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 1498ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 1499ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 15006229ed1fSDaniel Mack .suspend = at803x_suspend, 15016229ed1fSDaniel Mack .resume = at803x_resume, 1502dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 150306d5f344SRussell King .read_status = at803x_read_status, 15040eae5982SMåns Rullgård .config_intr = at803x_config_intr, 150529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 1506cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 1507cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 15086cb75767SMichael Walle .cable_test_start = at803x_cable_test_start, 15096cb75767SMichael Walle .cable_test_get_status = at803x_cable_test_get_status, 1510317420abSMugunthan V N }, { 151196c36712SMichael Walle /* Qualcomm Atheros AR8030 */ 1512bd8ca17fSDaniel Mack .phy_id = ATH8030_PHY_ID, 151396c36712SMichael Walle .name = "Qualcomm Atheros AR8030", 15140465d8f8SMichael Walle .phy_id_mask = AT8030_PHY_ID_MASK, 15152f664823SMichael Walle .probe = at803x_probe, 15162318ca8aSMichael Walle .remove = at803x_remove, 15170ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 151813a56b44SDaniel Mack .link_change_notify = at803x_link_change_notify, 1519ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 1520ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 15216229ed1fSDaniel Mack .suspend = at803x_suspend, 15226229ed1fSDaniel Mack .resume = at803x_resume, 1523dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 15240eae5982SMåns Rullgård .config_intr = at803x_config_intr, 152529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 152605d7cce8SMugunthan V N }, { 152796c36712SMichael Walle /* Qualcomm Atheros AR8031/AR8033 */ 15280465d8f8SMichael Walle PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 152996c36712SMichael Walle .name = "Qualcomm Atheros AR8031/AR8033", 15306cb75767SMichael Walle .flags = PHY_POLL_CABLE_TEST, 15312f664823SMichael Walle .probe = at803x_probe, 15322318ca8aSMichael Walle .remove = at803x_remove, 153305d7cce8SMugunthan V N .config_init = at803x_config_init, 153463477a5dSMichael Walle .config_aneg = at803x_config_aneg, 1535cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 153605d7cce8SMugunthan V N .set_wol = at803x_set_wol, 153705d7cce8SMugunthan V N .get_wol = at803x_get_wol, 15386229ed1fSDaniel Mack .suspend = at803x_suspend, 15396229ed1fSDaniel Mack .resume = at803x_resume, 1540c329e5afSDavid Bauer .read_page = at803x_read_page, 1541c329e5afSDavid Bauer .write_page = at803x_write_page, 1542b856150cSDavid Bauer .get_features = at803x_get_features, 154306d5f344SRussell King .read_status = at803x_read_status, 154477a99394SZhao Qiang .config_intr = &at803x_config_intr, 154529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 1546cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 1547cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 15486cb75767SMichael Walle .cable_test_start = at803x_cable_test_start, 15496cb75767SMichael Walle .cable_test_get_status = at803x_cable_test_get_status, 15507908d2ceSOleksij Rempel }, { 15515800091aSDavid Bauer /* Qualcomm Atheros AR8032 */ 15525800091aSDavid Bauer PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 15535800091aSDavid Bauer .name = "Qualcomm Atheros AR8032", 15545800091aSDavid Bauer .probe = at803x_probe, 15555800091aSDavid Bauer .remove = at803x_remove, 1556dc0f3ed1SOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 15575800091aSDavid Bauer .config_init = at803x_config_init, 15585800091aSDavid Bauer .link_change_notify = at803x_link_change_notify, 15595800091aSDavid Bauer .set_wol = at803x_set_wol, 15605800091aSDavid Bauer .get_wol = at803x_get_wol, 15615800091aSDavid Bauer .suspend = at803x_suspend, 15625800091aSDavid Bauer .resume = at803x_resume, 15635800091aSDavid Bauer /* PHY_BASIC_FEATURES */ 15645800091aSDavid Bauer .config_intr = at803x_config_intr, 156529773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 1566dc0f3ed1SOleksij Rempel .cable_test_start = at803x_cable_test_start, 1567dc0f3ed1SOleksij Rempel .cable_test_get_status = at803x_cable_test_get_status, 15685800091aSDavid Bauer }, { 15697908d2ceSOleksij Rempel /* ATHEROS AR9331 */ 15707908d2ceSOleksij Rempel PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 157196c36712SMichael Walle .name = "Qualcomm Atheros AR9331 built-in PHY", 15727908d2ceSOleksij Rempel .suspend = at803x_suspend, 15737908d2ceSOleksij Rempel .resume = at803x_resume, 1574dc0f3ed1SOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 15757908d2ceSOleksij Rempel /* PHY_BASIC_FEATURES */ 15767908d2ceSOleksij Rempel .config_intr = &at803x_config_intr, 157729773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 1578dc0f3ed1SOleksij Rempel .cable_test_start = at803x_cable_test_start, 1579dc0f3ed1SOleksij Rempel .cable_test_get_status = at803x_cable_test_get_status, 15807dce80c2SOleksij Rempel .read_status = at803x_read_status, 15817dce80c2SOleksij Rempel .soft_reset = genphy_soft_reset, 15827dce80c2SOleksij Rempel .config_aneg = at803x_config_aneg, 1583272833b9SAnsuel Smith }, { 1584fada2ce0SDavid Bauer /* Qualcomm Atheros QCA9561 */ 1585fada2ce0SDavid Bauer PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 1586fada2ce0SDavid Bauer .name = "Qualcomm Atheros QCA9561 built-in PHY", 1587fada2ce0SDavid Bauer .suspend = at803x_suspend, 1588fada2ce0SDavid Bauer .resume = at803x_resume, 1589fada2ce0SDavid Bauer .flags = PHY_POLL_CABLE_TEST, 1590fada2ce0SDavid Bauer /* PHY_BASIC_FEATURES */ 1591fada2ce0SDavid Bauer .config_intr = &at803x_config_intr, 1592fada2ce0SDavid Bauer .handle_interrupt = at803x_handle_interrupt, 1593fada2ce0SDavid Bauer .cable_test_start = at803x_cable_test_start, 1594fada2ce0SDavid Bauer .cable_test_get_status = at803x_cable_test_get_status, 1595fada2ce0SDavid Bauer .read_status = at803x_read_status, 1596fada2ce0SDavid Bauer .soft_reset = genphy_soft_reset, 1597fada2ce0SDavid Bauer .config_aneg = at803x_config_aneg, 1598fada2ce0SDavid Bauer }, { 1599272833b9SAnsuel Smith /* QCA8337 */ 1600272833b9SAnsuel Smith .phy_id = QCA8337_PHY_ID, 1601272833b9SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 1602d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8337 internal PHY", 1603272833b9SAnsuel Smith /* PHY_GBIT_FEATURES */ 16041ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 1605272833b9SAnsuel Smith .probe = at803x_probe, 1606272833b9SAnsuel Smith .flags = PHY_IS_INTERNAL, 1607272833b9SAnsuel Smith .config_init = qca83xx_config_init, 1608272833b9SAnsuel Smith .soft_reset = genphy_soft_reset, 1609272833b9SAnsuel Smith .get_sset_count = at803x_get_sset_count, 1610272833b9SAnsuel Smith .get_strings = at803x_get_strings, 1611272833b9SAnsuel Smith .get_stats = at803x_get_stats, 1612ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 1613ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 16140ccf8511SAnsuel Smith }, { 1615b4df02b5SAnsuel Smith /* QCA8327-A from switch QCA8327-AL1A */ 1616b4df02b5SAnsuel Smith .phy_id = QCA8327_A_PHY_ID, 16170ccf8511SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 1618d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8327-A internal PHY", 1619b4df02b5SAnsuel Smith /* PHY_GBIT_FEATURES */ 16201ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 1621b4df02b5SAnsuel Smith .probe = at803x_probe, 1622b4df02b5SAnsuel Smith .flags = PHY_IS_INTERNAL, 1623b4df02b5SAnsuel Smith .config_init = qca83xx_config_init, 1624b4df02b5SAnsuel Smith .soft_reset = genphy_soft_reset, 1625b4df02b5SAnsuel Smith .get_sset_count = at803x_get_sset_count, 1626b4df02b5SAnsuel Smith .get_strings = at803x_get_strings, 1627b4df02b5SAnsuel Smith .get_stats = at803x_get_stats, 1628ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 1629ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 1630b4df02b5SAnsuel Smith }, { 1631b4df02b5SAnsuel Smith /* QCA8327-B from switch QCA8327-BL1A */ 1632b4df02b5SAnsuel Smith .phy_id = QCA8327_B_PHY_ID, 1633b4df02b5SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 1634d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8327-B internal PHY", 16350ccf8511SAnsuel Smith /* PHY_GBIT_FEATURES */ 16361ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 16370ccf8511SAnsuel Smith .probe = at803x_probe, 16380ccf8511SAnsuel Smith .flags = PHY_IS_INTERNAL, 16390ccf8511SAnsuel Smith .config_init = qca83xx_config_init, 16400ccf8511SAnsuel Smith .soft_reset = genphy_soft_reset, 16410ccf8511SAnsuel Smith .get_sset_count = at803x_get_sset_count, 16420ccf8511SAnsuel Smith .get_strings = at803x_get_strings, 16430ccf8511SAnsuel Smith .get_stats = at803x_get_stats, 1644ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 1645ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 1646daf61732SLuo Jie }, { 1647daf61732SLuo Jie /* Qualcomm QCA8081 */ 1648daf61732SLuo Jie PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 1649daf61732SLuo Jie .name = "Qualcomm QCA8081", 1650daf61732SLuo Jie .config_intr = at803x_config_intr, 1651daf61732SLuo Jie .handle_interrupt = at803x_handle_interrupt, 1652daf61732SLuo Jie .get_tunable = at803x_get_tunable, 1653daf61732SLuo Jie .set_tunable = at803x_set_tunable, 1654daf61732SLuo Jie .set_wol = at803x_set_wol, 1655daf61732SLuo Jie .get_wol = at803x_get_wol, 1656daf61732SLuo Jie .suspend = genphy_suspend, 1657daf61732SLuo Jie .resume = genphy_resume, 1658*79c7bc05SLuo Jie .read_status = qca808x_read_status, 1659272833b9SAnsuel Smith }, }; 16600ca7111aSMatus Ujhelyi 166150fd7150SJohan Hovold module_phy_driver(at803x_driver); 16620ca7111aSMatus Ujhelyi 16630ca7111aSMatus Ujhelyi static struct mdio_device_id __maybe_unused atheros_tbl[] = { 16640465d8f8SMichael Walle { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 16650465d8f8SMichael Walle { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 16665800091aSDavid Bauer { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 16670465d8f8SMichael Walle { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 16687908d2ceSOleksij Rempel { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 16690ccf8511SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 1670b4df02b5SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 1671b4df02b5SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 1672fada2ce0SDavid Bauer { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 1673daf61732SLuo Jie { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 16740ca7111aSMatus Ujhelyi { } 16750ca7111aSMatus Ujhelyi }; 16760ca7111aSMatus Ujhelyi 16770ca7111aSMatus Ujhelyi MODULE_DEVICE_TABLE(mdio, atheros_tbl); 1678