1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+ 20ca7111aSMatus Ujhelyi /* 30ca7111aSMatus Ujhelyi * drivers/net/phy/at803x.c 40ca7111aSMatus Ujhelyi * 596c36712SMichael Walle * Driver for Qualcomm Atheros AR803x PHY 60ca7111aSMatus Ujhelyi * 70ca7111aSMatus Ujhelyi * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 80ca7111aSMatus Ujhelyi */ 90ca7111aSMatus Ujhelyi 100ca7111aSMatus Ujhelyi #include <linux/phy.h> 110ca7111aSMatus Ujhelyi #include <linux/module.h> 120ca7111aSMatus Ujhelyi #include <linux/string.h> 130ca7111aSMatus Ujhelyi #include <linux/netdevice.h> 140ca7111aSMatus Ujhelyi #include <linux/etherdevice.h> 156cb75767SMichael Walle #include <linux/ethtool_netlink.h> 1613a56b44SDaniel Mack #include <linux/of_gpio.h> 172f664823SMichael Walle #include <linux/bitfield.h> 1813a56b44SDaniel Mack #include <linux/gpio/consumer.h> 192f664823SMichael Walle #include <linux/regulator/of_regulator.h> 202f664823SMichael Walle #include <linux/regulator/driver.h> 212f664823SMichael Walle #include <linux/regulator/consumer.h> 222f664823SMichael Walle #include <dt-bindings/net/qca-ar803x.h> 230ca7111aSMatus Ujhelyi 247dce80c2SOleksij Rempel #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 257dce80c2SOleksij Rempel #define AT803X_SFC_ASSERT_CRS BIT(11) 267dce80c2SOleksij Rempel #define AT803X_SFC_FORCE_LINK BIT(10) 277dce80c2SOleksij Rempel #define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5) 287dce80c2SOleksij Rempel #define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3 297dce80c2SOleksij Rempel #define AT803X_SFC_MANUAL_MDIX 0x1 307dce80c2SOleksij Rempel #define AT803X_SFC_MANUAL_MDI 0x0 317dce80c2SOleksij Rempel #define AT803X_SFC_SQE_TEST BIT(2) 327dce80c2SOleksij Rempel #define AT803X_SFC_POLARITY_REVERSAL BIT(1) 337dce80c2SOleksij Rempel #define AT803X_SFC_DISABLE_JABBER BIT(0) 347dce80c2SOleksij Rempel 3506d5f344SRussell King #define AT803X_SPECIFIC_STATUS 0x11 369540cddaSLuo Jie #define AT803X_SS_SPEED_MASK GENMASK(15, 14) 379540cddaSLuo Jie #define AT803X_SS_SPEED_1000 2 389540cddaSLuo Jie #define AT803X_SS_SPEED_100 1 399540cddaSLuo Jie #define AT803X_SS_SPEED_10 0 4006d5f344SRussell King #define AT803X_SS_DUPLEX BIT(13) 4106d5f344SRussell King #define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11) 4206d5f344SRussell King #define AT803X_SS_MDIX BIT(6) 4306d5f344SRussell King 4479c7bc05SLuo Jie #define QCA808X_SS_SPEED_MASK GENMASK(9, 7) 4579c7bc05SLuo Jie #define QCA808X_SS_SPEED_2500 4 4679c7bc05SLuo Jie 470ca7111aSMatus Ujhelyi #define AT803X_INTR_ENABLE 0x12 48e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) 49e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14) 50e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) 51e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) 52e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) 53e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) 54*3265f421SRobert Hancock #define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) 55*3265f421SRobert Hancock #define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) 56e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) 57e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) 58e6e4a556SMartin Blumenstingl #define AT803X_INTR_ENABLE_WOL BIT(0) 59e6e4a556SMartin Blumenstingl 600ca7111aSMatus Ujhelyi #define AT803X_INTR_STATUS 0x13 61a46bd63bSMartin Blumenstingl 6213a56b44SDaniel Mack #define AT803X_SMART_SPEED 0x14 63cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_ENABLE BIT(5) 64cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2) 65cde0f4f8SMichael Walle #define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1) 666cb75767SMichael Walle #define AT803X_CDT 0x16 676cb75767SMichael Walle #define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8) 686cb75767SMichael Walle #define AT803X_CDT_ENABLE_TEST BIT(0) 696cb75767SMichael Walle #define AT803X_CDT_STATUS 0x1c 706cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_NORMAL 0 716cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_SHORT 1 726cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_OPEN 2 736cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_FAIL 3 746cb75767SMichael Walle #define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8) 756cb75767SMichael Walle #define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0) 7613a56b44SDaniel Mack #define AT803X_LED_CONTROL 0x18 77a46bd63bSMartin Blumenstingl 787beecaf7SLuo Jie #define AT803X_PHY_MMD3_WOL_CTRL 0x8012 797beecaf7SLuo Jie #define AT803X_WOL_EN BIT(5) 800ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 810ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 820ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 83f62265b5SZefir Kurtisi #define AT803X_REG_CHIP_CONFIG 0x1f 84f62265b5SZefir Kurtisi #define AT803X_BT_BX_REG_SEL 0x8000 85a46bd63bSMartin Blumenstingl 861ca6d1b1SMugunthan V N #define AT803X_DEBUG_ADDR 0x1D 871ca6d1b1SMugunthan V N #define AT803X_DEBUG_DATA 0x1E 88a46bd63bSMartin Blumenstingl 89f62265b5SZefir Kurtisi #define AT803X_MODE_CFG_MASK 0x0F 90*3265f421SRobert Hancock #define AT803X_MODE_CFG_BASET_RGMII 0x00 91*3265f421SRobert Hancock #define AT803X_MODE_CFG_BASET_SGMII 0x01 92*3265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 93*3265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 94*3265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 95*3265f421SRobert Hancock #define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 96*3265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 97*3265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 98*3265f421SRobert Hancock #define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B 99*3265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E 100*3265f421SRobert Hancock #define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F 101f62265b5SZefir Kurtisi 102f62265b5SZefir Kurtisi #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ 103f62265b5SZefir Kurtisi #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 104f62265b5SZefir Kurtisi 10567999555SAnsuel Smith #define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 1061ca83119SAnsuel Smith #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) 1071ca83119SAnsuel Smith #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) 1082e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) 109a46bd63bSMartin Blumenstingl 11067999555SAnsuel Smith #define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 1112e5f9f28SMartin Blumenstingl #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) 1120ca7111aSMatus Ujhelyi 113ba3c01eeSAnsuel Smith #define AT803X_DEBUG_REG_HIB_CTRL 0x0b 114ba3c01eeSAnsuel Smith #define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) 115ba3c01eeSAnsuel Smith #define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) 116ba3c01eeSAnsuel Smith 117272833b9SAnsuel Smith #define AT803X_DEBUG_REG_3C 0x3C 118272833b9SAnsuel Smith 11967999555SAnsuel Smith #define AT803X_DEBUG_REG_GREEN 0x3D 120ba3c01eeSAnsuel Smith #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) 121272833b9SAnsuel Smith 1222f664823SMichael Walle #define AT803X_DEBUG_REG_1F 0x1F 1232f664823SMichael Walle #define AT803X_DEBUG_PLL_ON BIT(2) 1242f664823SMichael Walle #define AT803X_DEBUG_RGMII_1V8 BIT(3) 1252f664823SMichael Walle 126272833b9SAnsuel Smith #define MDIO_AZ_DEBUG 0x800D 127272833b9SAnsuel Smith 1282f664823SMichael Walle /* AT803x supports either the XTAL input pad, an internal PLL or the 1292f664823SMichael Walle * DSP as clock reference for the clock output pad. The XTAL reference 1302f664823SMichael Walle * is only used for 25 MHz output, all other frequencies need the PLL. 1312f664823SMichael Walle * The DSP as a clock reference is used in synchronous ethernet 1322f664823SMichael Walle * applications. 1332f664823SMichael Walle * 1342f664823SMichael Walle * By default the PLL is only enabled if there is a link. Otherwise 1352f664823SMichael Walle * the PHY will go into low power state and disabled the PLL. You can 1362f664823SMichael Walle * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always 1372f664823SMichael Walle * enabled. 1382f664823SMichael Walle */ 1392f664823SMichael Walle #define AT803X_MMD7_CLK25M 0x8016 1402f664823SMichael Walle #define AT803X_CLK_OUT_MASK GENMASK(4, 2) 1412f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_XTAL 0 1422f664823SMichael Walle #define AT803X_CLK_OUT_25MHZ_DSP 1 1432f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_PLL 2 1442f664823SMichael Walle #define AT803X_CLK_OUT_50MHZ_DSP 3 1452f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_PLL 4 1462f664823SMichael Walle #define AT803X_CLK_OUT_62_5MHZ_DSP 5 1472f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_PLL 6 1482f664823SMichael Walle #define AT803X_CLK_OUT_125MHZ_DSP 7 1492f664823SMichael Walle 150428061f7SMichael Walle /* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask 151428061f7SMichael Walle * but doesn't support choosing between XTAL/PLL and DSP. 1522f664823SMichael Walle */ 1532f664823SMichael Walle #define AT8035_CLK_OUT_MASK GENMASK(4, 3) 1542f664823SMichael Walle 1552f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7) 1562f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_FULL 0 1572f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_HALF 1 1582f664823SMichael Walle #define AT803X_CLK_OUT_STRENGTH_QUARTER 2 1592f664823SMichael Walle 160cde0f4f8SMichael Walle #define AT803X_DEFAULT_DOWNSHIFT 5 161cde0f4f8SMichael Walle #define AT803X_MIN_DOWNSHIFT 2 162cde0f4f8SMichael Walle #define AT803X_MAX_DOWNSHIFT 9 163cde0f4f8SMichael Walle 164390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL1 0x805b 165390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL2 0x805c 166390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL3 0x805d 167390b4cadSRussell King #define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8) 168390b4cadSRussell King 1697908d2ceSOleksij Rempel #define ATH9331_PHY_ID 0x004dd041 170bd8ca17fSDaniel Mack #define ATH8030_PHY_ID 0x004dd076 171bd8ca17fSDaniel Mack #define ATH8031_PHY_ID 0x004dd074 1725800091aSDavid Bauer #define ATH8032_PHY_ID 0x004dd023 173bd8ca17fSDaniel Mack #define ATH8035_PHY_ID 0x004dd072 1740465d8f8SMichael Walle #define AT8030_PHY_ID_MASK 0xffffffef 175bd8ca17fSDaniel Mack 176daf61732SLuo Jie #define QCA8081_PHY_ID 0x004dd101 177daf61732SLuo Jie 178b4df02b5SAnsuel Smith #define QCA8327_A_PHY_ID 0x004dd033 179b4df02b5SAnsuel Smith #define QCA8327_B_PHY_ID 0x004dd034 180272833b9SAnsuel Smith #define QCA8337_PHY_ID 0x004dd036 181fada2ce0SDavid Bauer #define QCA9561_PHY_ID 0x004dd042 182272833b9SAnsuel Smith #define QCA8K_PHY_ID_MASK 0xffffffff 183272833b9SAnsuel Smith 184272833b9SAnsuel Smith #define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) 185272833b9SAnsuel Smith 186c329e5afSDavid Bauer #define AT803X_PAGE_FIBER 0 187c329e5afSDavid Bauer #define AT803X_PAGE_COPPER 1 188c329e5afSDavid Bauer 189d0e13fd5SAnsuel Smith /* don't turn off internal PLL */ 190d0e13fd5SAnsuel Smith #define AT803X_KEEP_PLL_ENABLED BIT(0) 191d0e13fd5SAnsuel Smith #define AT803X_DISABLE_SMARTEEE BIT(1) 192d0e13fd5SAnsuel Smith 1932acdd43fSLuo Jie /* ADC threshold */ 1942acdd43fSLuo Jie #define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80 1952acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0) 1962acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_80MV 0 1972acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_100MV 0xf0 1982acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_200MV 0x0f 1992acdd43fSLuo Jie #define QCA808X_ADC_THRESHOLD_300MV 0xff 2002acdd43fSLuo Jie 2012acdd43fSLuo Jie /* CLD control */ 2022acdd43fSLuo Jie #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007 2032acdd43fSLuo Jie #define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4) 2042acdd43fSLuo Jie #define QCA808X_8023AZ_AFE_EN 0x90 2052acdd43fSLuo Jie 2062acdd43fSLuo Jie /* AZ control */ 2072acdd43fSLuo Jie #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008 2082acdd43fSLuo Jie #define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32 2092acdd43fSLuo Jie 2102acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014 2112acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529 2122acdd43fSLuo Jie 2132acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E 2142acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341 2152acdd43fSLuo Jie 2162acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E 2172acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419 2182acdd43fSLuo Jie 2192acdd43fSLuo Jie #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020 2202acdd43fSLuo Jie #define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341 2212acdd43fSLuo Jie 2222acdd43fSLuo Jie #define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c 2232acdd43fSLuo Jie #define QCA808X_TOP_OPTION1_DATA 0x0 2242acdd43fSLuo Jie 2252acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_1 0xa100 2262acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_1_VALUE 0x9203 2272acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_2 0xa101 2282acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad 2292acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_3 0xa103 2302acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_3_VALUE 0x1698 2312acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_4 0xa105 2322acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_4_VALUE 0x8001 2332acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_5 0xa106 2342acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_5_VALUE 0x1111 2352acdd43fSLuo Jie #define QCA808X_PHY_MMD3_DEBUG_6 0xa011 2362acdd43fSLuo Jie #define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85 2372acdd43fSLuo Jie 2389d4dae29SLuo Jie /* master/slave seed config */ 2399d4dae29SLuo Jie #define QCA808X_PHY_DEBUG_LOCAL_SEED 9 2409d4dae29SLuo Jie #define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1) 2419d4dae29SLuo Jie #define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2) 2429d4dae29SLuo Jie #define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32 2439d4dae29SLuo Jie 2448c84d752SLuo Jie /* Hibernation yields lower power consumpiton in contrast with normal operation mode. 2458c84d752SLuo Jie * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s. 2468c84d752SLuo Jie */ 2478c84d752SLuo Jie #define QCA808X_DBG_AN_TEST 0xb 2488c84d752SLuo Jie #define QCA808X_HIBERNATION_EN BIT(15) 2498c84d752SLuo Jie 2508c84d752SLuo Jie #define QCA808X_CDT_ENABLE_TEST BIT(15) 2518c84d752SLuo Jie #define QCA808X_CDT_INTER_CHECK_DIS BIT(13) 2528c84d752SLuo Jie #define QCA808X_CDT_LENGTH_UNIT BIT(10) 2538c84d752SLuo Jie 2548c84d752SLuo Jie #define QCA808X_MMD3_CDT_STATUS 0x8064 2558c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065 2568c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066 2578c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067 2588c84d752SLuo Jie #define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068 2598c84d752SLuo Jie #define QCA808X_CDT_DIAG_LENGTH GENMASK(7, 0) 2608c84d752SLuo Jie 2618c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12) 2628c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8) 2638c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4) 2648c84d752SLuo Jie #define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0) 2658c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_FAIL 0 2668c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_NORMAL 1 2678c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_OPEN 2 2688c84d752SLuo Jie #define QCA808X_CDT_STATUS_STAT_SHORT 3 2698c84d752SLuo Jie 270daf61732SLuo Jie MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); 2710ca7111aSMatus Ujhelyi MODULE_AUTHOR("Matus Ujhelyi"); 2720ca7111aSMatus Ujhelyi MODULE_LICENSE("GPL"); 2730ca7111aSMatus Ujhelyi 274272833b9SAnsuel Smith enum stat_access_type { 275272833b9SAnsuel Smith PHY, 276272833b9SAnsuel Smith MMD 277272833b9SAnsuel Smith }; 278272833b9SAnsuel Smith 279272833b9SAnsuel Smith struct at803x_hw_stat { 280272833b9SAnsuel Smith const char *string; 281272833b9SAnsuel Smith u8 reg; 282272833b9SAnsuel Smith u32 mask; 283272833b9SAnsuel Smith enum stat_access_type access_type; 284272833b9SAnsuel Smith }; 285272833b9SAnsuel Smith 286272833b9SAnsuel Smith static struct at803x_hw_stat at803x_hw_stats[] = { 287272833b9SAnsuel Smith { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, 288272833b9SAnsuel Smith { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, 289272833b9SAnsuel Smith { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, 290272833b9SAnsuel Smith }; 291272833b9SAnsuel Smith 2922f664823SMichael Walle struct at803x_priv { 2932f664823SMichael Walle int flags; 2942f664823SMichael Walle u16 clk_25m_reg; 2952f664823SMichael Walle u16 clk_25m_mask; 296390b4cadSRussell King u8 smarteee_lpi_tw_1g; 297390b4cadSRussell King u8 smarteee_lpi_tw_100m; 298*3265f421SRobert Hancock bool is_fiber; 299*3265f421SRobert Hancock bool is_1000basex; 3002f664823SMichael Walle struct regulator_dev *vddio_rdev; 3012f664823SMichael Walle struct regulator_dev *vddh_rdev; 3022f664823SMichael Walle struct regulator *vddio; 303272833b9SAnsuel Smith u64 stats[ARRAY_SIZE(at803x_hw_stats)]; 3042f664823SMichael Walle }; 3052f664823SMichael Walle 30613a56b44SDaniel Mack struct at803x_context { 30713a56b44SDaniel Mack u16 bmcr; 30813a56b44SDaniel Mack u16 advertise; 30913a56b44SDaniel Mack u16 control1000; 31013a56b44SDaniel Mack u16 int_enable; 31113a56b44SDaniel Mack u16 smart_speed; 31213a56b44SDaniel Mack u16 led_control; 31313a56b44SDaniel Mack }; 31413a56b44SDaniel Mack 315272833b9SAnsuel Smith static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) 316272833b9SAnsuel Smith { 317272833b9SAnsuel Smith int ret; 318272833b9SAnsuel Smith 319272833b9SAnsuel Smith ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 320272833b9SAnsuel Smith if (ret < 0) 321272833b9SAnsuel Smith return ret; 322272833b9SAnsuel Smith 323272833b9SAnsuel Smith return phy_write(phydev, AT803X_DEBUG_DATA, data); 324272833b9SAnsuel Smith } 325272833b9SAnsuel Smith 3262e5f9f28SMartin Blumenstingl static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) 3272e5f9f28SMartin Blumenstingl { 3282e5f9f28SMartin Blumenstingl int ret; 3292e5f9f28SMartin Blumenstingl 3302e5f9f28SMartin Blumenstingl ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); 3312e5f9f28SMartin Blumenstingl if (ret < 0) 3322e5f9f28SMartin Blumenstingl return ret; 3332e5f9f28SMartin Blumenstingl 3342e5f9f28SMartin Blumenstingl return phy_read(phydev, AT803X_DEBUG_DATA); 3352e5f9f28SMartin Blumenstingl } 3362e5f9f28SMartin Blumenstingl 3372e5f9f28SMartin Blumenstingl static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg, 3382e5f9f28SMartin Blumenstingl u16 clear, u16 set) 3392e5f9f28SMartin Blumenstingl { 3402e5f9f28SMartin Blumenstingl u16 val; 3412e5f9f28SMartin Blumenstingl int ret; 3422e5f9f28SMartin Blumenstingl 3432e5f9f28SMartin Blumenstingl ret = at803x_debug_reg_read(phydev, reg); 3442e5f9f28SMartin Blumenstingl if (ret < 0) 3452e5f9f28SMartin Blumenstingl return ret; 3462e5f9f28SMartin Blumenstingl 3472e5f9f28SMartin Blumenstingl val = ret & 0xffff; 3482e5f9f28SMartin Blumenstingl val &= ~clear; 3492e5f9f28SMartin Blumenstingl val |= set; 3502e5f9f28SMartin Blumenstingl 3512e5f9f28SMartin Blumenstingl return phy_write(phydev, AT803X_DEBUG_DATA, val); 3522e5f9f28SMartin Blumenstingl } 3532e5f9f28SMartin Blumenstingl 354c329e5afSDavid Bauer static int at803x_write_page(struct phy_device *phydev, int page) 355c329e5afSDavid Bauer { 356c329e5afSDavid Bauer int mask; 357c329e5afSDavid Bauer int set; 358c329e5afSDavid Bauer 359c329e5afSDavid Bauer if (page == AT803X_PAGE_COPPER) { 360c329e5afSDavid Bauer set = AT803X_BT_BX_REG_SEL; 361c329e5afSDavid Bauer mask = 0; 362c329e5afSDavid Bauer } else { 363c329e5afSDavid Bauer set = 0; 364c329e5afSDavid Bauer mask = AT803X_BT_BX_REG_SEL; 365c329e5afSDavid Bauer } 366c329e5afSDavid Bauer 367c329e5afSDavid Bauer return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); 368c329e5afSDavid Bauer } 369c329e5afSDavid Bauer 370c329e5afSDavid Bauer static int at803x_read_page(struct phy_device *phydev) 371c329e5afSDavid Bauer { 372c329e5afSDavid Bauer int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); 373c329e5afSDavid Bauer 374c329e5afSDavid Bauer if (ccr < 0) 375c329e5afSDavid Bauer return ccr; 376c329e5afSDavid Bauer 377c329e5afSDavid Bauer if (ccr & AT803X_BT_BX_REG_SEL) 378c329e5afSDavid Bauer return AT803X_PAGE_COPPER; 379c329e5afSDavid Bauer 380c329e5afSDavid Bauer return AT803X_PAGE_FIBER; 381c329e5afSDavid Bauer } 382c329e5afSDavid Bauer 3836d4cd041SVinod Koul static int at803x_enable_rx_delay(struct phy_device *phydev) 3846d4cd041SVinod Koul { 38567999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, 3866d4cd041SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN); 3876d4cd041SVinod Koul } 3886d4cd041SVinod Koul 3896d4cd041SVinod Koul static int at803x_enable_tx_delay(struct phy_device *phydev) 3906d4cd041SVinod Koul { 39167999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, 3926d4cd041SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN); 3936d4cd041SVinod Koul } 3946d4cd041SVinod Koul 39543f2ebd5SVinod Koul static int at803x_disable_rx_delay(struct phy_device *phydev) 3962e5f9f28SMartin Blumenstingl { 39767999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 398cd28d1d6SVinod Koul AT803X_DEBUG_RX_CLK_DLY_EN, 0); 3992e5f9f28SMartin Blumenstingl } 4002e5f9f28SMartin Blumenstingl 40143f2ebd5SVinod Koul static int at803x_disable_tx_delay(struct phy_device *phydev) 4022e5f9f28SMartin Blumenstingl { 40367999555SAnsuel Smith return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 404cd28d1d6SVinod Koul AT803X_DEBUG_TX_CLK_DLY_EN, 0); 4052e5f9f28SMartin Blumenstingl } 4062e5f9f28SMartin Blumenstingl 40713a56b44SDaniel Mack /* save relevant PHY registers to private copy */ 40813a56b44SDaniel Mack static void at803x_context_save(struct phy_device *phydev, 40913a56b44SDaniel Mack struct at803x_context *context) 41013a56b44SDaniel Mack { 41113a56b44SDaniel Mack context->bmcr = phy_read(phydev, MII_BMCR); 41213a56b44SDaniel Mack context->advertise = phy_read(phydev, MII_ADVERTISE); 41313a56b44SDaniel Mack context->control1000 = phy_read(phydev, MII_CTRL1000); 41413a56b44SDaniel Mack context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); 41513a56b44SDaniel Mack context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); 41613a56b44SDaniel Mack context->led_control = phy_read(phydev, AT803X_LED_CONTROL); 41713a56b44SDaniel Mack } 41813a56b44SDaniel Mack 41913a56b44SDaniel Mack /* restore relevant PHY registers from private copy */ 42013a56b44SDaniel Mack static void at803x_context_restore(struct phy_device *phydev, 42113a56b44SDaniel Mack const struct at803x_context *context) 42213a56b44SDaniel Mack { 42313a56b44SDaniel Mack phy_write(phydev, MII_BMCR, context->bmcr); 42413a56b44SDaniel Mack phy_write(phydev, MII_ADVERTISE, context->advertise); 42513a56b44SDaniel Mack phy_write(phydev, MII_CTRL1000, context->control1000); 42613a56b44SDaniel Mack phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); 42713a56b44SDaniel Mack phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); 42813a56b44SDaniel Mack phy_write(phydev, AT803X_LED_CONTROL, context->led_control); 42913a56b44SDaniel Mack } 43013a56b44SDaniel Mack 431ea13c9eeSMugunthan V N static int at803x_set_wol(struct phy_device *phydev, 432ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 4330ca7111aSMatus Ujhelyi { 4340ca7111aSMatus Ujhelyi struct net_device *ndev = phydev->attached_dev; 4350ca7111aSMatus Ujhelyi const u8 *mac; 4367beecaf7SLuo Jie int ret, irq_enabled; 437c0f0b563SLuo Jie unsigned int i; 438edcb501eSColin Ian King static const unsigned int offsets[] = { 4390ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_32_47_OFFSET, 4400ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_16_31_OFFSET, 4410ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_0_15_OFFSET, 4420ca7111aSMatus Ujhelyi }; 4430ca7111aSMatus Ujhelyi 4440ca7111aSMatus Ujhelyi if (!ndev) 445ea13c9eeSMugunthan V N return -ENODEV; 4460ca7111aSMatus Ujhelyi 447ea13c9eeSMugunthan V N if (wol->wolopts & WAKE_MAGIC) { 4480ca7111aSMatus Ujhelyi mac = (const u8 *) ndev->dev_addr; 4490ca7111aSMatus Ujhelyi 4500ca7111aSMatus Ujhelyi if (!is_valid_ether_addr(mac)) 451fc755687SDan Murphy return -EINVAL; 4520ca7111aSMatus Ujhelyi 4530e021396SCarlo Caione for (i = 0; i < 3; i++) 454c0f0b563SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i], 4550ca7111aSMatus Ujhelyi mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 456ea13c9eeSMugunthan V N 4577beecaf7SLuo Jie /* Enable WOL function */ 4587beecaf7SLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 4597beecaf7SLuo Jie 0, AT803X_WOL_EN); 4607beecaf7SLuo Jie if (ret) 4617beecaf7SLuo Jie return ret; 4627beecaf7SLuo Jie /* Enable WOL interrupt */ 4632d4284e8SLuo Jie ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); 464ea13c9eeSMugunthan V N if (ret) 465ea13c9eeSMugunthan V N return ret; 466ea13c9eeSMugunthan V N } else { 4677beecaf7SLuo Jie /* Disable WoL function */ 4687beecaf7SLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL, 4697beecaf7SLuo Jie AT803X_WOL_EN, 0); 4707beecaf7SLuo Jie if (ret) 4717beecaf7SLuo Jie return ret; 4727beecaf7SLuo Jie /* Disable WOL interrupt */ 4732d4284e8SLuo Jie ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); 474ea13c9eeSMugunthan V N if (ret) 475ea13c9eeSMugunthan V N return ret; 476ea13c9eeSMugunthan V N } 477ea13c9eeSMugunthan V N 4787beecaf7SLuo Jie /* Clear WOL status */ 4797beecaf7SLuo Jie ret = phy_read(phydev, AT803X_INTR_STATUS); 4807beecaf7SLuo Jie if (ret < 0) 481ea13c9eeSMugunthan V N return ret; 4827beecaf7SLuo Jie 4837beecaf7SLuo Jie /* Check if there are other interrupts except for WOL triggered when PHY is 4847beecaf7SLuo Jie * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can 4857beecaf7SLuo Jie * be passed up to the interrupt PIN. 4867beecaf7SLuo Jie */ 4877beecaf7SLuo Jie irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 4887beecaf7SLuo Jie if (irq_enabled < 0) 4897beecaf7SLuo Jie return irq_enabled; 4907beecaf7SLuo Jie 4917beecaf7SLuo Jie irq_enabled &= ~AT803X_INTR_ENABLE_WOL; 4927beecaf7SLuo Jie if (ret & irq_enabled && !phy_polling_mode(phydev)) 4937beecaf7SLuo Jie phy_trigger_machine(phydev); 4947beecaf7SLuo Jie 4957beecaf7SLuo Jie return 0; 496ea13c9eeSMugunthan V N } 497ea13c9eeSMugunthan V N 498ea13c9eeSMugunthan V N static void at803x_get_wol(struct phy_device *phydev, 499ea13c9eeSMugunthan V N struct ethtool_wolinfo *wol) 500ea13c9eeSMugunthan V N { 501911e3a46SJiapeng Chong int value; 502ea13c9eeSMugunthan V N 503ea13c9eeSMugunthan V N wol->supported = WAKE_MAGIC; 504ea13c9eeSMugunthan V N wol->wolopts = 0; 505ea13c9eeSMugunthan V N 5067beecaf7SLuo Jie value = phy_read_mmd(phydev, MDIO_MMD_PCS, AT803X_PHY_MMD3_WOL_CTRL); 5077beecaf7SLuo Jie if (value < 0) 5087beecaf7SLuo Jie return; 5097beecaf7SLuo Jie 5107beecaf7SLuo Jie if (value & AT803X_WOL_EN) 511ea13c9eeSMugunthan V N wol->wolopts |= WAKE_MAGIC; 5120ca7111aSMatus Ujhelyi } 5130ca7111aSMatus Ujhelyi 514272833b9SAnsuel Smith static int at803x_get_sset_count(struct phy_device *phydev) 515272833b9SAnsuel Smith { 516272833b9SAnsuel Smith return ARRAY_SIZE(at803x_hw_stats); 517272833b9SAnsuel Smith } 518272833b9SAnsuel Smith 519272833b9SAnsuel Smith static void at803x_get_strings(struct phy_device *phydev, u8 *data) 520272833b9SAnsuel Smith { 521272833b9SAnsuel Smith int i; 522272833b9SAnsuel Smith 523272833b9SAnsuel Smith for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { 524272833b9SAnsuel Smith strscpy(data + i * ETH_GSTRING_LEN, 525272833b9SAnsuel Smith at803x_hw_stats[i].string, ETH_GSTRING_LEN); 526272833b9SAnsuel Smith } 527272833b9SAnsuel Smith } 528272833b9SAnsuel Smith 529272833b9SAnsuel Smith static u64 at803x_get_stat(struct phy_device *phydev, int i) 530272833b9SAnsuel Smith { 531272833b9SAnsuel Smith struct at803x_hw_stat stat = at803x_hw_stats[i]; 532272833b9SAnsuel Smith struct at803x_priv *priv = phydev->priv; 533272833b9SAnsuel Smith int val; 534272833b9SAnsuel Smith u64 ret; 535272833b9SAnsuel Smith 536272833b9SAnsuel Smith if (stat.access_type == MMD) 537272833b9SAnsuel Smith val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); 538272833b9SAnsuel Smith else 539272833b9SAnsuel Smith val = phy_read(phydev, stat.reg); 540272833b9SAnsuel Smith 541272833b9SAnsuel Smith if (val < 0) { 542272833b9SAnsuel Smith ret = U64_MAX; 543272833b9SAnsuel Smith } else { 544272833b9SAnsuel Smith val = val & stat.mask; 545272833b9SAnsuel Smith priv->stats[i] += val; 546272833b9SAnsuel Smith ret = priv->stats[i]; 547272833b9SAnsuel Smith } 548272833b9SAnsuel Smith 549272833b9SAnsuel Smith return ret; 550272833b9SAnsuel Smith } 551272833b9SAnsuel Smith 552272833b9SAnsuel Smith static void at803x_get_stats(struct phy_device *phydev, 553272833b9SAnsuel Smith struct ethtool_stats *stats, u64 *data) 554272833b9SAnsuel Smith { 555272833b9SAnsuel Smith int i; 556272833b9SAnsuel Smith 557272833b9SAnsuel Smith for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) 558272833b9SAnsuel Smith data[i] = at803x_get_stat(phydev, i); 559272833b9SAnsuel Smith } 560272833b9SAnsuel Smith 5616229ed1fSDaniel Mack static int at803x_suspend(struct phy_device *phydev) 5626229ed1fSDaniel Mack { 5636229ed1fSDaniel Mack int value; 5646229ed1fSDaniel Mack int wol_enabled; 5656229ed1fSDaniel Mack 5666229ed1fSDaniel Mack value = phy_read(phydev, AT803X_INTR_ENABLE); 567e6e4a556SMartin Blumenstingl wol_enabled = value & AT803X_INTR_ENABLE_WOL; 5686229ed1fSDaniel Mack 5696229ed1fSDaniel Mack if (wol_enabled) 570fea23fb5SRussell King value = BMCR_ISOLATE; 5716229ed1fSDaniel Mack else 572fea23fb5SRussell King value = BMCR_PDOWN; 5736229ed1fSDaniel Mack 574fea23fb5SRussell King phy_modify(phydev, MII_BMCR, 0, value); 5756229ed1fSDaniel Mack 5766229ed1fSDaniel Mack return 0; 5776229ed1fSDaniel Mack } 5786229ed1fSDaniel Mack 5796229ed1fSDaniel Mack static int at803x_resume(struct phy_device *phydev) 5806229ed1fSDaniel Mack { 581f102852fSRussell King return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); 5826229ed1fSDaniel Mack } 5836229ed1fSDaniel Mack 5842f664823SMichael Walle static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev, 5852f664823SMichael Walle unsigned int selector) 5862f664823SMichael Walle { 5872f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 5882f664823SMichael Walle 5892f664823SMichael Walle if (selector) 5902f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 5912f664823SMichael Walle 0, AT803X_DEBUG_RGMII_1V8); 5922f664823SMichael Walle else 5932f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 5942f664823SMichael Walle AT803X_DEBUG_RGMII_1V8, 0); 5952f664823SMichael Walle } 5962f664823SMichael Walle 5972f664823SMichael Walle static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev) 5982f664823SMichael Walle { 5992f664823SMichael Walle struct phy_device *phydev = rdev_get_drvdata(rdev); 6002f664823SMichael Walle int val; 6012f664823SMichael Walle 6022f664823SMichael Walle val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F); 6032f664823SMichael Walle if (val < 0) 6042f664823SMichael Walle return val; 6052f664823SMichael Walle 6062f664823SMichael Walle return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0; 6072f664823SMichael Walle } 6082f664823SMichael Walle 6093faaf539SRikard Falkeborn static const struct regulator_ops vddio_regulator_ops = { 6102f664823SMichael Walle .list_voltage = regulator_list_voltage_table, 6112f664823SMichael Walle .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel, 6122f664823SMichael Walle .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel, 6132f664823SMichael Walle }; 6142f664823SMichael Walle 6152f664823SMichael Walle static const unsigned int vddio_voltage_table[] = { 6162f664823SMichael Walle 1500000, 6172f664823SMichael Walle 1800000, 6182f664823SMichael Walle }; 6192f664823SMichael Walle 6202f664823SMichael Walle static const struct regulator_desc vddio_desc = { 6212f664823SMichael Walle .name = "vddio", 6222f664823SMichael Walle .of_match = of_match_ptr("vddio-regulator"), 6232f664823SMichael Walle .n_voltages = ARRAY_SIZE(vddio_voltage_table), 6242f664823SMichael Walle .volt_table = vddio_voltage_table, 6252f664823SMichael Walle .ops = &vddio_regulator_ops, 6262f664823SMichael Walle .type = REGULATOR_VOLTAGE, 6272f664823SMichael Walle .owner = THIS_MODULE, 6282f664823SMichael Walle }; 6292f664823SMichael Walle 6303faaf539SRikard Falkeborn static const struct regulator_ops vddh_regulator_ops = { 6312f664823SMichael Walle }; 6322f664823SMichael Walle 6332f664823SMichael Walle static const struct regulator_desc vddh_desc = { 6342f664823SMichael Walle .name = "vddh", 6352f664823SMichael Walle .of_match = of_match_ptr("vddh-regulator"), 6362f664823SMichael Walle .n_voltages = 1, 6372f664823SMichael Walle .fixed_uV = 2500000, 6382f664823SMichael Walle .ops = &vddh_regulator_ops, 6392f664823SMichael Walle .type = REGULATOR_VOLTAGE, 6402f664823SMichael Walle .owner = THIS_MODULE, 6412f664823SMichael Walle }; 6422f664823SMichael Walle 6432f664823SMichael Walle static int at8031_register_regulators(struct phy_device *phydev) 6442f664823SMichael Walle { 6452f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 6462f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 6472f664823SMichael Walle struct regulator_config config = { }; 6482f664823SMichael Walle 6492f664823SMichael Walle config.dev = dev; 6502f664823SMichael Walle config.driver_data = phydev; 6512f664823SMichael Walle 6522f664823SMichael Walle priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config); 6532f664823SMichael Walle if (IS_ERR(priv->vddio_rdev)) { 6542f664823SMichael Walle phydev_err(phydev, "failed to register VDDIO regulator\n"); 6552f664823SMichael Walle return PTR_ERR(priv->vddio_rdev); 6562f664823SMichael Walle } 6572f664823SMichael Walle 6582f664823SMichael Walle priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config); 6592f664823SMichael Walle if (IS_ERR(priv->vddh_rdev)) { 6602f664823SMichael Walle phydev_err(phydev, "failed to register VDDH regulator\n"); 6612f664823SMichael Walle return PTR_ERR(priv->vddh_rdev); 6622f664823SMichael Walle } 6632f664823SMichael Walle 6642f664823SMichael Walle return 0; 6652f664823SMichael Walle } 6662f664823SMichael Walle 6672f664823SMichael Walle static int at803x_parse_dt(struct phy_device *phydev) 6682f664823SMichael Walle { 6692f664823SMichael Walle struct device_node *node = phydev->mdio.dev.of_node; 6702f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 671390b4cadSRussell King u32 freq, strength, tw; 6723f2edd30SAndrew Lunn unsigned int sel; 6732f664823SMichael Walle int ret; 6742f664823SMichael Walle 6752f664823SMichael Walle if (!IS_ENABLED(CONFIG_OF_MDIO)) 6762f664823SMichael Walle return 0; 6772f664823SMichael Walle 678390b4cadSRussell King if (of_property_read_bool(node, "qca,disable-smarteee")) 679390b4cadSRussell King priv->flags |= AT803X_DISABLE_SMARTEEE; 680390b4cadSRussell King 681390b4cadSRussell King if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { 682390b4cadSRussell King if (!tw || tw > 255) { 683390b4cadSRussell King phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); 684390b4cadSRussell King return -EINVAL; 685390b4cadSRussell King } 686390b4cadSRussell King priv->smarteee_lpi_tw_1g = tw; 687390b4cadSRussell King } 688390b4cadSRussell King 689390b4cadSRussell King if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { 690390b4cadSRussell King if (!tw || tw > 255) { 691390b4cadSRussell King phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); 692390b4cadSRussell King return -EINVAL; 693390b4cadSRussell King } 694390b4cadSRussell King priv->smarteee_lpi_tw_100m = tw; 695390b4cadSRussell King } 696390b4cadSRussell King 6972f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq); 6982f664823SMichael Walle if (!ret) { 6992f664823SMichael Walle switch (freq) { 7002f664823SMichael Walle case 25000000: 7012f664823SMichael Walle sel = AT803X_CLK_OUT_25MHZ_XTAL; 7022f664823SMichael Walle break; 7032f664823SMichael Walle case 50000000: 7042f664823SMichael Walle sel = AT803X_CLK_OUT_50MHZ_PLL; 7052f664823SMichael Walle break; 7062f664823SMichael Walle case 62500000: 7072f664823SMichael Walle sel = AT803X_CLK_OUT_62_5MHZ_PLL; 7082f664823SMichael Walle break; 7092f664823SMichael Walle case 125000000: 7102f664823SMichael Walle sel = AT803X_CLK_OUT_125MHZ_PLL; 7112f664823SMichael Walle break; 7122f664823SMichael Walle default: 7132f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-frequency\n"); 7142f664823SMichael Walle return -EINVAL; 7152f664823SMichael Walle } 7162f664823SMichael Walle 7173f2edd30SAndrew Lunn priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel); 7183f2edd30SAndrew Lunn priv->clk_25m_mask |= AT803X_CLK_OUT_MASK; 7192f664823SMichael Walle 7202f664823SMichael Walle /* Fixup for the AR8030/AR8035. This chip has another mask and 7212f664823SMichael Walle * doesn't support the DSP reference. Eg. the lowest bit of the 7222f664823SMichael Walle * mask. The upper two bits select the same frequencies. Mask 7232f664823SMichael Walle * the lowest bit here. 7242f664823SMichael Walle * 7252f664823SMichael Walle * Warning: 7262f664823SMichael Walle * There was no datasheet for the AR8030 available so this is 7272f664823SMichael Walle * just a guess. But the AR8035 is listed as pin compatible 7282f664823SMichael Walle * to the AR8030 so there might be a good chance it works on 7292f664823SMichael Walle * the AR8030 too. 7302f664823SMichael Walle */ 7318887ca54SRussell King if (phydev->drv->phy_id == ATH8030_PHY_ID || 7328887ca54SRussell King phydev->drv->phy_id == ATH8035_PHY_ID) { 733b1f4c209SOleksij Rempel priv->clk_25m_reg &= AT8035_CLK_OUT_MASK; 734b1f4c209SOleksij Rempel priv->clk_25m_mask &= AT8035_CLK_OUT_MASK; 7352f664823SMichael Walle } 7362f664823SMichael Walle } 7372f664823SMichael Walle 7382f664823SMichael Walle ret = of_property_read_u32(node, "qca,clk-out-strength", &strength); 7392f664823SMichael Walle if (!ret) { 7402f664823SMichael Walle priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK; 7412f664823SMichael Walle switch (strength) { 7422f664823SMichael Walle case AR803X_STRENGTH_FULL: 7432f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL; 7442f664823SMichael Walle break; 7452f664823SMichael Walle case AR803X_STRENGTH_HALF: 7462f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF; 7472f664823SMichael Walle break; 7482f664823SMichael Walle case AR803X_STRENGTH_QUARTER: 7492f664823SMichael Walle priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER; 7502f664823SMichael Walle break; 7512f664823SMichael Walle default: 7522f664823SMichael Walle phydev_err(phydev, "invalid qca,clk-out-strength\n"); 7532f664823SMichael Walle return -EINVAL; 7542f664823SMichael Walle } 7552f664823SMichael Walle } 7562f664823SMichael Walle 757428061f7SMichael Walle /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping 758428061f7SMichael Walle * options. 759428061f7SMichael Walle */ 7608887ca54SRussell King if (phydev->drv->phy_id == ATH8031_PHY_ID) { 7612f664823SMichael Walle if (of_property_read_bool(node, "qca,keep-pll-enabled")) 7622f664823SMichael Walle priv->flags |= AT803X_KEEP_PLL_ENABLED; 7632f664823SMichael Walle 7642f664823SMichael Walle ret = at8031_register_regulators(phydev); 7652f664823SMichael Walle if (ret < 0) 7662f664823SMichael Walle return ret; 7672f664823SMichael Walle 7682f664823SMichael Walle priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev, 7692f664823SMichael Walle "vddio"); 7702f664823SMichael Walle if (IS_ERR(priv->vddio)) { 7712f664823SMichael Walle phydev_err(phydev, "failed to get VDDIO regulator\n"); 7722f664823SMichael Walle return PTR_ERR(priv->vddio); 7732f664823SMichael Walle } 7742f664823SMichael Walle } 7752f664823SMichael Walle 7762f664823SMichael Walle return 0; 7772f664823SMichael Walle } 7782f664823SMichael Walle 7792f664823SMichael Walle static int at803x_probe(struct phy_device *phydev) 7802f664823SMichael Walle { 7812f664823SMichael Walle struct device *dev = &phydev->mdio.dev; 7822f664823SMichael Walle struct at803x_priv *priv; 783c329e5afSDavid Bauer int ret; 7842f664823SMichael Walle 7852f664823SMichael Walle priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 7862f664823SMichael Walle if (!priv) 7872f664823SMichael Walle return -ENOMEM; 7882f664823SMichael Walle 7892f664823SMichael Walle phydev->priv = priv; 7902f664823SMichael Walle 791c329e5afSDavid Bauer ret = at803x_parse_dt(phydev); 792c329e5afSDavid Bauer if (ret) 793c329e5afSDavid Bauer return ret; 794c329e5afSDavid Bauer 7958f7e8762SMichael Walle if (priv->vddio) { 7968f7e8762SMichael Walle ret = regulator_enable(priv->vddio); 7978f7e8762SMichael Walle if (ret < 0) 7988f7e8762SMichael Walle return ret; 7998f7e8762SMichael Walle } 8008f7e8762SMichael Walle 801*3265f421SRobert Hancock if (phydev->drv->phy_id == ATH8031_PHY_ID) { 802*3265f421SRobert Hancock int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); 803*3265f421SRobert Hancock int mode_cfg; 804*3265f421SRobert Hancock 805*3265f421SRobert Hancock if (ccr < 0) 806*3265f421SRobert Hancock goto err; 807*3265f421SRobert Hancock mode_cfg = ccr & AT803X_MODE_CFG_MASK; 808*3265f421SRobert Hancock 809*3265f421SRobert Hancock switch (mode_cfg) { 810*3265f421SRobert Hancock case AT803X_MODE_CFG_BX1000_RGMII_50OHM: 811*3265f421SRobert Hancock case AT803X_MODE_CFG_BX1000_RGMII_75OHM: 812*3265f421SRobert Hancock priv->is_1000basex = true; 813*3265f421SRobert Hancock fallthrough; 814*3265f421SRobert Hancock case AT803X_MODE_CFG_FX100_RGMII_50OHM: 815*3265f421SRobert Hancock case AT803X_MODE_CFG_FX100_RGMII_75OHM: 816*3265f421SRobert Hancock priv->is_fiber = true; 817*3265f421SRobert Hancock break; 818*3265f421SRobert Hancock } 819*3265f421SRobert Hancock } 820*3265f421SRobert Hancock 8218f7e8762SMichael Walle return 0; 822*3265f421SRobert Hancock 823*3265f421SRobert Hancock err: 824*3265f421SRobert Hancock if (priv->vddio) 825*3265f421SRobert Hancock regulator_disable(priv->vddio); 826*3265f421SRobert Hancock 827*3265f421SRobert Hancock return ret; 8282f664823SMichael Walle } 8292f664823SMichael Walle 8302318ca8aSMichael Walle static void at803x_remove(struct phy_device *phydev) 8312318ca8aSMichael Walle { 8322318ca8aSMichael Walle struct at803x_priv *priv = phydev->priv; 8332318ca8aSMichael Walle 8342318ca8aSMichael Walle if (priv->vddio) 8352318ca8aSMichael Walle regulator_disable(priv->vddio); 8362318ca8aSMichael Walle } 8372318ca8aSMichael Walle 838b856150cSDavid Bauer static int at803x_get_features(struct phy_device *phydev) 839b856150cSDavid Bauer { 840*3265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 841b856150cSDavid Bauer int err; 842b856150cSDavid Bauer 843b856150cSDavid Bauer err = genphy_read_abilities(phydev); 844b856150cSDavid Bauer if (err) 845b856150cSDavid Bauer return err; 846b856150cSDavid Bauer 847765c22aaSLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) { 848765c22aaSLuo Jie err = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_NG_EXTABLE); 849765c22aaSLuo Jie if (err < 0) 850765c22aaSLuo Jie return err; 851765c22aaSLuo Jie 852765c22aaSLuo Jie linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported, 853765c22aaSLuo Jie err & MDIO_PMA_NG_EXTABLE_2_5GBT); 854765c22aaSLuo Jie } 855765c22aaSLuo Jie 856f5621a01SVladimir Oltean if (phydev->drv->phy_id != ATH8031_PHY_ID) 857b856150cSDavid Bauer return 0; 858b856150cSDavid Bauer 859b856150cSDavid Bauer /* AR8031/AR8033 have different status registers 860b856150cSDavid Bauer * for copper and fiber operation. However, the 861b856150cSDavid Bauer * extended status register is the same for both 862b856150cSDavid Bauer * operation modes. 863b856150cSDavid Bauer * 864b856150cSDavid Bauer * As a result of that, ESTATUS_1000_XFULL is set 865b856150cSDavid Bauer * to 1 even when operating in copper TP mode. 866b856150cSDavid Bauer * 867*3265f421SRobert Hancock * Remove this mode from the supported link modes 868*3265f421SRobert Hancock * when not operating in 1000BaseX mode. 869b856150cSDavid Bauer */ 870*3265f421SRobert Hancock if (!priv->is_1000basex) 871b856150cSDavid Bauer linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 872b856150cSDavid Bauer phydev->supported); 873*3265f421SRobert Hancock 874b856150cSDavid Bauer return 0; 875b856150cSDavid Bauer } 876b856150cSDavid Bauer 877390b4cadSRussell King static int at803x_smarteee_config(struct phy_device *phydev) 878390b4cadSRussell King { 879390b4cadSRussell King struct at803x_priv *priv = phydev->priv; 880390b4cadSRussell King u16 mask = 0, val = 0; 881390b4cadSRussell King int ret; 882390b4cadSRussell King 883390b4cadSRussell King if (priv->flags & AT803X_DISABLE_SMARTEEE) 884390b4cadSRussell King return phy_modify_mmd(phydev, MDIO_MMD_PCS, 885390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3, 886390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0); 887390b4cadSRussell King 888390b4cadSRussell King if (priv->smarteee_lpi_tw_1g) { 889390b4cadSRussell King mask |= 0xff00; 890390b4cadSRussell King val |= priv->smarteee_lpi_tw_1g << 8; 891390b4cadSRussell King } 892390b4cadSRussell King if (priv->smarteee_lpi_tw_100m) { 893390b4cadSRussell King mask |= 0x00ff; 894390b4cadSRussell King val |= priv->smarteee_lpi_tw_100m; 895390b4cadSRussell King } 896390b4cadSRussell King if (!mask) 897390b4cadSRussell King return 0; 898390b4cadSRussell King 899390b4cadSRussell King ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1, 900390b4cadSRussell King mask, val); 901390b4cadSRussell King if (ret) 902390b4cadSRussell King return ret; 903390b4cadSRussell King 904390b4cadSRussell King return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3, 905390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 906390b4cadSRussell King AT803X_MMD3_SMARTEEE_CTL3_LPI_EN); 907390b4cadSRussell King } 908390b4cadSRussell King 9092f664823SMichael Walle static int at803x_clk_out_config(struct phy_device *phydev) 9102f664823SMichael Walle { 9112f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 9122f664823SMichael Walle 9132f664823SMichael Walle if (!priv->clk_25m_mask) 9142f664823SMichael Walle return 0; 9152f664823SMichael Walle 916a45c1c10SRussell King return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, 917a45c1c10SRussell King priv->clk_25m_mask, priv->clk_25m_reg); 9182f664823SMichael Walle } 9192f664823SMichael Walle 9202f664823SMichael Walle static int at8031_pll_config(struct phy_device *phydev) 9212f664823SMichael Walle { 9222f664823SMichael Walle struct at803x_priv *priv = phydev->priv; 9232f664823SMichael Walle 9242f664823SMichael Walle /* The default after hardware reset is PLL OFF. After a soft reset, the 9252f664823SMichael Walle * values are retained. 9262f664823SMichael Walle */ 9272f664823SMichael Walle if (priv->flags & AT803X_KEEP_PLL_ENABLED) 9282f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 9292f664823SMichael Walle 0, AT803X_DEBUG_PLL_ON); 9302f664823SMichael Walle else 9312f664823SMichael Walle return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F, 9322f664823SMichael Walle AT803X_DEBUG_PLL_ON, 0); 9332f664823SMichael Walle } 9342f664823SMichael Walle 9350ca7111aSMatus Ujhelyi static int at803x_config_init(struct phy_device *phydev) 9360ca7111aSMatus Ujhelyi { 937*3265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 9381ca6d1b1SMugunthan V N int ret; 9390ca7111aSMatus Ujhelyi 9404f3a00c7SRobert Hancock if (phydev->drv->phy_id == ATH8031_PHY_ID) { 9414f3a00c7SRobert Hancock /* Some bootloaders leave the fiber page selected. 942*3265f421SRobert Hancock * Switch to the appropriate page (fiber or copper), as otherwise we 943*3265f421SRobert Hancock * read the PHY capabilities from the wrong page. 9444f3a00c7SRobert Hancock */ 9454f3a00c7SRobert Hancock phy_lock_mdio_bus(phydev); 946*3265f421SRobert Hancock ret = at803x_write_page(phydev, 947*3265f421SRobert Hancock priv->is_fiber ? AT803X_PAGE_FIBER : 948*3265f421SRobert Hancock AT803X_PAGE_COPPER); 9494f3a00c7SRobert Hancock phy_unlock_mdio_bus(phydev); 9504f3a00c7SRobert Hancock if (ret) 9514f3a00c7SRobert Hancock return ret; 9524f3a00c7SRobert Hancock 9534f3a00c7SRobert Hancock ret = at8031_pll_config(phydev); 9544f3a00c7SRobert Hancock if (ret < 0) 9554f3a00c7SRobert Hancock return ret; 9564f3a00c7SRobert Hancock } 9574f3a00c7SRobert Hancock 9586d4cd041SVinod Koul /* The RX and TX delay default is: 9596d4cd041SVinod Koul * after HW reset: RX delay enabled and TX delay disabled 9606d4cd041SVinod Koul * after SW reset: RX delay enabled, while TX delay retains the 9616d4cd041SVinod Koul * value before reset. 9626d4cd041SVinod Koul */ 963bb0ce4c1SAndré Draszik if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 964bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 965bb0ce4c1SAndré Draszik ret = at803x_enable_rx_delay(phydev); 966bb0ce4c1SAndré Draszik else 967cd28d1d6SVinod Koul ret = at803x_disable_rx_delay(phydev); 9682e5f9f28SMartin Blumenstingl if (ret < 0) 9691ca6d1b1SMugunthan V N return ret; 9706d4cd041SVinod Koul 9716d4cd041SVinod Koul if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 972bb0ce4c1SAndré Draszik phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 9736d4cd041SVinod Koul ret = at803x_enable_tx_delay(phydev); 974bb0ce4c1SAndré Draszik else 975bb0ce4c1SAndré Draszik ret = at803x_disable_tx_delay(phydev); 9762f664823SMichael Walle if (ret < 0) 9776d4cd041SVinod Koul return ret; 9782f664823SMichael Walle 979390b4cadSRussell King ret = at803x_smarteee_config(phydev); 980390b4cadSRussell King if (ret < 0) 981390b4cadSRussell King return ret; 982390b4cadSRussell King 9832f664823SMichael Walle ret = at803x_clk_out_config(phydev); 9842f664823SMichael Walle if (ret < 0) 9852f664823SMichael Walle return ret; 9862f664823SMichael Walle 9873c51fa5dSRussell King /* Ar803x extended next page bit is enabled by default. Cisco 9883c51fa5dSRussell King * multigig switches read this bit and attempt to negotiate 10Gbps 9893c51fa5dSRussell King * rates even if the next page bit is disabled. This is incorrect 9903c51fa5dSRussell King * behaviour but we still need to accommodate it. XNP is only needed 9913c51fa5dSRussell King * for 10Gbps support, so disable XNP. 9923c51fa5dSRussell King */ 9933c51fa5dSRussell King return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); 9940ca7111aSMatus Ujhelyi } 9950ca7111aSMatus Ujhelyi 99677a99394SZhao Qiang static int at803x_ack_interrupt(struct phy_device *phydev) 99777a99394SZhao Qiang { 99877a99394SZhao Qiang int err; 99977a99394SZhao Qiang 1000a46bd63bSMartin Blumenstingl err = phy_read(phydev, AT803X_INTR_STATUS); 100177a99394SZhao Qiang 100277a99394SZhao Qiang return (err < 0) ? err : 0; 100377a99394SZhao Qiang } 100477a99394SZhao Qiang 100577a99394SZhao Qiang static int at803x_config_intr(struct phy_device *phydev) 100677a99394SZhao Qiang { 1007*3265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 100877a99394SZhao Qiang int err; 100977a99394SZhao Qiang int value; 101077a99394SZhao Qiang 1011a46bd63bSMartin Blumenstingl value = phy_read(phydev, AT803X_INTR_ENABLE); 101277a99394SZhao Qiang 1013e6e4a556SMartin Blumenstingl if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1014a3417885SIoana Ciornei /* Clear any pending interrupts */ 1015a3417885SIoana Ciornei err = at803x_ack_interrupt(phydev); 1016a3417885SIoana Ciornei if (err) 1017a3417885SIoana Ciornei return err; 1018a3417885SIoana Ciornei 1019e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_AUTONEG_ERR; 1020e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_SPEED_CHANGED; 1021e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; 1022e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_FAIL; 1023e6e4a556SMartin Blumenstingl value |= AT803X_INTR_ENABLE_LINK_SUCCESS; 1024*3265f421SRobert Hancock if (priv->is_fiber) { 1025*3265f421SRobert Hancock value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; 1026*3265f421SRobert Hancock value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; 1027*3265f421SRobert Hancock } 1028e6e4a556SMartin Blumenstingl 1029e6e4a556SMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, value); 1030a3417885SIoana Ciornei } else { 1031a46bd63bSMartin Blumenstingl err = phy_write(phydev, AT803X_INTR_ENABLE, 0); 1032a3417885SIoana Ciornei if (err) 1033a3417885SIoana Ciornei return err; 1034a3417885SIoana Ciornei 1035a3417885SIoana Ciornei /* Clear any pending interrupts */ 1036a3417885SIoana Ciornei err = at803x_ack_interrupt(phydev); 1037a3417885SIoana Ciornei } 103877a99394SZhao Qiang 103977a99394SZhao Qiang return err; 104077a99394SZhao Qiang } 104177a99394SZhao Qiang 104229773097SIoana Ciornei static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev) 104329773097SIoana Ciornei { 104429773097SIoana Ciornei int irq_status, int_enabled; 104529773097SIoana Ciornei 104629773097SIoana Ciornei irq_status = phy_read(phydev, AT803X_INTR_STATUS); 104729773097SIoana Ciornei if (irq_status < 0) { 104829773097SIoana Ciornei phy_error(phydev); 104929773097SIoana Ciornei return IRQ_NONE; 105029773097SIoana Ciornei } 105129773097SIoana Ciornei 105229773097SIoana Ciornei /* Read the current enabled interrupts */ 105329773097SIoana Ciornei int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 105429773097SIoana Ciornei if (int_enabled < 0) { 105529773097SIoana Ciornei phy_error(phydev); 105629773097SIoana Ciornei return IRQ_NONE; 105729773097SIoana Ciornei } 105829773097SIoana Ciornei 105929773097SIoana Ciornei /* See if this was one of our enabled interrupts */ 106029773097SIoana Ciornei if (!(irq_status & int_enabled)) 106129773097SIoana Ciornei return IRQ_NONE; 106229773097SIoana Ciornei 106329773097SIoana Ciornei phy_trigger_machine(phydev); 106429773097SIoana Ciornei 106529773097SIoana Ciornei return IRQ_HANDLED; 106629773097SIoana Ciornei } 106729773097SIoana Ciornei 106813a56b44SDaniel Mack static void at803x_link_change_notify(struct phy_device *phydev) 106913a56b44SDaniel Mack { 107013a56b44SDaniel Mack /* 107113a56b44SDaniel Mack * Conduct a hardware reset for AT8030 every time a link loss is 107213a56b44SDaniel Mack * signalled. This is necessary to circumvent a hardware bug that 107313a56b44SDaniel Mack * occurs when the cable is unplugged while TX packets are pending 107413a56b44SDaniel Mack * in the FIFO. In such cases, the FIFO enters an error mode it 107513a56b44SDaniel Mack * cannot recover from by software. 107613a56b44SDaniel Mack */ 10776110ed2dSDavid Bauer if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) { 107813a56b44SDaniel Mack struct at803x_context context; 107913a56b44SDaniel Mack 108013a56b44SDaniel Mack at803x_context_save(phydev, &context); 108113a56b44SDaniel Mack 1082bafbdd52SSergei Shtylyov phy_device_reset(phydev, 1); 108313a56b44SDaniel Mack msleep(1); 1084bafbdd52SSergei Shtylyov phy_device_reset(phydev, 0); 1085d57019d1SSergei Shtylyov msleep(1); 108613a56b44SDaniel Mack 108713a56b44SDaniel Mack at803x_context_restore(phydev, &context); 108813a56b44SDaniel Mack 10895c5f626bSHeiner Kallweit phydev_dbg(phydev, "%s(): phy was reset\n", __func__); 109013a56b44SDaniel Mack } 109113a56b44SDaniel Mack } 109213a56b44SDaniel Mack 109379c7bc05SLuo Jie static int at803x_read_specific_status(struct phy_device *phydev) 109406d5f344SRussell King { 109579c7bc05SLuo Jie int ss; 109606d5f344SRussell King 109706d5f344SRussell King /* Read the AT8035 PHY-Specific Status register, which indicates the 109806d5f344SRussell King * speed and duplex that the PHY is actually using, irrespective of 109906d5f344SRussell King * whether we are in autoneg mode or not. 110006d5f344SRussell King */ 110106d5f344SRussell King ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 110206d5f344SRussell King if (ss < 0) 110306d5f344SRussell King return ss; 110406d5f344SRussell King 110506d5f344SRussell King if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) { 110679c7bc05SLuo Jie int sfc, speed; 11077dce80c2SOleksij Rempel 11087dce80c2SOleksij Rempel sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL); 11097dce80c2SOleksij Rempel if (sfc < 0) 11107dce80c2SOleksij Rempel return sfc; 11117dce80c2SOleksij Rempel 111279c7bc05SLuo Jie /* qca8081 takes the different bits for speed value from at803x */ 111379c7bc05SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) 111479c7bc05SLuo Jie speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); 111579c7bc05SLuo Jie else 111679c7bc05SLuo Jie speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); 111779c7bc05SLuo Jie 111879c7bc05SLuo Jie switch (speed) { 111906d5f344SRussell King case AT803X_SS_SPEED_10: 112006d5f344SRussell King phydev->speed = SPEED_10; 112106d5f344SRussell King break; 112206d5f344SRussell King case AT803X_SS_SPEED_100: 112306d5f344SRussell King phydev->speed = SPEED_100; 112406d5f344SRussell King break; 112506d5f344SRussell King case AT803X_SS_SPEED_1000: 112606d5f344SRussell King phydev->speed = SPEED_1000; 112706d5f344SRussell King break; 112879c7bc05SLuo Jie case QCA808X_SS_SPEED_2500: 112979c7bc05SLuo Jie phydev->speed = SPEED_2500; 113079c7bc05SLuo Jie break; 113106d5f344SRussell King } 113206d5f344SRussell King if (ss & AT803X_SS_DUPLEX) 113306d5f344SRussell King phydev->duplex = DUPLEX_FULL; 113406d5f344SRussell King else 113506d5f344SRussell King phydev->duplex = DUPLEX_HALF; 11367dce80c2SOleksij Rempel 113706d5f344SRussell King if (ss & AT803X_SS_MDIX) 113806d5f344SRussell King phydev->mdix = ETH_TP_MDI_X; 113906d5f344SRussell King else 114006d5f344SRussell King phydev->mdix = ETH_TP_MDI; 11417dce80c2SOleksij Rempel 11427dce80c2SOleksij Rempel switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) { 11437dce80c2SOleksij Rempel case AT803X_SFC_MANUAL_MDI: 11447dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI; 11457dce80c2SOleksij Rempel break; 11467dce80c2SOleksij Rempel case AT803X_SFC_MANUAL_MDIX: 11477dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_X; 11487dce80c2SOleksij Rempel break; 11497dce80c2SOleksij Rempel case AT803X_SFC_AUTOMATIC_CROSSOVER: 11507dce80c2SOleksij Rempel phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 11517dce80c2SOleksij Rempel break; 11527dce80c2SOleksij Rempel } 115306d5f344SRussell King } 115406d5f344SRussell King 115579c7bc05SLuo Jie return 0; 115679c7bc05SLuo Jie } 115779c7bc05SLuo Jie 115879c7bc05SLuo Jie static int at803x_read_status(struct phy_device *phydev) 115979c7bc05SLuo Jie { 1160*3265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 116179c7bc05SLuo Jie int err, old_link = phydev->link; 116279c7bc05SLuo Jie 1163*3265f421SRobert Hancock if (priv->is_1000basex) 1164*3265f421SRobert Hancock return genphy_c37_read_status(phydev); 1165*3265f421SRobert Hancock 116679c7bc05SLuo Jie /* Update the link, but return if there was an error */ 116779c7bc05SLuo Jie err = genphy_update_link(phydev); 116879c7bc05SLuo Jie if (err) 116979c7bc05SLuo Jie return err; 117079c7bc05SLuo Jie 117179c7bc05SLuo Jie /* why bother the PHY if nothing can have changed */ 117279c7bc05SLuo Jie if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) 117379c7bc05SLuo Jie return 0; 117479c7bc05SLuo Jie 117579c7bc05SLuo Jie phydev->speed = SPEED_UNKNOWN; 117679c7bc05SLuo Jie phydev->duplex = DUPLEX_UNKNOWN; 117779c7bc05SLuo Jie phydev->pause = 0; 117879c7bc05SLuo Jie phydev->asym_pause = 0; 117979c7bc05SLuo Jie 118079c7bc05SLuo Jie err = genphy_read_lpa(phydev); 118179c7bc05SLuo Jie if (err < 0) 118279c7bc05SLuo Jie return err; 118379c7bc05SLuo Jie 118479c7bc05SLuo Jie err = at803x_read_specific_status(phydev); 118579c7bc05SLuo Jie if (err < 0) 118679c7bc05SLuo Jie return err; 118779c7bc05SLuo Jie 118806d5f344SRussell King if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) 118906d5f344SRussell King phy_resolve_aneg_pause(phydev); 119006d5f344SRussell King 119106d5f344SRussell King return 0; 119206d5f344SRussell King } 119306d5f344SRussell King 11947dce80c2SOleksij Rempel static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl) 11957dce80c2SOleksij Rempel { 11967dce80c2SOleksij Rempel u16 val; 11977dce80c2SOleksij Rempel 11987dce80c2SOleksij Rempel switch (ctrl) { 11997dce80c2SOleksij Rempel case ETH_TP_MDI: 12007dce80c2SOleksij Rempel val = AT803X_SFC_MANUAL_MDI; 12017dce80c2SOleksij Rempel break; 12027dce80c2SOleksij Rempel case ETH_TP_MDI_X: 12037dce80c2SOleksij Rempel val = AT803X_SFC_MANUAL_MDIX; 12047dce80c2SOleksij Rempel break; 12057dce80c2SOleksij Rempel case ETH_TP_MDI_AUTO: 12067dce80c2SOleksij Rempel val = AT803X_SFC_AUTOMATIC_CROSSOVER; 12077dce80c2SOleksij Rempel break; 12087dce80c2SOleksij Rempel default: 12097dce80c2SOleksij Rempel return 0; 12107dce80c2SOleksij Rempel } 12117dce80c2SOleksij Rempel 12127dce80c2SOleksij Rempel return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL, 12137dce80c2SOleksij Rempel AT803X_SFC_MDI_CROSSOVER_MODE_M, 12147dce80c2SOleksij Rempel FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val)); 12157dce80c2SOleksij Rempel } 12167dce80c2SOleksij Rempel 12177dce80c2SOleksij Rempel static int at803x_config_aneg(struct phy_device *phydev) 12187dce80c2SOleksij Rempel { 1219*3265f421SRobert Hancock struct at803x_priv *priv = phydev->priv; 12207dce80c2SOleksij Rempel int ret; 12217dce80c2SOleksij Rempel 12227dce80c2SOleksij Rempel ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); 12237dce80c2SOleksij Rempel if (ret < 0) 12247dce80c2SOleksij Rempel return ret; 12257dce80c2SOleksij Rempel 12267dce80c2SOleksij Rempel /* Changes of the midx bits are disruptive to the normal operation; 12277dce80c2SOleksij Rempel * therefore any changes to these registers must be followed by a 12287dce80c2SOleksij Rempel * software reset to take effect. 12297dce80c2SOleksij Rempel */ 12307dce80c2SOleksij Rempel if (ret == 1) { 12317dce80c2SOleksij Rempel ret = genphy_soft_reset(phydev); 12327dce80c2SOleksij Rempel if (ret < 0) 12337dce80c2SOleksij Rempel return ret; 12347dce80c2SOleksij Rempel } 12357dce80c2SOleksij Rempel 1236*3265f421SRobert Hancock if (priv->is_1000basex) 1237*3265f421SRobert Hancock return genphy_c37_config_aneg(phydev); 1238*3265f421SRobert Hancock 1239f884d449SLuo Jie /* Do not restart auto-negotiation by setting ret to 0 defautly, 1240f884d449SLuo Jie * when calling __genphy_config_aneg later. 1241f884d449SLuo Jie */ 1242f884d449SLuo Jie ret = 0; 1243f884d449SLuo Jie 1244f884d449SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) { 1245f884d449SLuo Jie int phy_ctrl = 0; 1246f884d449SLuo Jie 1247f884d449SLuo Jie /* The reg MII_BMCR also needs to be configured for force mode, the 1248f884d449SLuo Jie * genphy_config_aneg is also needed. 1249f884d449SLuo Jie */ 1250f884d449SLuo Jie if (phydev->autoneg == AUTONEG_DISABLE) 1251f884d449SLuo Jie genphy_c45_pma_setup_forced(phydev); 1252f884d449SLuo Jie 1253f884d449SLuo Jie if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) 1254f884d449SLuo Jie phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G; 1255f884d449SLuo Jie 1256f884d449SLuo Jie ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 1257f884d449SLuo Jie MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl); 1258f884d449SLuo Jie if (ret < 0) 1259f884d449SLuo Jie return ret; 1260f884d449SLuo Jie } 1261f884d449SLuo Jie 1262f884d449SLuo Jie return __genphy_config_aneg(phydev, ret); 12637dce80c2SOleksij Rempel } 12647dce80c2SOleksij Rempel 1265cde0f4f8SMichael Walle static int at803x_get_downshift(struct phy_device *phydev, u8 *d) 1266cde0f4f8SMichael Walle { 1267cde0f4f8SMichael Walle int val; 1268cde0f4f8SMichael Walle 1269cde0f4f8SMichael Walle val = phy_read(phydev, AT803X_SMART_SPEED); 1270cde0f4f8SMichael Walle if (val < 0) 1271cde0f4f8SMichael Walle return val; 1272cde0f4f8SMichael Walle 1273cde0f4f8SMichael Walle if (val & AT803X_SMART_SPEED_ENABLE) 1274cde0f4f8SMichael Walle *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2; 1275cde0f4f8SMichael Walle else 1276cde0f4f8SMichael Walle *d = DOWNSHIFT_DEV_DISABLE; 1277cde0f4f8SMichael Walle 1278cde0f4f8SMichael Walle return 0; 1279cde0f4f8SMichael Walle } 1280cde0f4f8SMichael Walle 1281cde0f4f8SMichael Walle static int at803x_set_downshift(struct phy_device *phydev, u8 cnt) 1282cde0f4f8SMichael Walle { 1283cde0f4f8SMichael Walle u16 mask, set; 1284cde0f4f8SMichael Walle int ret; 1285cde0f4f8SMichael Walle 1286cde0f4f8SMichael Walle switch (cnt) { 1287cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DEFAULT_COUNT: 1288cde0f4f8SMichael Walle cnt = AT803X_DEFAULT_DOWNSHIFT; 1289cde0f4f8SMichael Walle fallthrough; 1290cde0f4f8SMichael Walle case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT: 1291cde0f4f8SMichael Walle set = AT803X_SMART_SPEED_ENABLE | 1292cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER | 1293cde0f4f8SMichael Walle FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2); 1294cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK; 1295cde0f4f8SMichael Walle break; 1296cde0f4f8SMichael Walle case DOWNSHIFT_DEV_DISABLE: 1297cde0f4f8SMichael Walle set = 0; 1298cde0f4f8SMichael Walle mask = AT803X_SMART_SPEED_ENABLE | 1299cde0f4f8SMichael Walle AT803X_SMART_SPEED_BYPASS_TIMER; 1300cde0f4f8SMichael Walle break; 1301cde0f4f8SMichael Walle default: 1302cde0f4f8SMichael Walle return -EINVAL; 1303cde0f4f8SMichael Walle } 1304cde0f4f8SMichael Walle 1305cde0f4f8SMichael Walle ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set); 1306cde0f4f8SMichael Walle 1307cde0f4f8SMichael Walle /* After changing the smart speed settings, we need to perform a 1308cde0f4f8SMichael Walle * software reset, use phy_init_hw() to make sure we set the 1309cde0f4f8SMichael Walle * reapply any values which might got lost during software reset. 1310cde0f4f8SMichael Walle */ 1311cde0f4f8SMichael Walle if (ret == 1) 1312cde0f4f8SMichael Walle ret = phy_init_hw(phydev); 1313cde0f4f8SMichael Walle 1314cde0f4f8SMichael Walle return ret; 1315cde0f4f8SMichael Walle } 1316cde0f4f8SMichael Walle 1317cde0f4f8SMichael Walle static int at803x_get_tunable(struct phy_device *phydev, 1318cde0f4f8SMichael Walle struct ethtool_tunable *tuna, void *data) 1319cde0f4f8SMichael Walle { 1320cde0f4f8SMichael Walle switch (tuna->id) { 1321cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 1322cde0f4f8SMichael Walle return at803x_get_downshift(phydev, data); 1323cde0f4f8SMichael Walle default: 1324cde0f4f8SMichael Walle return -EOPNOTSUPP; 1325cde0f4f8SMichael Walle } 1326cde0f4f8SMichael Walle } 1327cde0f4f8SMichael Walle 1328cde0f4f8SMichael Walle static int at803x_set_tunable(struct phy_device *phydev, 1329cde0f4f8SMichael Walle struct ethtool_tunable *tuna, const void *data) 1330cde0f4f8SMichael Walle { 1331cde0f4f8SMichael Walle switch (tuna->id) { 1332cde0f4f8SMichael Walle case ETHTOOL_PHY_DOWNSHIFT: 1333cde0f4f8SMichael Walle return at803x_set_downshift(phydev, *(const u8 *)data); 1334cde0f4f8SMichael Walle default: 1335cde0f4f8SMichael Walle return -EOPNOTSUPP; 1336cde0f4f8SMichael Walle } 1337cde0f4f8SMichael Walle } 1338cde0f4f8SMichael Walle 13396cb75767SMichael Walle static int at803x_cable_test_result_trans(u16 status) 13406cb75767SMichael Walle { 13416cb75767SMichael Walle switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 13426cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_NORMAL: 13436cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_OK; 13446cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_SHORT: 13456cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 13466cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_OPEN: 13476cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 13486cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_FAIL: 13496cb75767SMichael Walle default: 13506cb75767SMichael Walle return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 13516cb75767SMichael Walle } 13526cb75767SMichael Walle } 13536cb75767SMichael Walle 13546cb75767SMichael Walle static bool at803x_cdt_test_failed(u16 status) 13556cb75767SMichael Walle { 13566cb75767SMichael Walle return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) == 13576cb75767SMichael Walle AT803X_CDT_STATUS_STAT_FAIL; 13586cb75767SMichael Walle } 13596cb75767SMichael Walle 13606cb75767SMichael Walle static bool at803x_cdt_fault_length_valid(u16 status) 13616cb75767SMichael Walle { 13626cb75767SMichael Walle switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) { 13636cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_OPEN: 13646cb75767SMichael Walle case AT803X_CDT_STATUS_STAT_SHORT: 13656cb75767SMichael Walle return true; 13666cb75767SMichael Walle } 13676cb75767SMichael Walle return false; 13686cb75767SMichael Walle } 13696cb75767SMichael Walle 13706cb75767SMichael Walle static int at803x_cdt_fault_length(u16 status) 13716cb75767SMichael Walle { 13726cb75767SMichael Walle int dt; 13736cb75767SMichael Walle 13746cb75767SMichael Walle /* According to the datasheet the distance to the fault is 13756cb75767SMichael Walle * DELTA_TIME * 0.824 meters. 13766cb75767SMichael Walle * 13776cb75767SMichael Walle * The author suspect the correct formula is: 13786cb75767SMichael Walle * 13796cb75767SMichael Walle * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2 13806cb75767SMichael Walle * 13816cb75767SMichael Walle * where c is the speed of light, VF is the velocity factor of 13826cb75767SMichael Walle * the twisted pair cable, 125MHz the counter frequency and 13836cb75767SMichael Walle * we need to divide by 2 because the hardware will measure the 13846cb75767SMichael Walle * round trip time to the fault and back to the PHY. 13856cb75767SMichael Walle * 13866cb75767SMichael Walle * With a VF of 0.69 we get the factor 0.824 mentioned in the 13876cb75767SMichael Walle * datasheet. 13886cb75767SMichael Walle */ 13896cb75767SMichael Walle dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status); 13906cb75767SMichael Walle 13916cb75767SMichael Walle return (dt * 824) / 10; 13926cb75767SMichael Walle } 13936cb75767SMichael Walle 13946cb75767SMichael Walle static int at803x_cdt_start(struct phy_device *phydev, int pair) 13956cb75767SMichael Walle { 13966cb75767SMichael Walle u16 cdt; 13976cb75767SMichael Walle 13988c84d752SLuo Jie /* qca8081 takes the different bit 15 to enable CDT test */ 13998c84d752SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) 14008c84d752SLuo Jie cdt = QCA808X_CDT_ENABLE_TEST | 14018c84d752SLuo Jie QCA808X_CDT_LENGTH_UNIT | 14028c84d752SLuo Jie QCA808X_CDT_INTER_CHECK_DIS; 14038c84d752SLuo Jie else 14046cb75767SMichael Walle cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) | 14056cb75767SMichael Walle AT803X_CDT_ENABLE_TEST; 14066cb75767SMichael Walle 14076cb75767SMichael Walle return phy_write(phydev, AT803X_CDT, cdt); 14086cb75767SMichael Walle } 14096cb75767SMichael Walle 14106cb75767SMichael Walle static int at803x_cdt_wait_for_completion(struct phy_device *phydev) 14116cb75767SMichael Walle { 14126cb75767SMichael Walle int val, ret; 14138c84d752SLuo Jie u16 cdt_en; 14148c84d752SLuo Jie 14158c84d752SLuo Jie if (phydev->drv->phy_id == QCA8081_PHY_ID) 14168c84d752SLuo Jie cdt_en = QCA808X_CDT_ENABLE_TEST; 14178c84d752SLuo Jie else 14188c84d752SLuo Jie cdt_en = AT803X_CDT_ENABLE_TEST; 14196cb75767SMichael Walle 14206cb75767SMichael Walle /* One test run takes about 25ms */ 14216cb75767SMichael Walle ret = phy_read_poll_timeout(phydev, AT803X_CDT, val, 14228c84d752SLuo Jie !(val & cdt_en), 14236cb75767SMichael Walle 30000, 100000, true); 14246cb75767SMichael Walle 14256cb75767SMichael Walle return ret < 0 ? ret : 0; 14266cb75767SMichael Walle } 14276cb75767SMichael Walle 14286cb75767SMichael Walle static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair) 14296cb75767SMichael Walle { 14306cb75767SMichael Walle static const int ethtool_pair[] = { 14316cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_A, 14326cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_B, 14336cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_C, 14346cb75767SMichael Walle ETHTOOL_A_CABLE_PAIR_D, 14356cb75767SMichael Walle }; 14366cb75767SMichael Walle int ret, val; 14376cb75767SMichael Walle 14386cb75767SMichael Walle ret = at803x_cdt_start(phydev, pair); 14396cb75767SMichael Walle if (ret) 14406cb75767SMichael Walle return ret; 14416cb75767SMichael Walle 14426cb75767SMichael Walle ret = at803x_cdt_wait_for_completion(phydev); 14436cb75767SMichael Walle if (ret) 14446cb75767SMichael Walle return ret; 14456cb75767SMichael Walle 14466cb75767SMichael Walle val = phy_read(phydev, AT803X_CDT_STATUS); 14476cb75767SMichael Walle if (val < 0) 14486cb75767SMichael Walle return val; 14496cb75767SMichael Walle 14506cb75767SMichael Walle if (at803x_cdt_test_failed(val)) 14516cb75767SMichael Walle return 0; 14526cb75767SMichael Walle 14536cb75767SMichael Walle ethnl_cable_test_result(phydev, ethtool_pair[pair], 14546cb75767SMichael Walle at803x_cable_test_result_trans(val)); 14556cb75767SMichael Walle 14566cb75767SMichael Walle if (at803x_cdt_fault_length_valid(val)) 14576cb75767SMichael Walle ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], 14586cb75767SMichael Walle at803x_cdt_fault_length(val)); 14596cb75767SMichael Walle 14606cb75767SMichael Walle return 1; 14616cb75767SMichael Walle } 14626cb75767SMichael Walle 14636cb75767SMichael Walle static int at803x_cable_test_get_status(struct phy_device *phydev, 14646cb75767SMichael Walle bool *finished) 14656cb75767SMichael Walle { 1466dc0f3ed1SOleksij Rempel unsigned long pair_mask; 14676cb75767SMichael Walle int retries = 20; 14686cb75767SMichael Walle int pair, ret; 14696cb75767SMichael Walle 1470dc0f3ed1SOleksij Rempel if (phydev->phy_id == ATH9331_PHY_ID || 1471fada2ce0SDavid Bauer phydev->phy_id == ATH8032_PHY_ID || 1472fada2ce0SDavid Bauer phydev->phy_id == QCA9561_PHY_ID) 1473dc0f3ed1SOleksij Rempel pair_mask = 0x3; 1474dc0f3ed1SOleksij Rempel else 1475dc0f3ed1SOleksij Rempel pair_mask = 0xf; 1476dc0f3ed1SOleksij Rempel 14776cb75767SMichael Walle *finished = false; 14786cb75767SMichael Walle 14796cb75767SMichael Walle /* According to the datasheet the CDT can be performed when 14806cb75767SMichael Walle * there is no link partner or when the link partner is 14816cb75767SMichael Walle * auto-negotiating. Starting the test will restart the AN 14826cb75767SMichael Walle * automatically. It seems that doing this repeatedly we will 14836cb75767SMichael Walle * get a slot where our link partner won't disturb our 14846cb75767SMichael Walle * measurement. 14856cb75767SMichael Walle */ 14866cb75767SMichael Walle while (pair_mask && retries--) { 14876cb75767SMichael Walle for_each_set_bit(pair, &pair_mask, 4) { 14886cb75767SMichael Walle ret = at803x_cable_test_one_pair(phydev, pair); 14896cb75767SMichael Walle if (ret < 0) 14906cb75767SMichael Walle return ret; 14916cb75767SMichael Walle if (ret) 14926cb75767SMichael Walle clear_bit(pair, &pair_mask); 14936cb75767SMichael Walle } 14946cb75767SMichael Walle if (pair_mask) 14956cb75767SMichael Walle msleep(250); 14966cb75767SMichael Walle } 14976cb75767SMichael Walle 14986cb75767SMichael Walle *finished = true; 14996cb75767SMichael Walle 15006cb75767SMichael Walle return 0; 15016cb75767SMichael Walle } 15026cb75767SMichael Walle 15036cb75767SMichael Walle static int at803x_cable_test_start(struct phy_device *phydev) 15046cb75767SMichael Walle { 15056cb75767SMichael Walle /* Enable auto-negotiation, but advertise no capabilities, no link 15066cb75767SMichael Walle * will be established. A restart of the auto-negotiation is not 15076cb75767SMichael Walle * required, because the cable test will automatically break the link. 15086cb75767SMichael Walle */ 15096cb75767SMichael Walle phy_write(phydev, MII_BMCR, BMCR_ANENABLE); 15106cb75767SMichael Walle phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA); 1511dc0f3ed1SOleksij Rempel if (phydev->phy_id != ATH9331_PHY_ID && 1512fada2ce0SDavid Bauer phydev->phy_id != ATH8032_PHY_ID && 1513fada2ce0SDavid Bauer phydev->phy_id != QCA9561_PHY_ID) 15146cb75767SMichael Walle phy_write(phydev, MII_CTRL1000, 0); 15156cb75767SMichael Walle 15166cb75767SMichael Walle /* we do all the (time consuming) work later */ 15176cb75767SMichael Walle return 0; 15186cb75767SMichael Walle } 15196cb75767SMichael Walle 1520272833b9SAnsuel Smith static int qca83xx_config_init(struct phy_device *phydev) 1521272833b9SAnsuel Smith { 1522272833b9SAnsuel Smith u8 switch_revision; 1523272833b9SAnsuel Smith 1524272833b9SAnsuel Smith switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; 1525272833b9SAnsuel Smith 1526272833b9SAnsuel Smith switch (switch_revision) { 1527272833b9SAnsuel Smith case 1: 1528272833b9SAnsuel Smith /* For 100M waveform */ 152967999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); 1530272833b9SAnsuel Smith /* Turn on Gigabit clock */ 153167999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); 1532272833b9SAnsuel Smith break; 1533272833b9SAnsuel Smith 1534272833b9SAnsuel Smith case 2: 1535272833b9SAnsuel Smith phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); 1536272833b9SAnsuel Smith fallthrough; 1537272833b9SAnsuel Smith case 4: 1538272833b9SAnsuel Smith phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); 153967999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); 154067999555SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); 1541272833b9SAnsuel Smith at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); 1542272833b9SAnsuel Smith break; 1543272833b9SAnsuel Smith } 1544272833b9SAnsuel Smith 15451ca83119SAnsuel Smith /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. 15461ca83119SAnsuel Smith * Disable on init and enable only with 100m speed following 15471ca83119SAnsuel Smith * qca original source code. 15481ca83119SAnsuel Smith */ 15491ca83119SAnsuel Smith if (phydev->drv->phy_id == QCA8327_A_PHY_ID || 15501ca83119SAnsuel Smith phydev->drv->phy_id == QCA8327_B_PHY_ID) 155167999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 15521ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 0); 15531ca83119SAnsuel Smith 15549d1c29b4SAnsuel Smith /* Following original QCA sourcecode set port to prefer master */ 15559d1c29b4SAnsuel Smith phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); 15569d1c29b4SAnsuel Smith 1557272833b9SAnsuel Smith return 0; 1558272833b9SAnsuel Smith } 1559272833b9SAnsuel Smith 15601ca83119SAnsuel Smith static void qca83xx_link_change_notify(struct phy_device *phydev) 15611ca83119SAnsuel Smith { 15621ca83119SAnsuel Smith /* QCA8337 doesn't require DAC Amplitude adjustement */ 15631ca83119SAnsuel Smith if (phydev->drv->phy_id == QCA8337_PHY_ID) 15641ca83119SAnsuel Smith return; 15651ca83119SAnsuel Smith 15661ca83119SAnsuel Smith /* Set DAC Amplitude adjustment to +6% for 100m on link running */ 15671ca83119SAnsuel Smith if (phydev->state == PHY_RUNNING) { 15681ca83119SAnsuel Smith if (phydev->speed == SPEED_100) 156967999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 15701ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 15711ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN); 15721ca83119SAnsuel Smith } else { 15731ca83119SAnsuel Smith /* Reset DAC Amplitude adjustment */ 157467999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 15751ca83119SAnsuel Smith QCA8327_DEBUG_MANU_CTRL_EN, 0); 15761ca83119SAnsuel Smith } 15771ca83119SAnsuel Smith } 15781ca83119SAnsuel Smith 1579ba3c01eeSAnsuel Smith static int qca83xx_resume(struct phy_device *phydev) 1580ba3c01eeSAnsuel Smith { 1581ba3c01eeSAnsuel Smith int ret, val; 1582ba3c01eeSAnsuel Smith 1583ba3c01eeSAnsuel Smith /* Skip reset if not suspended */ 1584ba3c01eeSAnsuel Smith if (!phydev->suspended) 1585ba3c01eeSAnsuel Smith return 0; 1586ba3c01eeSAnsuel Smith 1587ba3c01eeSAnsuel Smith /* Reinit the port, reset values set by suspend */ 1588ba3c01eeSAnsuel Smith qca83xx_config_init(phydev); 1589ba3c01eeSAnsuel Smith 1590ba3c01eeSAnsuel Smith /* Reset the port on port resume */ 1591ba3c01eeSAnsuel Smith phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); 1592ba3c01eeSAnsuel Smith 1593ba3c01eeSAnsuel Smith /* On resume from suspend the switch execute a reset and 1594ba3c01eeSAnsuel Smith * restart auto-negotiation. Wait for reset to complete. 1595ba3c01eeSAnsuel Smith */ 1596ba3c01eeSAnsuel Smith ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), 1597ba3c01eeSAnsuel Smith 50000, 600000, true); 1598ba3c01eeSAnsuel Smith if (ret) 1599ba3c01eeSAnsuel Smith return ret; 1600ba3c01eeSAnsuel Smith 1601ba3c01eeSAnsuel Smith msleep(1); 1602ba3c01eeSAnsuel Smith 1603ba3c01eeSAnsuel Smith return 0; 1604ba3c01eeSAnsuel Smith } 1605ba3c01eeSAnsuel Smith 1606ba3c01eeSAnsuel Smith static int qca83xx_suspend(struct phy_device *phydev) 1607ba3c01eeSAnsuel Smith { 1608ba3c01eeSAnsuel Smith u16 mask = 0; 1609ba3c01eeSAnsuel Smith 1610ba3c01eeSAnsuel Smith /* Only QCA8337 support actual suspend. 1611ba3c01eeSAnsuel Smith * QCA8327 cause port unreliability when phy suspend 1612ba3c01eeSAnsuel Smith * is set. 1613ba3c01eeSAnsuel Smith */ 1614ba3c01eeSAnsuel Smith if (phydev->drv->phy_id == QCA8337_PHY_ID) { 1615ba3c01eeSAnsuel Smith genphy_suspend(phydev); 1616ba3c01eeSAnsuel Smith } else { 1617ba3c01eeSAnsuel Smith mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); 1618ba3c01eeSAnsuel Smith phy_modify(phydev, MII_BMCR, mask, 0); 1619ba3c01eeSAnsuel Smith } 1620ba3c01eeSAnsuel Smith 162167999555SAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, 1622ba3c01eeSAnsuel Smith AT803X_DEBUG_GATE_CLK_IN1000, 0); 1623ba3c01eeSAnsuel Smith 1624ba3c01eeSAnsuel Smith at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, 1625ba3c01eeSAnsuel Smith AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | 1626ba3c01eeSAnsuel Smith AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); 1627ba3c01eeSAnsuel Smith 1628ba3c01eeSAnsuel Smith return 0; 1629ba3c01eeSAnsuel Smith } 1630ba3c01eeSAnsuel Smith 16312acdd43fSLuo Jie static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) 16322acdd43fSLuo Jie { 16332acdd43fSLuo Jie int ret; 16342acdd43fSLuo Jie 16352acdd43fSLuo Jie /* Enable fast retrain */ 16362acdd43fSLuo Jie ret = genphy_c45_fast_retrain(phydev, true); 16372acdd43fSLuo Jie if (ret) 16382acdd43fSLuo Jie return ret; 16392acdd43fSLuo Jie 16402acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1, 16412acdd43fSLuo Jie QCA808X_TOP_OPTION1_DATA); 16422acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB, 16432acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_20DB_VALUE); 16442acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB, 16452acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_17DB_VALUE); 16462acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB, 16472acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_27DB_VALUE); 16482acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB, 16492acdd43fSLuo Jie QCA808X_MSE_THRESHOLD_28DB_VALUE); 16502acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, 16512acdd43fSLuo Jie QCA808X_MMD3_DEBUG_1_VALUE); 16522acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, 16532acdd43fSLuo Jie QCA808X_MMD3_DEBUG_4_VALUE); 16542acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, 16552acdd43fSLuo Jie QCA808X_MMD3_DEBUG_5_VALUE); 16562acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, 16572acdd43fSLuo Jie QCA808X_MMD3_DEBUG_3_VALUE); 16582acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6, 16592acdd43fSLuo Jie QCA808X_MMD3_DEBUG_6_VALUE); 16602acdd43fSLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2, 16612acdd43fSLuo Jie QCA808X_MMD3_DEBUG_2_VALUE); 16622acdd43fSLuo Jie 16632acdd43fSLuo Jie return 0; 16642acdd43fSLuo Jie } 16652acdd43fSLuo Jie 16669d4dae29SLuo Jie static int qca808x_phy_ms_random_seed_set(struct phy_device *phydev) 16679d4dae29SLuo Jie { 16689d4dae29SLuo Jie u16 seed_value = (prandom_u32() % QCA808X_MASTER_SLAVE_SEED_RANGE); 16699d4dae29SLuo Jie 16709d4dae29SLuo Jie return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 16719d4dae29SLuo Jie QCA808X_MASTER_SLAVE_SEED_CFG, 16729d4dae29SLuo Jie FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value)); 16739d4dae29SLuo Jie } 16749d4dae29SLuo Jie 16759d4dae29SLuo Jie static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable) 16769d4dae29SLuo Jie { 16779d4dae29SLuo Jie u16 seed_enable = 0; 16789d4dae29SLuo Jie 16799d4dae29SLuo Jie if (enable) 16809d4dae29SLuo Jie seed_enable = QCA808X_MASTER_SLAVE_SEED_ENABLE; 16819d4dae29SLuo Jie 16829d4dae29SLuo Jie return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED, 16839d4dae29SLuo Jie QCA808X_MASTER_SLAVE_SEED_ENABLE, seed_enable); 16849d4dae29SLuo Jie } 16859d4dae29SLuo Jie 16862acdd43fSLuo Jie static int qca808x_config_init(struct phy_device *phydev) 16872acdd43fSLuo Jie { 16882acdd43fSLuo Jie int ret; 16892acdd43fSLuo Jie 16902acdd43fSLuo Jie /* Active adc&vga on 802.3az for the link 1000M and 100M */ 16912acdd43fSLuo Jie ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7, 16922acdd43fSLuo Jie QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN); 16932acdd43fSLuo Jie if (ret) 16942acdd43fSLuo Jie return ret; 16952acdd43fSLuo Jie 16962acdd43fSLuo Jie /* Adjust the threshold on 802.3az for the link 1000M */ 16972acdd43fSLuo Jie ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 16982acdd43fSLuo Jie QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL); 16992acdd43fSLuo Jie if (ret) 17002acdd43fSLuo Jie return ret; 17012acdd43fSLuo Jie 17022acdd43fSLuo Jie /* Config the fast retrain for the link 2500M */ 17032acdd43fSLuo Jie ret = qca808x_phy_fast_retrain_config(phydev); 17042acdd43fSLuo Jie if (ret) 17052acdd43fSLuo Jie return ret; 17062acdd43fSLuo Jie 17079d4dae29SLuo Jie /* Configure lower ramdom seed to make phy linked as slave mode */ 17089d4dae29SLuo Jie ret = qca808x_phy_ms_random_seed_set(phydev); 17099d4dae29SLuo Jie if (ret) 17109d4dae29SLuo Jie return ret; 17119d4dae29SLuo Jie 17129d4dae29SLuo Jie /* Enable seed */ 17139d4dae29SLuo Jie ret = qca808x_phy_ms_seed_enable(phydev, true); 17149d4dae29SLuo Jie if (ret) 17159d4dae29SLuo Jie return ret; 17169d4dae29SLuo Jie 17172acdd43fSLuo Jie /* Configure adc threshold as 100mv for the link 10M */ 17182acdd43fSLuo Jie return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, 17192acdd43fSLuo Jie QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV); 17202acdd43fSLuo Jie } 17212acdd43fSLuo Jie 172279c7bc05SLuo Jie static int qca808x_read_status(struct phy_device *phydev) 172379c7bc05SLuo Jie { 172479c7bc05SLuo Jie int ret; 172579c7bc05SLuo Jie 172679c7bc05SLuo Jie ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); 172779c7bc05SLuo Jie if (ret < 0) 172879c7bc05SLuo Jie return ret; 172979c7bc05SLuo Jie 173079c7bc05SLuo Jie linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising, 173179c7bc05SLuo Jie ret & MDIO_AN_10GBT_STAT_LP2_5G); 173279c7bc05SLuo Jie 173379c7bc05SLuo Jie ret = genphy_read_status(phydev); 173479c7bc05SLuo Jie if (ret) 173579c7bc05SLuo Jie return ret; 173679c7bc05SLuo Jie 173779c7bc05SLuo Jie ret = at803x_read_specific_status(phydev); 173879c7bc05SLuo Jie if (ret < 0) 173979c7bc05SLuo Jie return ret; 174079c7bc05SLuo Jie 174179c7bc05SLuo Jie if (phydev->link && phydev->speed == SPEED_2500) 174279c7bc05SLuo Jie phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 174379c7bc05SLuo Jie else 174479c7bc05SLuo Jie phydev->interface = PHY_INTERFACE_MODE_SMII; 174579c7bc05SLuo Jie 17468bc1c543SLuo Jie /* generate seed as a lower random value to make PHY linked as SLAVE easily, 17478bc1c543SLuo Jie * except for master/slave configuration fault detected. 17488bc1c543SLuo Jie * the reason for not putting this code into the function link_change_notify is 17498bc1c543SLuo Jie * the corner case where the link partner is also the qca8081 PHY and the seed 17508bc1c543SLuo Jie * value is configured as the same value, the link can't be up and no link change 17518bc1c543SLuo Jie * occurs. 17528bc1c543SLuo Jie */ 17538bc1c543SLuo Jie if (!phydev->link) { 17548bc1c543SLuo Jie if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR) { 17558bc1c543SLuo Jie qca808x_phy_ms_seed_enable(phydev, false); 17568bc1c543SLuo Jie } else { 17578bc1c543SLuo Jie qca808x_phy_ms_random_seed_set(phydev); 17588bc1c543SLuo Jie qca808x_phy_ms_seed_enable(phydev, true); 17598bc1c543SLuo Jie } 17608bc1c543SLuo Jie } 17618bc1c543SLuo Jie 176279c7bc05SLuo Jie return 0; 176379c7bc05SLuo Jie } 176479c7bc05SLuo Jie 17659d4dae29SLuo Jie static int qca808x_soft_reset(struct phy_device *phydev) 17669d4dae29SLuo Jie { 17679d4dae29SLuo Jie int ret; 17689d4dae29SLuo Jie 17699d4dae29SLuo Jie ret = genphy_soft_reset(phydev); 17709d4dae29SLuo Jie if (ret < 0) 17719d4dae29SLuo Jie return ret; 17729d4dae29SLuo Jie 17739d4dae29SLuo Jie return qca808x_phy_ms_seed_enable(phydev, true); 17749d4dae29SLuo Jie } 17759d4dae29SLuo Jie 17768c84d752SLuo Jie static bool qca808x_cdt_fault_length_valid(int cdt_code) 17778c84d752SLuo Jie { 17788c84d752SLuo Jie switch (cdt_code) { 17798c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_SHORT: 17808c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_OPEN: 17818c84d752SLuo Jie return true; 17828c84d752SLuo Jie default: 17838c84d752SLuo Jie return false; 17848c84d752SLuo Jie } 17858c84d752SLuo Jie } 17868c84d752SLuo Jie 17878c84d752SLuo Jie static int qca808x_cable_test_result_trans(int cdt_code) 17888c84d752SLuo Jie { 17898c84d752SLuo Jie switch (cdt_code) { 17908c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_NORMAL: 17918c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_OK; 17928c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_SHORT: 17938c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; 17948c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_OPEN: 17958c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; 17968c84d752SLuo Jie case QCA808X_CDT_STATUS_STAT_FAIL: 17978c84d752SLuo Jie default: 17988c84d752SLuo Jie return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; 17998c84d752SLuo Jie } 18008c84d752SLuo Jie } 18018c84d752SLuo Jie 18028c84d752SLuo Jie static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair) 18038c84d752SLuo Jie { 18048c84d752SLuo Jie int val; 18058c84d752SLuo Jie u32 cdt_length_reg = 0; 18068c84d752SLuo Jie 18078c84d752SLuo Jie switch (pair) { 18088c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_A: 18098c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A; 18108c84d752SLuo Jie break; 18118c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_B: 18128c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B; 18138c84d752SLuo Jie break; 18148c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_C: 18158c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C; 18168c84d752SLuo Jie break; 18178c84d752SLuo Jie case ETHTOOL_A_CABLE_PAIR_D: 18188c84d752SLuo Jie cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D; 18198c84d752SLuo Jie break; 18208c84d752SLuo Jie default: 18218c84d752SLuo Jie return -EINVAL; 18228c84d752SLuo Jie } 18238c84d752SLuo Jie 18248c84d752SLuo Jie val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg); 18258c84d752SLuo Jie if (val < 0) 18268c84d752SLuo Jie return val; 18278c84d752SLuo Jie 18288c84d752SLuo Jie return (FIELD_GET(QCA808X_CDT_DIAG_LENGTH, val) * 824) / 10; 18298c84d752SLuo Jie } 18308c84d752SLuo Jie 18318c84d752SLuo Jie static int qca808x_cable_test_start(struct phy_device *phydev) 18328c84d752SLuo Jie { 18338c84d752SLuo Jie int ret; 18348c84d752SLuo Jie 18358c84d752SLuo Jie /* perform CDT with the following configs: 18368c84d752SLuo Jie * 1. disable hibernation. 18378c84d752SLuo Jie * 2. force PHY working in MDI mode. 18388c84d752SLuo Jie * 3. for PHY working in 1000BaseT. 18398c84d752SLuo Jie * 4. configure the threshold. 18408c84d752SLuo Jie */ 18418c84d752SLuo Jie 18428c84d752SLuo Jie ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0); 18438c84d752SLuo Jie if (ret < 0) 18448c84d752SLuo Jie return ret; 18458c84d752SLuo Jie 18468c84d752SLuo Jie ret = at803x_config_mdix(phydev, ETH_TP_MDI); 18478c84d752SLuo Jie if (ret < 0) 18488c84d752SLuo Jie return ret; 18498c84d752SLuo Jie 18508c84d752SLuo Jie /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */ 18518c84d752SLuo Jie phydev->duplex = DUPLEX_FULL; 18528c84d752SLuo Jie phydev->speed = SPEED_1000; 18538c84d752SLuo Jie ret = genphy_c45_pma_setup_forced(phydev); 18548c84d752SLuo Jie if (ret < 0) 18558c84d752SLuo Jie return ret; 18568c84d752SLuo Jie 18578c84d752SLuo Jie ret = genphy_setup_forced(phydev); 18588c84d752SLuo Jie if (ret < 0) 18598c84d752SLuo Jie return ret; 18608c84d752SLuo Jie 18618c84d752SLuo Jie /* configure the thresholds for open, short, pair ok test */ 18628c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); 18638c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); 18648c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); 18658c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); 18668c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); 18678c84d752SLuo Jie phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); 18688c84d752SLuo Jie 18698c84d752SLuo Jie return 0; 18708c84d752SLuo Jie } 18718c84d752SLuo Jie 18728c84d752SLuo Jie static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished) 18738c84d752SLuo Jie { 18748c84d752SLuo Jie int ret, val; 18758c84d752SLuo Jie int pair_a, pair_b, pair_c, pair_d; 18768c84d752SLuo Jie 18778c84d752SLuo Jie *finished = false; 18788c84d752SLuo Jie 18798c84d752SLuo Jie ret = at803x_cdt_start(phydev, 0); 18808c84d752SLuo Jie if (ret) 18818c84d752SLuo Jie return ret; 18828c84d752SLuo Jie 18838c84d752SLuo Jie ret = at803x_cdt_wait_for_completion(phydev); 18848c84d752SLuo Jie if (ret) 18858c84d752SLuo Jie return ret; 18868c84d752SLuo Jie 18878c84d752SLuo Jie val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS); 18888c84d752SLuo Jie if (val < 0) 18898c84d752SLuo Jie return val; 18908c84d752SLuo Jie 18918c84d752SLuo Jie pair_a = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, val); 18928c84d752SLuo Jie pair_b = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, val); 18938c84d752SLuo Jie pair_c = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, val); 18948c84d752SLuo Jie pair_d = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, val); 18958c84d752SLuo Jie 18968c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, 18978c84d752SLuo Jie qca808x_cable_test_result_trans(pair_a)); 18988c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, 18998c84d752SLuo Jie qca808x_cable_test_result_trans(pair_b)); 19008c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, 19018c84d752SLuo Jie qca808x_cable_test_result_trans(pair_c)); 19028c84d752SLuo Jie ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, 19038c84d752SLuo Jie qca808x_cable_test_result_trans(pair_d)); 19048c84d752SLuo Jie 19058c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_a)) 19068c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, 19078c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A)); 19088c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_b)) 19098c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, 19108c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B)); 19118c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_c)) 19128c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, 19138c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C)); 19148c84d752SLuo Jie if (qca808x_cdt_fault_length_valid(pair_d)) 19158c84d752SLuo Jie ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, 19168c84d752SLuo Jie qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D)); 19178c84d752SLuo Jie 19188c84d752SLuo Jie *finished = true; 19198c84d752SLuo Jie 19208c84d752SLuo Jie return 0; 19218c84d752SLuo Jie } 19228c84d752SLuo Jie 1923317420abSMugunthan V N static struct phy_driver at803x_driver[] = { 1924317420abSMugunthan V N { 192596c36712SMichael Walle /* Qualcomm Atheros AR8035 */ 19260465d8f8SMichael Walle PHY_ID_MATCH_EXACT(ATH8035_PHY_ID), 192796c36712SMichael Walle .name = "Qualcomm Atheros AR8035", 19286cb75767SMichael Walle .flags = PHY_POLL_CABLE_TEST, 19292f664823SMichael Walle .probe = at803x_probe, 19302318ca8aSMichael Walle .remove = at803x_remove, 19317dce80c2SOleksij Rempel .config_aneg = at803x_config_aneg, 19320ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 1933cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 1934ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 1935ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 19366229ed1fSDaniel Mack .suspend = at803x_suspend, 19376229ed1fSDaniel Mack .resume = at803x_resume, 1938dcdecdcfSHeiner Kallweit /* PHY_GBIT_FEATURES */ 193906d5f344SRussell King .read_status = at803x_read_status, 19400eae5982SMåns Rullgård .config_intr = at803x_config_intr, 194129773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 1942cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 1943cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 19446cb75767SMichael Walle .cable_test_start = at803x_cable_test_start, 19456cb75767SMichael Walle .cable_test_get_status = at803x_cable_test_get_status, 1946317420abSMugunthan V N }, { 194796c36712SMichael Walle /* Qualcomm Atheros AR8030 */ 1948bd8ca17fSDaniel Mack .phy_id = ATH8030_PHY_ID, 194996c36712SMichael Walle .name = "Qualcomm Atheros AR8030", 19500465d8f8SMichael Walle .phy_id_mask = AT8030_PHY_ID_MASK, 19512f664823SMichael Walle .probe = at803x_probe, 19522318ca8aSMichael Walle .remove = at803x_remove, 19530ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 195413a56b44SDaniel Mack .link_change_notify = at803x_link_change_notify, 1955ea13c9eeSMugunthan V N .set_wol = at803x_set_wol, 1956ea13c9eeSMugunthan V N .get_wol = at803x_get_wol, 19576229ed1fSDaniel Mack .suspend = at803x_suspend, 19586229ed1fSDaniel Mack .resume = at803x_resume, 1959dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */ 19600eae5982SMåns Rullgård .config_intr = at803x_config_intr, 196129773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 196205d7cce8SMugunthan V N }, { 196396c36712SMichael Walle /* Qualcomm Atheros AR8031/AR8033 */ 19640465d8f8SMichael Walle PHY_ID_MATCH_EXACT(ATH8031_PHY_ID), 196596c36712SMichael Walle .name = "Qualcomm Atheros AR8031/AR8033", 19666cb75767SMichael Walle .flags = PHY_POLL_CABLE_TEST, 19672f664823SMichael Walle .probe = at803x_probe, 19682318ca8aSMichael Walle .remove = at803x_remove, 196905d7cce8SMugunthan V N .config_init = at803x_config_init, 197063477a5dSMichael Walle .config_aneg = at803x_config_aneg, 1971cde0f4f8SMichael Walle .soft_reset = genphy_soft_reset, 197205d7cce8SMugunthan V N .set_wol = at803x_set_wol, 197305d7cce8SMugunthan V N .get_wol = at803x_get_wol, 19746229ed1fSDaniel Mack .suspend = at803x_suspend, 19756229ed1fSDaniel Mack .resume = at803x_resume, 1976c329e5afSDavid Bauer .read_page = at803x_read_page, 1977c329e5afSDavid Bauer .write_page = at803x_write_page, 1978b856150cSDavid Bauer .get_features = at803x_get_features, 197906d5f344SRussell King .read_status = at803x_read_status, 198077a99394SZhao Qiang .config_intr = &at803x_config_intr, 198129773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 1982cde0f4f8SMichael Walle .get_tunable = at803x_get_tunable, 1983cde0f4f8SMichael Walle .set_tunable = at803x_set_tunable, 19846cb75767SMichael Walle .cable_test_start = at803x_cable_test_start, 19856cb75767SMichael Walle .cable_test_get_status = at803x_cable_test_get_status, 19867908d2ceSOleksij Rempel }, { 19875800091aSDavid Bauer /* Qualcomm Atheros AR8032 */ 19885800091aSDavid Bauer PHY_ID_MATCH_EXACT(ATH8032_PHY_ID), 19895800091aSDavid Bauer .name = "Qualcomm Atheros AR8032", 19905800091aSDavid Bauer .probe = at803x_probe, 19915800091aSDavid Bauer .remove = at803x_remove, 1992dc0f3ed1SOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 19935800091aSDavid Bauer .config_init = at803x_config_init, 19945800091aSDavid Bauer .link_change_notify = at803x_link_change_notify, 19955800091aSDavid Bauer .set_wol = at803x_set_wol, 19965800091aSDavid Bauer .get_wol = at803x_get_wol, 19975800091aSDavid Bauer .suspend = at803x_suspend, 19985800091aSDavid Bauer .resume = at803x_resume, 19995800091aSDavid Bauer /* PHY_BASIC_FEATURES */ 20005800091aSDavid Bauer .config_intr = at803x_config_intr, 200129773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 2002dc0f3ed1SOleksij Rempel .cable_test_start = at803x_cable_test_start, 2003dc0f3ed1SOleksij Rempel .cable_test_get_status = at803x_cable_test_get_status, 20045800091aSDavid Bauer }, { 20057908d2ceSOleksij Rempel /* ATHEROS AR9331 */ 20067908d2ceSOleksij Rempel PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), 200796c36712SMichael Walle .name = "Qualcomm Atheros AR9331 built-in PHY", 20087908d2ceSOleksij Rempel .suspend = at803x_suspend, 20097908d2ceSOleksij Rempel .resume = at803x_resume, 2010dc0f3ed1SOleksij Rempel .flags = PHY_POLL_CABLE_TEST, 20117908d2ceSOleksij Rempel /* PHY_BASIC_FEATURES */ 20127908d2ceSOleksij Rempel .config_intr = &at803x_config_intr, 201329773097SIoana Ciornei .handle_interrupt = at803x_handle_interrupt, 2014dc0f3ed1SOleksij Rempel .cable_test_start = at803x_cable_test_start, 2015dc0f3ed1SOleksij Rempel .cable_test_get_status = at803x_cable_test_get_status, 20167dce80c2SOleksij Rempel .read_status = at803x_read_status, 20177dce80c2SOleksij Rempel .soft_reset = genphy_soft_reset, 20187dce80c2SOleksij Rempel .config_aneg = at803x_config_aneg, 2019272833b9SAnsuel Smith }, { 2020fada2ce0SDavid Bauer /* Qualcomm Atheros QCA9561 */ 2021fada2ce0SDavid Bauer PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), 2022fada2ce0SDavid Bauer .name = "Qualcomm Atheros QCA9561 built-in PHY", 2023fada2ce0SDavid Bauer .suspend = at803x_suspend, 2024fada2ce0SDavid Bauer .resume = at803x_resume, 2025fada2ce0SDavid Bauer .flags = PHY_POLL_CABLE_TEST, 2026fada2ce0SDavid Bauer /* PHY_BASIC_FEATURES */ 2027fada2ce0SDavid Bauer .config_intr = &at803x_config_intr, 2028fada2ce0SDavid Bauer .handle_interrupt = at803x_handle_interrupt, 2029fada2ce0SDavid Bauer .cable_test_start = at803x_cable_test_start, 2030fada2ce0SDavid Bauer .cable_test_get_status = at803x_cable_test_get_status, 2031fada2ce0SDavid Bauer .read_status = at803x_read_status, 2032fada2ce0SDavid Bauer .soft_reset = genphy_soft_reset, 2033fada2ce0SDavid Bauer .config_aneg = at803x_config_aneg, 2034fada2ce0SDavid Bauer }, { 2035272833b9SAnsuel Smith /* QCA8337 */ 2036272833b9SAnsuel Smith .phy_id = QCA8337_PHY_ID, 2037272833b9SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 2038d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8337 internal PHY", 2039272833b9SAnsuel Smith /* PHY_GBIT_FEATURES */ 20401ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 2041272833b9SAnsuel Smith .probe = at803x_probe, 2042272833b9SAnsuel Smith .flags = PHY_IS_INTERNAL, 2043272833b9SAnsuel Smith .config_init = qca83xx_config_init, 2044272833b9SAnsuel Smith .soft_reset = genphy_soft_reset, 2045272833b9SAnsuel Smith .get_sset_count = at803x_get_sset_count, 2046272833b9SAnsuel Smith .get_strings = at803x_get_strings, 2047272833b9SAnsuel Smith .get_stats = at803x_get_stats, 2048ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 2049ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 20500ccf8511SAnsuel Smith }, { 2051b4df02b5SAnsuel Smith /* QCA8327-A from switch QCA8327-AL1A */ 2052b4df02b5SAnsuel Smith .phy_id = QCA8327_A_PHY_ID, 20530ccf8511SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 2054d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8327-A internal PHY", 2055b4df02b5SAnsuel Smith /* PHY_GBIT_FEATURES */ 20561ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 2057b4df02b5SAnsuel Smith .probe = at803x_probe, 2058b4df02b5SAnsuel Smith .flags = PHY_IS_INTERNAL, 2059b4df02b5SAnsuel Smith .config_init = qca83xx_config_init, 2060b4df02b5SAnsuel Smith .soft_reset = genphy_soft_reset, 2061b4df02b5SAnsuel Smith .get_sset_count = at803x_get_sset_count, 2062b4df02b5SAnsuel Smith .get_strings = at803x_get_strings, 2063b4df02b5SAnsuel Smith .get_stats = at803x_get_stats, 2064ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 2065ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 2066b4df02b5SAnsuel Smith }, { 2067b4df02b5SAnsuel Smith /* QCA8327-B from switch QCA8327-BL1A */ 2068b4df02b5SAnsuel Smith .phy_id = QCA8327_B_PHY_ID, 2069b4df02b5SAnsuel Smith .phy_id_mask = QCA8K_PHY_ID_MASK, 2070d44fd860SAnsuel Smith .name = "Qualcomm Atheros 8327-B internal PHY", 20710ccf8511SAnsuel Smith /* PHY_GBIT_FEATURES */ 20721ca83119SAnsuel Smith .link_change_notify = qca83xx_link_change_notify, 20730ccf8511SAnsuel Smith .probe = at803x_probe, 20740ccf8511SAnsuel Smith .flags = PHY_IS_INTERNAL, 20750ccf8511SAnsuel Smith .config_init = qca83xx_config_init, 20760ccf8511SAnsuel Smith .soft_reset = genphy_soft_reset, 20770ccf8511SAnsuel Smith .get_sset_count = at803x_get_sset_count, 20780ccf8511SAnsuel Smith .get_strings = at803x_get_strings, 20790ccf8511SAnsuel Smith .get_stats = at803x_get_stats, 2080ba3c01eeSAnsuel Smith .suspend = qca83xx_suspend, 2081ba3c01eeSAnsuel Smith .resume = qca83xx_resume, 2082daf61732SLuo Jie }, { 2083daf61732SLuo Jie /* Qualcomm QCA8081 */ 2084daf61732SLuo Jie PHY_ID_MATCH_EXACT(QCA8081_PHY_ID), 2085daf61732SLuo Jie .name = "Qualcomm QCA8081", 20868c84d752SLuo Jie .flags = PHY_POLL_CABLE_TEST, 2087daf61732SLuo Jie .config_intr = at803x_config_intr, 2088daf61732SLuo Jie .handle_interrupt = at803x_handle_interrupt, 2089daf61732SLuo Jie .get_tunable = at803x_get_tunable, 2090daf61732SLuo Jie .set_tunable = at803x_set_tunable, 2091daf61732SLuo Jie .set_wol = at803x_set_wol, 2092daf61732SLuo Jie .get_wol = at803x_get_wol, 2093765c22aaSLuo Jie .get_features = at803x_get_features, 2094f884d449SLuo Jie .config_aneg = at803x_config_aneg, 2095daf61732SLuo Jie .suspend = genphy_suspend, 2096daf61732SLuo Jie .resume = genphy_resume, 209779c7bc05SLuo Jie .read_status = qca808x_read_status, 20982acdd43fSLuo Jie .config_init = qca808x_config_init, 20999d4dae29SLuo Jie .soft_reset = qca808x_soft_reset, 21008c84d752SLuo Jie .cable_test_start = qca808x_cable_test_start, 21018c84d752SLuo Jie .cable_test_get_status = qca808x_cable_test_get_status, 2102272833b9SAnsuel Smith }, }; 21030ca7111aSMatus Ujhelyi 210450fd7150SJohan Hovold module_phy_driver(at803x_driver); 21050ca7111aSMatus Ujhelyi 21060ca7111aSMatus Ujhelyi static struct mdio_device_id __maybe_unused atheros_tbl[] = { 21070465d8f8SMichael Walle { ATH8030_PHY_ID, AT8030_PHY_ID_MASK }, 21080465d8f8SMichael Walle { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) }, 21095800091aSDavid Bauer { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, 21100465d8f8SMichael Walle { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, 21117908d2ceSOleksij Rempel { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, 21120ccf8511SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, 2113b4df02b5SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, 2114b4df02b5SAnsuel Smith { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, 2115fada2ce0SDavid Bauer { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, 2116daf61732SLuo Jie { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, 21170ca7111aSMatus Ujhelyi { } 21180ca7111aSMatus Ujhelyi }; 21190ca7111aSMatus Ujhelyi 21200ca7111aSMatus Ujhelyi MODULE_DEVICE_TABLE(mdio, atheros_tbl); 2121