10ca7111aSMatus Ujhelyi /* 20ca7111aSMatus Ujhelyi * drivers/net/phy/at803x.c 30ca7111aSMatus Ujhelyi * 40ca7111aSMatus Ujhelyi * Driver for Atheros 803x PHY 50ca7111aSMatus Ujhelyi * 60ca7111aSMatus Ujhelyi * Author: Matus Ujhelyi <ujhelyi.m@gmail.com> 70ca7111aSMatus Ujhelyi * 80ca7111aSMatus Ujhelyi * This program is free software; you can redistribute it and/or modify it 90ca7111aSMatus Ujhelyi * under the terms of the GNU General Public License as published by the 100ca7111aSMatus Ujhelyi * Free Software Foundation; either version 2 of the License, or (at your 110ca7111aSMatus Ujhelyi * option) any later version. 120ca7111aSMatus Ujhelyi */ 130ca7111aSMatus Ujhelyi 140ca7111aSMatus Ujhelyi #include <linux/phy.h> 150ca7111aSMatus Ujhelyi #include <linux/module.h> 160ca7111aSMatus Ujhelyi #include <linux/string.h> 170ca7111aSMatus Ujhelyi #include <linux/netdevice.h> 180ca7111aSMatus Ujhelyi #include <linux/etherdevice.h> 190ca7111aSMatus Ujhelyi 200ca7111aSMatus Ujhelyi #define AT803X_INTR_ENABLE 0x12 210ca7111aSMatus Ujhelyi #define AT803X_INTR_STATUS 0x13 220ca7111aSMatus Ujhelyi #define AT803X_WOL_ENABLE 0x01 230ca7111aSMatus Ujhelyi #define AT803X_DEVICE_ADDR 0x03 240ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C 250ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B 260ca7111aSMatus Ujhelyi #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A 270ca7111aSMatus Ujhelyi #define AT803X_MMD_ACCESS_CONTROL 0x0D 280ca7111aSMatus Ujhelyi #define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E 290ca7111aSMatus Ujhelyi #define AT803X_FUNC_DATA 0x4003 300ca7111aSMatus Ujhelyi 310ca7111aSMatus Ujhelyi MODULE_DESCRIPTION("Atheros 803x PHY driver"); 320ca7111aSMatus Ujhelyi MODULE_AUTHOR("Matus Ujhelyi"); 330ca7111aSMatus Ujhelyi MODULE_LICENSE("GPL"); 340ca7111aSMatus Ujhelyi 350ca7111aSMatus Ujhelyi static void at803x_set_wol_mac_addr(struct phy_device *phydev) 360ca7111aSMatus Ujhelyi { 370ca7111aSMatus Ujhelyi struct net_device *ndev = phydev->attached_dev; 380ca7111aSMatus Ujhelyi const u8 *mac; 390ca7111aSMatus Ujhelyi unsigned int i, offsets[] = { 400ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_32_47_OFFSET, 410ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_16_31_OFFSET, 420ca7111aSMatus Ujhelyi AT803X_LOC_MAC_ADDR_0_15_OFFSET, 430ca7111aSMatus Ujhelyi }; 440ca7111aSMatus Ujhelyi 450ca7111aSMatus Ujhelyi if (!ndev) 460ca7111aSMatus Ujhelyi return; 470ca7111aSMatus Ujhelyi 480ca7111aSMatus Ujhelyi mac = (const u8 *) ndev->dev_addr; 490ca7111aSMatus Ujhelyi 500ca7111aSMatus Ujhelyi if (!is_valid_ether_addr(mac)) 510ca7111aSMatus Ujhelyi return; 520ca7111aSMatus Ujhelyi 530ca7111aSMatus Ujhelyi for (i = 0; i < 3; i++) { 540ca7111aSMatus Ujhelyi phy_write(phydev, AT803X_MMD_ACCESS_CONTROL, 550ca7111aSMatus Ujhelyi AT803X_DEVICE_ADDR); 560ca7111aSMatus Ujhelyi phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA, 570ca7111aSMatus Ujhelyi offsets[i]); 580ca7111aSMatus Ujhelyi phy_write(phydev, AT803X_MMD_ACCESS_CONTROL, 590ca7111aSMatus Ujhelyi AT803X_FUNC_DATA); 600ca7111aSMatus Ujhelyi phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA, 610ca7111aSMatus Ujhelyi mac[(i * 2) + 1] | (mac[(i * 2)] << 8)); 620ca7111aSMatus Ujhelyi } 630ca7111aSMatus Ujhelyi } 640ca7111aSMatus Ujhelyi 650ca7111aSMatus Ujhelyi static int at803x_config_init(struct phy_device *phydev) 660ca7111aSMatus Ujhelyi { 670ca7111aSMatus Ujhelyi int val; 680ca7111aSMatus Ujhelyi u32 features; 690ca7111aSMatus Ujhelyi int status; 700ca7111aSMatus Ujhelyi 710ca7111aSMatus Ujhelyi features = SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI | 720ca7111aSMatus Ujhelyi SUPPORTED_FIBRE | SUPPORTED_BNC; 730ca7111aSMatus Ujhelyi 740ca7111aSMatus Ujhelyi val = phy_read(phydev, MII_BMSR); 750ca7111aSMatus Ujhelyi if (val < 0) 760ca7111aSMatus Ujhelyi return val; 770ca7111aSMatus Ujhelyi 780ca7111aSMatus Ujhelyi if (val & BMSR_ANEGCAPABLE) 790ca7111aSMatus Ujhelyi features |= SUPPORTED_Autoneg; 800ca7111aSMatus Ujhelyi if (val & BMSR_100FULL) 810ca7111aSMatus Ujhelyi features |= SUPPORTED_100baseT_Full; 820ca7111aSMatus Ujhelyi if (val & BMSR_100HALF) 830ca7111aSMatus Ujhelyi features |= SUPPORTED_100baseT_Half; 840ca7111aSMatus Ujhelyi if (val & BMSR_10FULL) 850ca7111aSMatus Ujhelyi features |= SUPPORTED_10baseT_Full; 860ca7111aSMatus Ujhelyi if (val & BMSR_10HALF) 870ca7111aSMatus Ujhelyi features |= SUPPORTED_10baseT_Half; 880ca7111aSMatus Ujhelyi 890ca7111aSMatus Ujhelyi if (val & BMSR_ESTATEN) { 900ca7111aSMatus Ujhelyi val = phy_read(phydev, MII_ESTATUS); 910ca7111aSMatus Ujhelyi if (val < 0) 920ca7111aSMatus Ujhelyi return val; 930ca7111aSMatus Ujhelyi 940ca7111aSMatus Ujhelyi if (val & ESTATUS_1000_TFULL) 950ca7111aSMatus Ujhelyi features |= SUPPORTED_1000baseT_Full; 960ca7111aSMatus Ujhelyi if (val & ESTATUS_1000_THALF) 970ca7111aSMatus Ujhelyi features |= SUPPORTED_1000baseT_Half; 980ca7111aSMatus Ujhelyi } 990ca7111aSMatus Ujhelyi 1000ca7111aSMatus Ujhelyi phydev->supported = features; 1010ca7111aSMatus Ujhelyi phydev->advertising = features; 1020ca7111aSMatus Ujhelyi 1030ca7111aSMatus Ujhelyi /* enable WOL */ 1040ca7111aSMatus Ujhelyi at803x_set_wol_mac_addr(phydev); 1050ca7111aSMatus Ujhelyi status = phy_write(phydev, AT803X_INTR_ENABLE, AT803X_WOL_ENABLE); 1060ca7111aSMatus Ujhelyi status = phy_read(phydev, AT803X_INTR_STATUS); 1070ca7111aSMatus Ujhelyi 1080ca7111aSMatus Ujhelyi return 0; 1090ca7111aSMatus Ujhelyi } 1100ca7111aSMatus Ujhelyi 1110ca7111aSMatus Ujhelyi /* ATHEROS 8035 */ 1120ca7111aSMatus Ujhelyi static struct phy_driver at8035_driver = { 1130ca7111aSMatus Ujhelyi .phy_id = 0x004dd072, 1140ca7111aSMatus Ujhelyi .name = "Atheros 8035 ethernet", 1150ca7111aSMatus Ujhelyi .phy_id_mask = 0xffffffef, 1160ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 1170ca7111aSMatus Ujhelyi .features = PHY_GBIT_FEATURES, 1180ca7111aSMatus Ujhelyi .flags = PHY_HAS_INTERRUPT, 1190ca7111aSMatus Ujhelyi .config_aneg = &genphy_config_aneg, 1200ca7111aSMatus Ujhelyi .read_status = &genphy_read_status, 1210ca7111aSMatus Ujhelyi .driver = { 1220ca7111aSMatus Ujhelyi .owner = THIS_MODULE, 1230ca7111aSMatus Ujhelyi }, 1240ca7111aSMatus Ujhelyi }; 1250ca7111aSMatus Ujhelyi 1260ca7111aSMatus Ujhelyi /* ATHEROS 8030 */ 1270ca7111aSMatus Ujhelyi static struct phy_driver at8030_driver = { 1280ca7111aSMatus Ujhelyi .phy_id = 0x004dd076, 1290ca7111aSMatus Ujhelyi .name = "Atheros 8030 ethernet", 1300ca7111aSMatus Ujhelyi .phy_id_mask = 0xffffffef, 1310ca7111aSMatus Ujhelyi .config_init = at803x_config_init, 1320ca7111aSMatus Ujhelyi .features = PHY_GBIT_FEATURES, 1330ca7111aSMatus Ujhelyi .flags = PHY_HAS_INTERRUPT, 1340ca7111aSMatus Ujhelyi .config_aneg = &genphy_config_aneg, 1350ca7111aSMatus Ujhelyi .read_status = &genphy_read_status, 1360ca7111aSMatus Ujhelyi .driver = { 1370ca7111aSMatus Ujhelyi .owner = THIS_MODULE, 1380ca7111aSMatus Ujhelyi }, 1390ca7111aSMatus Ujhelyi }; 1400ca7111aSMatus Ujhelyi 1410ca7111aSMatus Ujhelyi static int __init atheros_init(void) 1420ca7111aSMatus Ujhelyi { 1430ca7111aSMatus Ujhelyi int ret; 1440ca7111aSMatus Ujhelyi 1450ca7111aSMatus Ujhelyi ret = phy_driver_register(&at8035_driver); 1460ca7111aSMatus Ujhelyi if (ret) 1470ca7111aSMatus Ujhelyi goto err1; 1480ca7111aSMatus Ujhelyi 1490ca7111aSMatus Ujhelyi ret = phy_driver_register(&at8030_driver); 1500ca7111aSMatus Ujhelyi if (ret) 1510ca7111aSMatus Ujhelyi goto err2; 1520ca7111aSMatus Ujhelyi 1530ca7111aSMatus Ujhelyi return 0; 1540ca7111aSMatus Ujhelyi 1550ca7111aSMatus Ujhelyi err2: 1560ca7111aSMatus Ujhelyi phy_driver_unregister(&at8035_driver); 1570ca7111aSMatus Ujhelyi err1: 1580ca7111aSMatus Ujhelyi return ret; 1590ca7111aSMatus Ujhelyi } 1600ca7111aSMatus Ujhelyi 1610ca7111aSMatus Ujhelyi static void __exit atheros_exit(void) 1620ca7111aSMatus Ujhelyi { 1630ca7111aSMatus Ujhelyi phy_driver_unregister(&at8035_driver); 1640ca7111aSMatus Ujhelyi phy_driver_unregister(&at8030_driver); 1650ca7111aSMatus Ujhelyi } 1660ca7111aSMatus Ujhelyi 1670ca7111aSMatus Ujhelyi module_init(atheros_init); 1680ca7111aSMatus Ujhelyi module_exit(atheros_exit); 1690ca7111aSMatus Ujhelyi 1700ca7111aSMatus Ujhelyi static struct mdio_device_id __maybe_unused atheros_tbl[] = { 1710ca7111aSMatus Ujhelyi { 0x004dd076, 0xffffffef }, 1720ca7111aSMatus Ujhelyi { 0x004dd072, 0xffffffef }, 1730ca7111aSMatus Ujhelyi { } 1740ca7111aSMatus Ujhelyi }; 1750ca7111aSMatus Ujhelyi 1760ca7111aSMatus Ujhelyi MODULE_DEVICE_TABLE(mdio, atheros_tbl); 177