1 /* 2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 3 * DWC Ether MAC version 4.xx has been used for developing this code. 4 * 5 * This contains the functions to handle the dma. 6 * 7 * Copyright (C) 2015 STMicroelectronics Ltd 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * Author: Alexandre Torgue <alexandre.torgue@st.com> 14 */ 15 16 #include <linux/io.h> 17 #include "dwmac4.h" 18 #include "dwmac4_dma.h" 19 20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 21 { 22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 23 int i; 24 25 pr_info("dwmac4: Master AXI performs %s burst length\n", 26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 27 28 if (axi->axi_lpi_en) 29 value |= DMA_AXI_EN_LPI; 30 if (axi->axi_xit_frm) 31 value |= DMA_AXI_LPI_XIT_FRM; 32 33 value &= ~DMA_AXI_WR_OSR_LMT; 34 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 35 DMA_AXI_WR_OSR_LMT_SHIFT; 36 37 value &= ~DMA_AXI_RD_OSR_LMT; 38 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 39 DMA_AXI_RD_OSR_LMT_SHIFT; 40 41 /* Depending on the UNDEF bit the Master AXI will perform any burst 42 * length according to the BLEN programmed (by default all BLEN are 43 * set). 44 */ 45 for (i = 0; i < AXI_BLEN; i++) { 46 switch (axi->axi_blen[i]) { 47 case 256: 48 value |= DMA_AXI_BLEN256; 49 break; 50 case 128: 51 value |= DMA_AXI_BLEN128; 52 break; 53 case 64: 54 value |= DMA_AXI_BLEN64; 55 break; 56 case 32: 57 value |= DMA_AXI_BLEN32; 58 break; 59 case 16: 60 value |= DMA_AXI_BLEN16; 61 break; 62 case 8: 63 value |= DMA_AXI_BLEN8; 64 break; 65 case 4: 66 value |= DMA_AXI_BLEN4; 67 break; 68 } 69 } 70 71 writel(value, ioaddr + DMA_SYS_BUS_MODE); 72 } 73 74 static void dwmac4_dma_init_channel(void __iomem *ioaddr, 75 struct stmmac_dma_cfg *dma_cfg, 76 u32 dma_tx_phy, u32 dma_rx_phy, 77 u32 channel) 78 { 79 u32 value; 80 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 81 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 82 83 /* set PBL for each channels. Currently we affect same configuration 84 * on each channel 85 */ 86 value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 87 if (dma_cfg->pblx8) 88 value = value | DMA_BUS_MODE_PBL; 89 writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 90 91 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 92 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 93 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 94 95 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 96 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 97 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 98 99 /* Mask interrupts by writing to CSR7 */ 100 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 101 102 writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 103 writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 104 } 105 106 static void dwmac4_dma_init(void __iomem *ioaddr, 107 struct stmmac_dma_cfg *dma_cfg, 108 u32 dma_tx, u32 dma_rx, int atds) 109 { 110 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 111 int i; 112 113 /* Set the Fixed burst mode */ 114 if (dma_cfg->fixed_burst) 115 value |= DMA_SYS_BUS_FB; 116 117 /* Mixed Burst has no effect when fb is set */ 118 if (dma_cfg->mixed_burst) 119 value |= DMA_SYS_BUS_MB; 120 121 if (dma_cfg->aal) 122 value |= DMA_SYS_BUS_AAL; 123 124 writel(value, ioaddr + DMA_SYS_BUS_MODE); 125 126 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 127 dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i); 128 } 129 130 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 131 u32 *reg_space) 132 { 133 reg_space[DMA_CHAN_CONTROL(channel) / 4] = 134 readl(ioaddr + DMA_CHAN_CONTROL(channel)); 135 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 136 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 137 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 138 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 139 reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 140 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 141 reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 142 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 143 reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 144 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 145 reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 146 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 147 reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 148 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 149 reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 150 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 151 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 152 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 153 reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 154 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 155 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 156 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 157 reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 158 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 159 reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 160 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 161 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 162 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 163 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 164 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 165 reg_space[DMA_CHAN_STATUS(channel) / 4] = 166 readl(ioaddr + DMA_CHAN_STATUS(channel)); 167 } 168 169 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 170 { 171 int i; 172 173 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 174 _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 175 } 176 177 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 178 { 179 int i; 180 181 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 182 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 183 } 184 185 static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, 186 int rxmode, u32 channel) 187 { 188 u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; 189 190 /* Following code only done for channel 0, other channels not yet 191 * supported. 192 */ 193 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 194 195 if (txmode == SF_DMA_MODE) { 196 pr_debug("GMAC: enable TX store and forward mode\n"); 197 /* Transmit COE type 2 cannot be done in cut-through mode. */ 198 mtl_tx_op |= MTL_OP_MODE_TSF; 199 } else { 200 pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode); 201 mtl_tx_op &= ~MTL_OP_MODE_TSF; 202 mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 203 /* Set the transmit threshold */ 204 if (txmode <= 32) 205 mtl_tx_op |= MTL_OP_MODE_TTC_32; 206 else if (txmode <= 64) 207 mtl_tx_op |= MTL_OP_MODE_TTC_64; 208 else if (txmode <= 96) 209 mtl_tx_op |= MTL_OP_MODE_TTC_96; 210 else if (txmode <= 128) 211 mtl_tx_op |= MTL_OP_MODE_TTC_128; 212 else if (txmode <= 192) 213 mtl_tx_op |= MTL_OP_MODE_TTC_192; 214 else if (txmode <= 256) 215 mtl_tx_op |= MTL_OP_MODE_TTC_256; 216 else if (txmode <= 384) 217 mtl_tx_op |= MTL_OP_MODE_TTC_384; 218 else 219 mtl_tx_op |= MTL_OP_MODE_TTC_512; 220 } 221 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 222 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 223 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 224 * with reset values: TXQEN off, TQS 256 bytes. 225 * 226 * Write the bits in both cases, since it will have no effect when RO. 227 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 228 * be RO, however, writing the whole TQS field will result in a value 229 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 230 */ 231 mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 232 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 233 234 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 235 236 if (rxmode == SF_DMA_MODE) { 237 pr_debug("GMAC: enable RX store and forward mode\n"); 238 mtl_rx_op |= MTL_OP_MODE_RSF; 239 } else { 240 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode); 241 mtl_rx_op &= ~MTL_OP_MODE_RSF; 242 mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 243 if (rxmode <= 32) 244 mtl_rx_op |= MTL_OP_MODE_RTC_32; 245 else if (rxmode <= 64) 246 mtl_rx_op |= MTL_OP_MODE_RTC_64; 247 else if (rxmode <= 96) 248 mtl_rx_op |= MTL_OP_MODE_RTC_96; 249 else 250 mtl_rx_op |= MTL_OP_MODE_RTC_128; 251 } 252 253 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 254 255 /* Enable MTL RX overflow */ 256 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 257 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 258 ioaddr + MTL_CHAN_INT_CTRL(channel)); 259 } 260 261 static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, 262 int rxmode, int rxfifosz) 263 { 264 /* Only Channel 0 is actually configured and used */ 265 dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0); 266 } 267 268 static void dwmac4_get_hw_feature(void __iomem *ioaddr, 269 struct dma_features *dma_cap) 270 { 271 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 272 273 /* MAC HW feature0 */ 274 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 275 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 276 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 277 dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 278 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 279 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 280 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 281 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 282 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 283 /* MMC */ 284 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 285 /* IEEE 1588-2008 */ 286 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 287 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 288 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 289 /* TX and RX csum */ 290 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 291 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 292 293 /* MAC HW feature1 */ 294 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 295 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 296 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 297 /* MAC HW feature2 */ 298 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 299 /* TX and RX number of channels */ 300 dma_cap->number_rx_channel = 301 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 302 dma_cap->number_tx_channel = 303 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 304 /* TX and RX number of queues */ 305 dma_cap->number_rx_queues = 306 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 307 dma_cap->number_tx_queues = 308 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 309 310 /* IEEE 1588-2002 */ 311 dma_cap->time_stamp = 0; 312 } 313 314 /* Enable/disable TSO feature and set MSS */ 315 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 316 { 317 u32 value; 318 319 if (en) { 320 /* enable TSO */ 321 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 322 writel(value | DMA_CONTROL_TSE, 323 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 324 } else { 325 /* enable TSO */ 326 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 327 writel(value & ~DMA_CONTROL_TSE, 328 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 329 } 330 } 331 332 const struct stmmac_dma_ops dwmac4_dma_ops = { 333 .reset = dwmac4_dma_reset, 334 .init = dwmac4_dma_init, 335 .axi = dwmac4_dma_axi, 336 .dump_regs = dwmac4_dump_dma_regs, 337 .dma_mode = dwmac4_dma_operation_mode, 338 .enable_dma_irq = dwmac4_enable_dma_irq, 339 .disable_dma_irq = dwmac4_disable_dma_irq, 340 .start_tx = dwmac4_dma_start_tx, 341 .stop_tx = dwmac4_dma_stop_tx, 342 .start_rx = dwmac4_dma_start_rx, 343 .stop_rx = dwmac4_dma_stop_rx, 344 .dma_interrupt = dwmac4_dma_interrupt, 345 .get_hw_feature = dwmac4_get_hw_feature, 346 .rx_watchdog = dwmac4_rx_watchdog, 347 .set_rx_ring_len = dwmac4_set_rx_ring_len, 348 .set_tx_ring_len = dwmac4_set_tx_ring_len, 349 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 350 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 351 .enable_tso = dwmac4_enable_tso, 352 }; 353 354 const struct stmmac_dma_ops dwmac410_dma_ops = { 355 .reset = dwmac4_dma_reset, 356 .init = dwmac4_dma_init, 357 .axi = dwmac4_dma_axi, 358 .dump_regs = dwmac4_dump_dma_regs, 359 .dma_mode = dwmac4_dma_operation_mode, 360 .enable_dma_irq = dwmac410_enable_dma_irq, 361 .disable_dma_irq = dwmac4_disable_dma_irq, 362 .start_tx = dwmac4_dma_start_tx, 363 .stop_tx = dwmac4_dma_stop_tx, 364 .start_rx = dwmac4_dma_start_rx, 365 .stop_rx = dwmac4_dma_stop_rx, 366 .dma_interrupt = dwmac4_dma_interrupt, 367 .get_hw_feature = dwmac4_get_hw_feature, 368 .rx_watchdog = dwmac4_rx_watchdog, 369 .set_rx_ring_len = dwmac4_set_rx_ring_len, 370 .set_tx_ring_len = dwmac4_set_tx_ring_len, 371 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 372 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 373 .enable_tso = dwmac4_enable_tso, 374 }; 375