1 /* 2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 3 * DWC Ether MAC version 4.xx has been used for developing this code. 4 * 5 * This contains the functions to handle the dma. 6 * 7 * Copyright (C) 2015 STMicroelectronics Ltd 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * Author: Alexandre Torgue <alexandre.torgue@st.com> 14 */ 15 16 #include <linux/io.h> 17 #include "dwmac4.h" 18 #include "dwmac4_dma.h" 19 20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 21 { 22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 23 int i; 24 25 pr_info("dwmac4: Master AXI performs %s burst length\n", 26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 27 28 if (axi->axi_lpi_en) 29 value |= DMA_AXI_EN_LPI; 30 if (axi->axi_xit_frm) 31 value |= DMA_AXI_LPI_XIT_FRM; 32 33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 34 DMA_AXI_WR_OSR_LMT_SHIFT; 35 36 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 37 DMA_AXI_RD_OSR_LMT_SHIFT; 38 39 /* Depending on the UNDEF bit the Master AXI will perform any burst 40 * length according to the BLEN programmed (by default all BLEN are 41 * set). 42 */ 43 for (i = 0; i < AXI_BLEN; i++) { 44 switch (axi->axi_blen[i]) { 45 case 256: 46 value |= DMA_AXI_BLEN256; 47 break; 48 case 128: 49 value |= DMA_AXI_BLEN128; 50 break; 51 case 64: 52 value |= DMA_AXI_BLEN64; 53 break; 54 case 32: 55 value |= DMA_AXI_BLEN32; 56 break; 57 case 16: 58 value |= DMA_AXI_BLEN16; 59 break; 60 case 8: 61 value |= DMA_AXI_BLEN8; 62 break; 63 case 4: 64 value |= DMA_AXI_BLEN4; 65 break; 66 } 67 } 68 69 writel(value, ioaddr + DMA_SYS_BUS_MODE); 70 } 71 72 static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl, 73 u32 dma_tx_phy, u32 dma_rx_phy, 74 u32 channel) 75 { 76 u32 value; 77 78 /* set PBL for each channels. Currently we affect same configuration 79 * on each channel 80 */ 81 value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 82 value = value | DMA_BUS_MODE_PBL; 83 writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 84 85 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 86 value = value | (pbl << DMA_BUS_MODE_PBL_SHIFT); 87 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 88 89 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 90 value = value | (pbl << DMA_BUS_MODE_RPBL_SHIFT); 91 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 92 93 /* Mask interrupts by writing to CSR7 */ 94 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 95 96 writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 97 writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 98 } 99 100 static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, 101 int aal, u32 dma_tx, u32 dma_rx, int atds) 102 { 103 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 104 int i; 105 106 /* Set the Fixed burst mode */ 107 if (fb) 108 value |= DMA_SYS_BUS_FB; 109 110 /* Mixed Burst has no effect when fb is set */ 111 if (mb) 112 value |= DMA_SYS_BUS_MB; 113 114 if (aal) 115 value |= DMA_SYS_BUS_AAL; 116 117 writel(value, ioaddr + DMA_SYS_BUS_MODE); 118 119 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 120 dwmac4_dma_init_channel(ioaddr, pbl, dma_tx, dma_rx, i); 121 } 122 123 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel) 124 { 125 pr_debug(" Channel %d\n", channel); 126 pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0, 127 readl(ioaddr + DMA_CHAN_CONTROL(channel))); 128 pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4, 129 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel))); 130 pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8, 131 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel))); 132 pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14, 133 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel))); 134 pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c, 135 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel))); 136 pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20, 137 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel))); 138 pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28, 139 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel))); 140 pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c, 141 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel))); 142 pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30, 143 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel))); 144 pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34, 145 readl(ioaddr + DMA_CHAN_INTR_ENA(channel))); 146 pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38, 147 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel))); 148 pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c, 149 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel))); 150 pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44, 151 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel))); 152 pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c, 153 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel))); 154 pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54, 155 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel))); 156 pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c, 157 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel))); 158 pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60, 159 readl(ioaddr + DMA_CHAN_STATUS(channel))); 160 } 161 162 static void dwmac4_dump_dma_regs(void __iomem *ioaddr) 163 { 164 int i; 165 166 pr_debug(" GMAC4 DMA registers\n"); 167 168 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 169 _dwmac4_dump_dma_regs(ioaddr, i); 170 } 171 172 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 173 { 174 int i; 175 176 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 177 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 178 } 179 180 static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, 181 int rxmode, u32 channel) 182 { 183 u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; 184 185 /* Following code only done for channel 0, other channels not yet 186 * supported. 187 */ 188 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 189 190 if (txmode == SF_DMA_MODE) { 191 pr_debug("GMAC: enable TX store and forward mode\n"); 192 /* Transmit COE type 2 cannot be done in cut-through mode. */ 193 mtl_tx_op |= MTL_OP_MODE_TSF; 194 } else { 195 pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode); 196 mtl_tx_op &= ~MTL_OP_MODE_TSF; 197 mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 198 /* Set the transmit threshold */ 199 if (txmode <= 32) 200 mtl_tx_op |= MTL_OP_MODE_TTC_32; 201 else if (txmode <= 64) 202 mtl_tx_op |= MTL_OP_MODE_TTC_64; 203 else if (txmode <= 96) 204 mtl_tx_op |= MTL_OP_MODE_TTC_96; 205 else if (txmode <= 128) 206 mtl_tx_op |= MTL_OP_MODE_TTC_128; 207 else if (txmode <= 192) 208 mtl_tx_op |= MTL_OP_MODE_TTC_192; 209 else if (txmode <= 256) 210 mtl_tx_op |= MTL_OP_MODE_TTC_256; 211 else if (txmode <= 384) 212 mtl_tx_op |= MTL_OP_MODE_TTC_384; 213 else 214 mtl_tx_op |= MTL_OP_MODE_TTC_512; 215 } 216 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 217 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 218 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 219 * with reset values: TXQEN off, TQS 256 bytes. 220 * 221 * Write the bits in both cases, since it will have no effect when RO. 222 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 223 * be RO, however, writing the whole TQS field will result in a value 224 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 225 */ 226 mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 227 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 228 229 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 230 231 if (rxmode == SF_DMA_MODE) { 232 pr_debug("GMAC: enable RX store and forward mode\n"); 233 mtl_rx_op |= MTL_OP_MODE_RSF; 234 } else { 235 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode); 236 mtl_rx_op &= ~MTL_OP_MODE_RSF; 237 mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 238 if (rxmode <= 32) 239 mtl_rx_op |= MTL_OP_MODE_RTC_32; 240 else if (rxmode <= 64) 241 mtl_rx_op |= MTL_OP_MODE_RTC_64; 242 else if (rxmode <= 96) 243 mtl_rx_op |= MTL_OP_MODE_RTC_96; 244 else 245 mtl_rx_op |= MTL_OP_MODE_RTC_128; 246 } 247 248 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 249 250 /* Enable MTL RX overflow */ 251 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 252 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 253 ioaddr + MTL_CHAN_INT_CTRL(channel)); 254 } 255 256 static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, 257 int rxmode, int rxfifosz) 258 { 259 /* Only Channel 0 is actually configured and used */ 260 dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0); 261 } 262 263 static void dwmac4_get_hw_feature(void __iomem *ioaddr, 264 struct dma_features *dma_cap) 265 { 266 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 267 268 /* MAC HW feature0 */ 269 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 270 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 271 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 272 dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 273 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 274 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 275 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 276 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 277 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 278 /* MMC */ 279 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 280 /* IEEE 1588-2008 */ 281 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 282 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 283 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 284 /* TX and RX csum */ 285 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 286 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 287 288 /* MAC HW feature1 */ 289 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 290 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 291 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 292 /* MAC HW feature2 */ 293 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 294 /* TX and RX number of channels */ 295 dma_cap->number_rx_channel = 296 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 297 dma_cap->number_tx_channel = 298 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 299 300 /* IEEE 1588-2002 */ 301 dma_cap->time_stamp = 0; 302 } 303 304 /* Enable/disable TSO feature and set MSS */ 305 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 306 { 307 u32 value; 308 309 if (en) { 310 /* enable TSO */ 311 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 312 writel(value | DMA_CONTROL_TSE, 313 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 314 } else { 315 /* enable TSO */ 316 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 317 writel(value & ~DMA_CONTROL_TSE, 318 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 319 } 320 } 321 322 const struct stmmac_dma_ops dwmac4_dma_ops = { 323 .reset = dwmac4_dma_reset, 324 .init = dwmac4_dma_init, 325 .axi = dwmac4_dma_axi, 326 .dump_regs = dwmac4_dump_dma_regs, 327 .dma_mode = dwmac4_dma_operation_mode, 328 .enable_dma_irq = dwmac4_enable_dma_irq, 329 .disable_dma_irq = dwmac4_disable_dma_irq, 330 .start_tx = dwmac4_dma_start_tx, 331 .stop_tx = dwmac4_dma_stop_tx, 332 .start_rx = dwmac4_dma_start_rx, 333 .stop_rx = dwmac4_dma_stop_rx, 334 .dma_interrupt = dwmac4_dma_interrupt, 335 .get_hw_feature = dwmac4_get_hw_feature, 336 .rx_watchdog = dwmac4_rx_watchdog, 337 .set_rx_ring_len = dwmac4_set_rx_ring_len, 338 .set_tx_ring_len = dwmac4_set_tx_ring_len, 339 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 340 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 341 .enable_tso = dwmac4_enable_tso, 342 }; 343 344 const struct stmmac_dma_ops dwmac410_dma_ops = { 345 .reset = dwmac4_dma_reset, 346 .init = dwmac4_dma_init, 347 .axi = dwmac4_dma_axi, 348 .dump_regs = dwmac4_dump_dma_regs, 349 .dma_mode = dwmac4_dma_operation_mode, 350 .enable_dma_irq = dwmac410_enable_dma_irq, 351 .disable_dma_irq = dwmac4_disable_dma_irq, 352 .start_tx = dwmac4_dma_start_tx, 353 .stop_tx = dwmac4_dma_stop_tx, 354 .start_rx = dwmac4_dma_start_rx, 355 .stop_rx = dwmac4_dma_stop_rx, 356 .dma_interrupt = dwmac4_dma_interrupt, 357 .get_hw_feature = dwmac4_get_hw_feature, 358 .rx_watchdog = dwmac4_rx_watchdog, 359 .set_rx_ring_len = dwmac4_set_rx_ring_len, 360 .set_tx_ring_len = dwmac4_set_tx_ring_len, 361 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 362 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 363 .enable_tso = dwmac4_enable_tso, 364 }; 365