1 /* 2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 3 * DWC Ether MAC version 4.xx has been used for developing this code. 4 * 5 * This contains the functions to handle the dma. 6 * 7 * Copyright (C) 2015 STMicroelectronics Ltd 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * Author: Alexandre Torgue <alexandre.torgue@st.com> 14 */ 15 16 #include <linux/io.h> 17 #include "dwmac4.h" 18 #include "dwmac4_dma.h" 19 20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 21 { 22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 23 int i; 24 25 pr_info("dwmac4: Master AXI performs %s burst length\n", 26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 27 28 if (axi->axi_lpi_en) 29 value |= DMA_AXI_EN_LPI; 30 if (axi->axi_xit_frm) 31 value |= DMA_AXI_LPI_XIT_FRM; 32 33 value &= ~DMA_AXI_WR_OSR_LMT; 34 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 35 DMA_AXI_WR_OSR_LMT_SHIFT; 36 37 value &= ~DMA_AXI_RD_OSR_LMT; 38 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 39 DMA_AXI_RD_OSR_LMT_SHIFT; 40 41 /* Depending on the UNDEF bit the Master AXI will perform any burst 42 * length according to the BLEN programmed (by default all BLEN are 43 * set). 44 */ 45 for (i = 0; i < AXI_BLEN; i++) { 46 switch (axi->axi_blen[i]) { 47 case 256: 48 value |= DMA_AXI_BLEN256; 49 break; 50 case 128: 51 value |= DMA_AXI_BLEN128; 52 break; 53 case 64: 54 value |= DMA_AXI_BLEN64; 55 break; 56 case 32: 57 value |= DMA_AXI_BLEN32; 58 break; 59 case 16: 60 value |= DMA_AXI_BLEN16; 61 break; 62 case 8: 63 value |= DMA_AXI_BLEN8; 64 break; 65 case 4: 66 value |= DMA_AXI_BLEN4; 67 break; 68 } 69 } 70 71 writel(value, ioaddr + DMA_SYS_BUS_MODE); 72 } 73 74 static void dwmac4_dma_init_channel(void __iomem *ioaddr, 75 struct stmmac_dma_cfg *dma_cfg, 76 u32 dma_tx_phy, u32 dma_rx_phy, 77 u32 channel) 78 { 79 u32 value; 80 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 81 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 82 83 /* set PBL for each channels. Currently we affect same configuration 84 * on each channel 85 */ 86 value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 87 if (dma_cfg->pblx8) 88 value = value | DMA_BUS_MODE_PBL; 89 writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 90 91 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 92 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 93 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 94 95 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 96 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 97 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 98 99 /* Mask interrupts by writing to CSR7 */ 100 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 101 102 writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 103 writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 104 } 105 106 static void dwmac4_dma_init(void __iomem *ioaddr, 107 struct stmmac_dma_cfg *dma_cfg, 108 u32 dma_tx, u32 dma_rx, int atds) 109 { 110 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 111 int i; 112 113 /* Set the Fixed burst mode */ 114 if (dma_cfg->fixed_burst) 115 value |= DMA_SYS_BUS_FB; 116 117 /* Mixed Burst has no effect when fb is set */ 118 if (dma_cfg->mixed_burst) 119 value |= DMA_SYS_BUS_MB; 120 121 if (dma_cfg->aal) 122 value |= DMA_SYS_BUS_AAL; 123 124 writel(value, ioaddr + DMA_SYS_BUS_MODE); 125 126 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 127 dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i); 128 } 129 130 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel) 131 { 132 pr_debug(" Channel %d\n", channel); 133 pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0, 134 readl(ioaddr + DMA_CHAN_CONTROL(channel))); 135 pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4, 136 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel))); 137 pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8, 138 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel))); 139 pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14, 140 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel))); 141 pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c, 142 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel))); 143 pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20, 144 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel))); 145 pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28, 146 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel))); 147 pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c, 148 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel))); 149 pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30, 150 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel))); 151 pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34, 152 readl(ioaddr + DMA_CHAN_INTR_ENA(channel))); 153 pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38, 154 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel))); 155 pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c, 156 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel))); 157 pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44, 158 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel))); 159 pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c, 160 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel))); 161 pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54, 162 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel))); 163 pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c, 164 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel))); 165 pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60, 166 readl(ioaddr + DMA_CHAN_STATUS(channel))); 167 } 168 169 static void dwmac4_dump_dma_regs(void __iomem *ioaddr) 170 { 171 int i; 172 173 pr_debug(" GMAC4 DMA registers\n"); 174 175 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 176 _dwmac4_dump_dma_regs(ioaddr, i); 177 } 178 179 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 180 { 181 int i; 182 183 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 184 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 185 } 186 187 static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, 188 int rxmode, u32 channel) 189 { 190 u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; 191 192 /* Following code only done for channel 0, other channels not yet 193 * supported. 194 */ 195 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 196 197 if (txmode == SF_DMA_MODE) { 198 pr_debug("GMAC: enable TX store and forward mode\n"); 199 /* Transmit COE type 2 cannot be done in cut-through mode. */ 200 mtl_tx_op |= MTL_OP_MODE_TSF; 201 } else { 202 pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode); 203 mtl_tx_op &= ~MTL_OP_MODE_TSF; 204 mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 205 /* Set the transmit threshold */ 206 if (txmode <= 32) 207 mtl_tx_op |= MTL_OP_MODE_TTC_32; 208 else if (txmode <= 64) 209 mtl_tx_op |= MTL_OP_MODE_TTC_64; 210 else if (txmode <= 96) 211 mtl_tx_op |= MTL_OP_MODE_TTC_96; 212 else if (txmode <= 128) 213 mtl_tx_op |= MTL_OP_MODE_TTC_128; 214 else if (txmode <= 192) 215 mtl_tx_op |= MTL_OP_MODE_TTC_192; 216 else if (txmode <= 256) 217 mtl_tx_op |= MTL_OP_MODE_TTC_256; 218 else if (txmode <= 384) 219 mtl_tx_op |= MTL_OP_MODE_TTC_384; 220 else 221 mtl_tx_op |= MTL_OP_MODE_TTC_512; 222 } 223 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 224 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 225 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 226 * with reset values: TXQEN off, TQS 256 bytes. 227 * 228 * Write the bits in both cases, since it will have no effect when RO. 229 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 230 * be RO, however, writing the whole TQS field will result in a value 231 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 232 */ 233 mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 234 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 235 236 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 237 238 if (rxmode == SF_DMA_MODE) { 239 pr_debug("GMAC: enable RX store and forward mode\n"); 240 mtl_rx_op |= MTL_OP_MODE_RSF; 241 } else { 242 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode); 243 mtl_rx_op &= ~MTL_OP_MODE_RSF; 244 mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 245 if (rxmode <= 32) 246 mtl_rx_op |= MTL_OP_MODE_RTC_32; 247 else if (rxmode <= 64) 248 mtl_rx_op |= MTL_OP_MODE_RTC_64; 249 else if (rxmode <= 96) 250 mtl_rx_op |= MTL_OP_MODE_RTC_96; 251 else 252 mtl_rx_op |= MTL_OP_MODE_RTC_128; 253 } 254 255 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 256 257 /* Enable MTL RX overflow */ 258 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 259 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 260 ioaddr + MTL_CHAN_INT_CTRL(channel)); 261 } 262 263 static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, 264 int rxmode, int rxfifosz) 265 { 266 /* Only Channel 0 is actually configured and used */ 267 dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0); 268 } 269 270 static void dwmac4_get_hw_feature(void __iomem *ioaddr, 271 struct dma_features *dma_cap) 272 { 273 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 274 275 /* MAC HW feature0 */ 276 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 277 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 278 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 279 dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 280 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 281 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 282 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 283 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 284 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 285 /* MMC */ 286 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 287 /* IEEE 1588-2008 */ 288 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 289 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 290 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 291 /* TX and RX csum */ 292 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 293 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 294 295 /* MAC HW feature1 */ 296 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 297 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 298 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 299 /* MAC HW feature2 */ 300 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 301 /* TX and RX number of channels */ 302 dma_cap->number_rx_channel = 303 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 304 dma_cap->number_tx_channel = 305 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 306 307 /* IEEE 1588-2002 */ 308 dma_cap->time_stamp = 0; 309 } 310 311 /* Enable/disable TSO feature and set MSS */ 312 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 313 { 314 u32 value; 315 316 if (en) { 317 /* enable TSO */ 318 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 319 writel(value | DMA_CONTROL_TSE, 320 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 321 } else { 322 /* enable TSO */ 323 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 324 writel(value & ~DMA_CONTROL_TSE, 325 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 326 } 327 } 328 329 const struct stmmac_dma_ops dwmac4_dma_ops = { 330 .reset = dwmac4_dma_reset, 331 .init = dwmac4_dma_init, 332 .axi = dwmac4_dma_axi, 333 .dump_regs = dwmac4_dump_dma_regs, 334 .dma_mode = dwmac4_dma_operation_mode, 335 .enable_dma_irq = dwmac4_enable_dma_irq, 336 .disable_dma_irq = dwmac4_disable_dma_irq, 337 .start_tx = dwmac4_dma_start_tx, 338 .stop_tx = dwmac4_dma_stop_tx, 339 .start_rx = dwmac4_dma_start_rx, 340 .stop_rx = dwmac4_dma_stop_rx, 341 .dma_interrupt = dwmac4_dma_interrupt, 342 .get_hw_feature = dwmac4_get_hw_feature, 343 .rx_watchdog = dwmac4_rx_watchdog, 344 .set_rx_ring_len = dwmac4_set_rx_ring_len, 345 .set_tx_ring_len = dwmac4_set_tx_ring_len, 346 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 347 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 348 .enable_tso = dwmac4_enable_tso, 349 }; 350 351 const struct stmmac_dma_ops dwmac410_dma_ops = { 352 .reset = dwmac4_dma_reset, 353 .init = dwmac4_dma_init, 354 .axi = dwmac4_dma_axi, 355 .dump_regs = dwmac4_dump_dma_regs, 356 .dma_mode = dwmac4_dma_operation_mode, 357 .enable_dma_irq = dwmac410_enable_dma_irq, 358 .disable_dma_irq = dwmac4_disable_dma_irq, 359 .start_tx = dwmac4_dma_start_tx, 360 .stop_tx = dwmac4_dma_stop_tx, 361 .start_rx = dwmac4_dma_start_rx, 362 .stop_rx = dwmac4_dma_stop_rx, 363 .dma_interrupt = dwmac4_dma_interrupt, 364 .get_hw_feature = dwmac4_get_hw_feature, 365 .rx_watchdog = dwmac4_rx_watchdog, 366 .set_rx_ring_len = dwmac4_set_rx_ring_len, 367 .set_tx_ring_len = dwmac4_set_tx_ring_len, 368 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 369 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 370 .enable_tso = dwmac4_enable_tso, 371 }; 372