1 /* 2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 3 * DWC Ether MAC version 4.xx has been used for developing this code. 4 * 5 * This contains the functions to handle the dma. 6 * 7 * Copyright (C) 2015 STMicroelectronics Ltd 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * Author: Alexandre Torgue <alexandre.torgue@st.com> 14 */ 15 16 #include <linux/io.h> 17 #include "dwmac4.h" 18 #include "dwmac4_dma.h" 19 20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 21 { 22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 23 int i; 24 25 pr_info("dwmac4: Master AXI performs %s burst length\n", 26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 27 28 if (axi->axi_lpi_en) 29 value |= DMA_AXI_EN_LPI; 30 if (axi->axi_xit_frm) 31 value |= DMA_AXI_LPI_XIT_FRM; 32 33 value &= ~DMA_AXI_WR_OSR_LMT; 34 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 35 DMA_AXI_WR_OSR_LMT_SHIFT; 36 37 value &= ~DMA_AXI_RD_OSR_LMT; 38 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 39 DMA_AXI_RD_OSR_LMT_SHIFT; 40 41 /* Depending on the UNDEF bit the Master AXI will perform any burst 42 * length according to the BLEN programmed (by default all BLEN are 43 * set). 44 */ 45 for (i = 0; i < AXI_BLEN; i++) { 46 switch (axi->axi_blen[i]) { 47 case 256: 48 value |= DMA_AXI_BLEN256; 49 break; 50 case 128: 51 value |= DMA_AXI_BLEN128; 52 break; 53 case 64: 54 value |= DMA_AXI_BLEN64; 55 break; 56 case 32: 57 value |= DMA_AXI_BLEN32; 58 break; 59 case 16: 60 value |= DMA_AXI_BLEN16; 61 break; 62 case 8: 63 value |= DMA_AXI_BLEN8; 64 break; 65 case 4: 66 value |= DMA_AXI_BLEN4; 67 break; 68 } 69 } 70 71 writel(value, ioaddr + DMA_SYS_BUS_MODE); 72 } 73 74 static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl, 75 u32 dma_tx_phy, u32 dma_rx_phy, 76 u32 channel) 77 { 78 u32 value; 79 80 /* set PBL for each channels. Currently we affect same configuration 81 * on each channel 82 */ 83 value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 84 value = value | DMA_BUS_MODE_PBL; 85 writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 86 87 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 88 value = value | (pbl << DMA_BUS_MODE_PBL_SHIFT); 89 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 90 91 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 92 value = value | (pbl << DMA_BUS_MODE_RPBL_SHIFT); 93 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 94 95 /* Mask interrupts by writing to CSR7 */ 96 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 97 98 writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 99 writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 100 } 101 102 static void dwmac4_dma_init(void __iomem *ioaddr, 103 struct stmmac_dma_cfg *dma_cfg, 104 u32 dma_tx, u32 dma_rx, int atds) 105 { 106 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 107 int i; 108 109 /* Set the Fixed burst mode */ 110 if (dma_cfg->fixed_burst) 111 value |= DMA_SYS_BUS_FB; 112 113 /* Mixed Burst has no effect when fb is set */ 114 if (dma_cfg->mixed_burst) 115 value |= DMA_SYS_BUS_MB; 116 117 if (dma_cfg->aal) 118 value |= DMA_SYS_BUS_AAL; 119 120 writel(value, ioaddr + DMA_SYS_BUS_MODE); 121 122 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 123 dwmac4_dma_init_channel(ioaddr, dma_cfg->pbl, 124 dma_tx, dma_rx, i); 125 } 126 127 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel) 128 { 129 pr_debug(" Channel %d\n", channel); 130 pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0, 131 readl(ioaddr + DMA_CHAN_CONTROL(channel))); 132 pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4, 133 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel))); 134 pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8, 135 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel))); 136 pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14, 137 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel))); 138 pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c, 139 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel))); 140 pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20, 141 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel))); 142 pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28, 143 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel))); 144 pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c, 145 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel))); 146 pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30, 147 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel))); 148 pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34, 149 readl(ioaddr + DMA_CHAN_INTR_ENA(channel))); 150 pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38, 151 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel))); 152 pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c, 153 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel))); 154 pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44, 155 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel))); 156 pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c, 157 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel))); 158 pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54, 159 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel))); 160 pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c, 161 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel))); 162 pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60, 163 readl(ioaddr + DMA_CHAN_STATUS(channel))); 164 } 165 166 static void dwmac4_dump_dma_regs(void __iomem *ioaddr) 167 { 168 int i; 169 170 pr_debug(" GMAC4 DMA registers\n"); 171 172 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 173 _dwmac4_dump_dma_regs(ioaddr, i); 174 } 175 176 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 177 { 178 int i; 179 180 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 181 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 182 } 183 184 static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, 185 int rxmode, u32 channel) 186 { 187 u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; 188 189 /* Following code only done for channel 0, other channels not yet 190 * supported. 191 */ 192 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 193 194 if (txmode == SF_DMA_MODE) { 195 pr_debug("GMAC: enable TX store and forward mode\n"); 196 /* Transmit COE type 2 cannot be done in cut-through mode. */ 197 mtl_tx_op |= MTL_OP_MODE_TSF; 198 } else { 199 pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode); 200 mtl_tx_op &= ~MTL_OP_MODE_TSF; 201 mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 202 /* Set the transmit threshold */ 203 if (txmode <= 32) 204 mtl_tx_op |= MTL_OP_MODE_TTC_32; 205 else if (txmode <= 64) 206 mtl_tx_op |= MTL_OP_MODE_TTC_64; 207 else if (txmode <= 96) 208 mtl_tx_op |= MTL_OP_MODE_TTC_96; 209 else if (txmode <= 128) 210 mtl_tx_op |= MTL_OP_MODE_TTC_128; 211 else if (txmode <= 192) 212 mtl_tx_op |= MTL_OP_MODE_TTC_192; 213 else if (txmode <= 256) 214 mtl_tx_op |= MTL_OP_MODE_TTC_256; 215 else if (txmode <= 384) 216 mtl_tx_op |= MTL_OP_MODE_TTC_384; 217 else 218 mtl_tx_op |= MTL_OP_MODE_TTC_512; 219 } 220 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 221 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 222 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 223 * with reset values: TXQEN off, TQS 256 bytes. 224 * 225 * Write the bits in both cases, since it will have no effect when RO. 226 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 227 * be RO, however, writing the whole TQS field will result in a value 228 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 229 */ 230 mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 231 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 232 233 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 234 235 if (rxmode == SF_DMA_MODE) { 236 pr_debug("GMAC: enable RX store and forward mode\n"); 237 mtl_rx_op |= MTL_OP_MODE_RSF; 238 } else { 239 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode); 240 mtl_rx_op &= ~MTL_OP_MODE_RSF; 241 mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 242 if (rxmode <= 32) 243 mtl_rx_op |= MTL_OP_MODE_RTC_32; 244 else if (rxmode <= 64) 245 mtl_rx_op |= MTL_OP_MODE_RTC_64; 246 else if (rxmode <= 96) 247 mtl_rx_op |= MTL_OP_MODE_RTC_96; 248 else 249 mtl_rx_op |= MTL_OP_MODE_RTC_128; 250 } 251 252 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 253 254 /* Enable MTL RX overflow */ 255 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 256 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 257 ioaddr + MTL_CHAN_INT_CTRL(channel)); 258 } 259 260 static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, 261 int rxmode, int rxfifosz) 262 { 263 /* Only Channel 0 is actually configured and used */ 264 dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0); 265 } 266 267 static void dwmac4_get_hw_feature(void __iomem *ioaddr, 268 struct dma_features *dma_cap) 269 { 270 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 271 272 /* MAC HW feature0 */ 273 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 274 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 275 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 276 dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 277 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 278 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 279 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 280 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 281 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 282 /* MMC */ 283 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 284 /* IEEE 1588-2008 */ 285 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 286 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 287 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 288 /* TX and RX csum */ 289 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 290 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 291 292 /* MAC HW feature1 */ 293 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 294 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 295 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 296 /* MAC HW feature2 */ 297 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 298 /* TX and RX number of channels */ 299 dma_cap->number_rx_channel = 300 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 301 dma_cap->number_tx_channel = 302 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 303 304 /* IEEE 1588-2002 */ 305 dma_cap->time_stamp = 0; 306 } 307 308 /* Enable/disable TSO feature and set MSS */ 309 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 310 { 311 u32 value; 312 313 if (en) { 314 /* enable TSO */ 315 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 316 writel(value | DMA_CONTROL_TSE, 317 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 318 } else { 319 /* enable TSO */ 320 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 321 writel(value & ~DMA_CONTROL_TSE, 322 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 323 } 324 } 325 326 const struct stmmac_dma_ops dwmac4_dma_ops = { 327 .reset = dwmac4_dma_reset, 328 .init = dwmac4_dma_init, 329 .axi = dwmac4_dma_axi, 330 .dump_regs = dwmac4_dump_dma_regs, 331 .dma_mode = dwmac4_dma_operation_mode, 332 .enable_dma_irq = dwmac4_enable_dma_irq, 333 .disable_dma_irq = dwmac4_disable_dma_irq, 334 .start_tx = dwmac4_dma_start_tx, 335 .stop_tx = dwmac4_dma_stop_tx, 336 .start_rx = dwmac4_dma_start_rx, 337 .stop_rx = dwmac4_dma_stop_rx, 338 .dma_interrupt = dwmac4_dma_interrupt, 339 .get_hw_feature = dwmac4_get_hw_feature, 340 .rx_watchdog = dwmac4_rx_watchdog, 341 .set_rx_ring_len = dwmac4_set_rx_ring_len, 342 .set_tx_ring_len = dwmac4_set_tx_ring_len, 343 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 344 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 345 .enable_tso = dwmac4_enable_tso, 346 }; 347 348 const struct stmmac_dma_ops dwmac410_dma_ops = { 349 .reset = dwmac4_dma_reset, 350 .init = dwmac4_dma_init, 351 .axi = dwmac4_dma_axi, 352 .dump_regs = dwmac4_dump_dma_regs, 353 .dma_mode = dwmac4_dma_operation_mode, 354 .enable_dma_irq = dwmac410_enable_dma_irq, 355 .disable_dma_irq = dwmac4_disable_dma_irq, 356 .start_tx = dwmac4_dma_start_tx, 357 .stop_tx = dwmac4_dma_stop_tx, 358 .start_rx = dwmac4_dma_start_rx, 359 .stop_rx = dwmac4_dma_stop_rx, 360 .dma_interrupt = dwmac4_dma_interrupt, 361 .get_hw_feature = dwmac4_get_hw_feature, 362 .rx_watchdog = dwmac4_rx_watchdog, 363 .set_rx_ring_len = dwmac4_set_rx_ring_len, 364 .set_tx_ring_len = dwmac4_set_tx_ring_len, 365 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 366 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 367 .enable_tso = dwmac4_enable_tso, 368 }; 369