1 /* 2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 3 * DWC Ether MAC version 4.xx has been used for developing this code. 4 * 5 * This contains the functions to handle the dma. 6 * 7 * Copyright (C) 2015 STMicroelectronics Ltd 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * Author: Alexandre Torgue <alexandre.torgue@st.com> 14 */ 15 16 #include <linux/io.h> 17 #include "dwmac4.h" 18 #include "dwmac4_dma.h" 19 20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 21 { 22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 23 int i; 24 25 pr_info("dwmac4: Master AXI performs %s burst length\n", 26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 27 28 if (axi->axi_lpi_en) 29 value |= DMA_AXI_EN_LPI; 30 if (axi->axi_xit_frm) 31 value |= DMA_AXI_LPI_XIT_FRM; 32 33 value &= ~DMA_AXI_WR_OSR_LMT; 34 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 35 DMA_AXI_WR_OSR_LMT_SHIFT; 36 37 value &= ~DMA_AXI_RD_OSR_LMT; 38 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 39 DMA_AXI_RD_OSR_LMT_SHIFT; 40 41 /* Depending on the UNDEF bit the Master AXI will perform any burst 42 * length according to the BLEN programmed (by default all BLEN are 43 * set). 44 */ 45 for (i = 0; i < AXI_BLEN; i++) { 46 switch (axi->axi_blen[i]) { 47 case 256: 48 value |= DMA_AXI_BLEN256; 49 break; 50 case 128: 51 value |= DMA_AXI_BLEN128; 52 break; 53 case 64: 54 value |= DMA_AXI_BLEN64; 55 break; 56 case 32: 57 value |= DMA_AXI_BLEN32; 58 break; 59 case 16: 60 value |= DMA_AXI_BLEN16; 61 break; 62 case 8: 63 value |= DMA_AXI_BLEN8; 64 break; 65 case 4: 66 value |= DMA_AXI_BLEN4; 67 break; 68 } 69 } 70 71 writel(value, ioaddr + DMA_SYS_BUS_MODE); 72 } 73 74 static void dwmac4_dma_init_channel(void __iomem *ioaddr, 75 struct stmmac_dma_cfg *dma_cfg, 76 u32 dma_tx_phy, u32 dma_rx_phy, 77 u32 channel) 78 { 79 u32 value; 80 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 81 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 82 83 /* set PBL for each channels. Currently we affect same configuration 84 * on each channel 85 */ 86 value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 87 if (dma_cfg->pblx8) 88 value = value | DMA_BUS_MODE_PBL; 89 writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 90 91 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 92 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 93 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 94 95 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 96 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 97 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 98 99 /* Mask interrupts by writing to CSR7 */ 100 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 101 102 writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 103 writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 104 } 105 106 static void dwmac4_dma_init(void __iomem *ioaddr, 107 struct stmmac_dma_cfg *dma_cfg, 108 u32 dma_tx, u32 dma_rx, int atds) 109 { 110 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 111 int i; 112 113 /* Set the Fixed burst mode */ 114 if (dma_cfg->fixed_burst) 115 value |= DMA_SYS_BUS_FB; 116 117 /* Mixed Burst has no effect when fb is set */ 118 if (dma_cfg->mixed_burst) 119 value |= DMA_SYS_BUS_MB; 120 121 if (dma_cfg->aal) 122 value |= DMA_SYS_BUS_AAL; 123 124 writel(value, ioaddr + DMA_SYS_BUS_MODE); 125 126 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 127 dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i); 128 } 129 130 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 131 u32 *reg_space) 132 { 133 reg_space[DMA_CHAN_CONTROL(channel) / 4] = 134 readl(ioaddr + DMA_CHAN_CONTROL(channel)); 135 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 136 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 137 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 138 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 139 reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 140 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 141 reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 142 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 143 reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 144 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 145 reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 146 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 147 reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 148 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 149 reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 150 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 151 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 152 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 153 reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 154 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 155 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 156 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 157 reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 158 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 159 reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 160 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 161 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 162 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 163 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 164 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 165 reg_space[DMA_CHAN_STATUS(channel) / 4] = 166 readl(ioaddr + DMA_CHAN_STATUS(channel)); 167 } 168 169 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 170 { 171 int i; 172 173 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 174 _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 175 } 176 177 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) 178 { 179 u32 chan; 180 181 for (chan = 0; chan < number_chan; chan++) 182 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan)); 183 } 184 185 static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 186 u32 channel, int fifosz) 187 { 188 unsigned int rqs = fifosz / 256 - 1; 189 u32 mtl_rx_op, mtl_rx_int; 190 191 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 192 193 if (mode == SF_DMA_MODE) { 194 pr_debug("GMAC: enable RX store and forward mode\n"); 195 mtl_rx_op |= MTL_OP_MODE_RSF; 196 } else { 197 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 198 mtl_rx_op &= ~MTL_OP_MODE_RSF; 199 mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 200 if (mode <= 32) 201 mtl_rx_op |= MTL_OP_MODE_RTC_32; 202 else if (mode <= 64) 203 mtl_rx_op |= MTL_OP_MODE_RTC_64; 204 else if (mode <= 96) 205 mtl_rx_op |= MTL_OP_MODE_RTC_96; 206 else 207 mtl_rx_op |= MTL_OP_MODE_RTC_128; 208 } 209 210 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 211 mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 212 213 /* enable flow control only if each channel gets 4 KiB or more FIFO */ 214 if (fifosz >= 4096) { 215 unsigned int rfd, rfa; 216 217 mtl_rx_op |= MTL_OP_MODE_EHFC; 218 219 /* Set Threshold for Activating Flow Control to min 2 frames, 220 * i.e. 1500 * 2 = 3000 bytes. 221 * 222 * Set Threshold for Deactivating Flow Control to min 1 frame, 223 * i.e. 1500 bytes. 224 */ 225 switch (fifosz) { 226 case 4096: 227 /* This violates the above formula because of FIFO size 228 * limit therefore overflow may occur in spite of this. 229 */ 230 rfd = 0x03; /* Full-2.5K */ 231 rfa = 0x01; /* Full-1.5K */ 232 break; 233 234 case 8192: 235 rfd = 0x06; /* Full-4K */ 236 rfa = 0x0a; /* Full-6K */ 237 break; 238 239 case 16384: 240 rfd = 0x06; /* Full-4K */ 241 rfa = 0x12; /* Full-10K */ 242 break; 243 244 default: 245 rfd = 0x06; /* Full-4K */ 246 rfa = 0x1e; /* Full-16K */ 247 break; 248 } 249 250 mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 251 mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 252 253 mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 254 mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 255 } 256 257 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 258 259 /* Enable MTL RX overflow */ 260 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 261 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 262 ioaddr + MTL_CHAN_INT_CTRL(channel)); 263 } 264 265 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 266 u32 channel) 267 { 268 u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 269 270 if (mode == SF_DMA_MODE) { 271 pr_debug("GMAC: enable TX store and forward mode\n"); 272 /* Transmit COE type 2 cannot be done in cut-through mode. */ 273 mtl_tx_op |= MTL_OP_MODE_TSF; 274 } else { 275 pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 276 mtl_tx_op &= ~MTL_OP_MODE_TSF; 277 mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 278 /* Set the transmit threshold */ 279 if (mode <= 32) 280 mtl_tx_op |= MTL_OP_MODE_TTC_32; 281 else if (mode <= 64) 282 mtl_tx_op |= MTL_OP_MODE_TTC_64; 283 else if (mode <= 96) 284 mtl_tx_op |= MTL_OP_MODE_TTC_96; 285 else if (mode <= 128) 286 mtl_tx_op |= MTL_OP_MODE_TTC_128; 287 else if (mode <= 192) 288 mtl_tx_op |= MTL_OP_MODE_TTC_192; 289 else if (mode <= 256) 290 mtl_tx_op |= MTL_OP_MODE_TTC_256; 291 else if (mode <= 384) 292 mtl_tx_op |= MTL_OP_MODE_TTC_384; 293 else 294 mtl_tx_op |= MTL_OP_MODE_TTC_512; 295 } 296 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 297 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 298 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 299 * with reset values: TXQEN off, TQS 256 bytes. 300 * 301 * Write the bits in both cases, since it will have no effect when RO. 302 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 303 * be RO, however, writing the whole TQS field will result in a value 304 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 305 */ 306 mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 307 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 308 } 309 310 static void dwmac4_get_hw_feature(void __iomem *ioaddr, 311 struct dma_features *dma_cap) 312 { 313 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 314 315 /* MAC HW feature0 */ 316 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 317 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 318 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 319 dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 320 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 321 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 322 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 323 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 324 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 325 /* MMC */ 326 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 327 /* IEEE 1588-2008 */ 328 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 329 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 330 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 331 /* TX and RX csum */ 332 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 333 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 334 335 /* MAC HW feature1 */ 336 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 337 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 338 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 339 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 340 * shifting and store the sizes in bytes. 341 */ 342 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 343 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 344 /* MAC HW feature2 */ 345 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 346 /* TX and RX number of channels */ 347 dma_cap->number_rx_channel = 348 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 349 dma_cap->number_tx_channel = 350 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 351 /* TX and RX number of queues */ 352 dma_cap->number_rx_queues = 353 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 354 dma_cap->number_tx_queues = 355 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 356 357 /* IEEE 1588-2002 */ 358 dma_cap->time_stamp = 0; 359 } 360 361 /* Enable/disable TSO feature and set MSS */ 362 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 363 { 364 u32 value; 365 366 if (en) { 367 /* enable TSO */ 368 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 369 writel(value | DMA_CONTROL_TSE, 370 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 371 } else { 372 /* enable TSO */ 373 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 374 writel(value & ~DMA_CONTROL_TSE, 375 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 376 } 377 } 378 379 const struct stmmac_dma_ops dwmac4_dma_ops = { 380 .reset = dwmac4_dma_reset, 381 .init = dwmac4_dma_init, 382 .axi = dwmac4_dma_axi, 383 .dump_regs = dwmac4_dump_dma_regs, 384 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 385 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 386 .enable_dma_irq = dwmac4_enable_dma_irq, 387 .disable_dma_irq = dwmac4_disable_dma_irq, 388 .start_tx = dwmac4_dma_start_tx, 389 .stop_tx = dwmac4_dma_stop_tx, 390 .start_rx = dwmac4_dma_start_rx, 391 .stop_rx = dwmac4_dma_stop_rx, 392 .dma_interrupt = dwmac4_dma_interrupt, 393 .get_hw_feature = dwmac4_get_hw_feature, 394 .rx_watchdog = dwmac4_rx_watchdog, 395 .set_rx_ring_len = dwmac4_set_rx_ring_len, 396 .set_tx_ring_len = dwmac4_set_tx_ring_len, 397 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 398 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 399 .enable_tso = dwmac4_enable_tso, 400 }; 401 402 const struct stmmac_dma_ops dwmac410_dma_ops = { 403 .reset = dwmac4_dma_reset, 404 .init = dwmac4_dma_init, 405 .axi = dwmac4_dma_axi, 406 .dump_regs = dwmac4_dump_dma_regs, 407 .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 408 .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 409 .enable_dma_irq = dwmac410_enable_dma_irq, 410 .disable_dma_irq = dwmac4_disable_dma_irq, 411 .start_tx = dwmac4_dma_start_tx, 412 .stop_tx = dwmac4_dma_stop_tx, 413 .start_rx = dwmac4_dma_start_rx, 414 .stop_rx = dwmac4_dma_stop_rx, 415 .dma_interrupt = dwmac4_dma_interrupt, 416 .get_hw_feature = dwmac4_get_hw_feature, 417 .rx_watchdog = dwmac4_rx_watchdog, 418 .set_rx_ring_len = dwmac4_set_rx_ring_len, 419 .set_tx_ring_len = dwmac4_set_tx_ring_len, 420 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 421 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 422 .enable_tso = dwmac4_enable_tso, 423 }; 424