1 /* 2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 3 * DWC Ether MAC version 4.xx has been used for developing this code. 4 * 5 * This contains the functions to handle the dma. 6 * 7 * Copyright (C) 2015 STMicroelectronics Ltd 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * Author: Alexandre Torgue <alexandre.torgue@st.com> 14 */ 15 16 #include <linux/io.h> 17 #include "dwmac4.h" 18 #include "dwmac4_dma.h" 19 20 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 21 { 22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 23 int i; 24 25 pr_info("dwmac4: Master AXI performs %s burst length\n", 26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 27 28 if (axi->axi_lpi_en) 29 value |= DMA_AXI_EN_LPI; 30 if (axi->axi_xit_frm) 31 value |= DMA_AXI_LPI_XIT_FRM; 32 33 value &= ~DMA_AXI_WR_OSR_LMT; 34 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 35 DMA_AXI_WR_OSR_LMT_SHIFT; 36 37 value &= ~DMA_AXI_RD_OSR_LMT; 38 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 39 DMA_AXI_RD_OSR_LMT_SHIFT; 40 41 /* Depending on the UNDEF bit the Master AXI will perform any burst 42 * length according to the BLEN programmed (by default all BLEN are 43 * set). 44 */ 45 for (i = 0; i < AXI_BLEN; i++) { 46 switch (axi->axi_blen[i]) { 47 case 256: 48 value |= DMA_AXI_BLEN256; 49 break; 50 case 128: 51 value |= DMA_AXI_BLEN128; 52 break; 53 case 64: 54 value |= DMA_AXI_BLEN64; 55 break; 56 case 32: 57 value |= DMA_AXI_BLEN32; 58 break; 59 case 16: 60 value |= DMA_AXI_BLEN16; 61 break; 62 case 8: 63 value |= DMA_AXI_BLEN8; 64 break; 65 case 4: 66 value |= DMA_AXI_BLEN4; 67 break; 68 } 69 } 70 71 writel(value, ioaddr + DMA_SYS_BUS_MODE); 72 } 73 74 static void dwmac4_dma_init_channel(void __iomem *ioaddr, 75 struct stmmac_dma_cfg *dma_cfg, 76 u32 dma_tx_phy, u32 dma_rx_phy, 77 u32 channel) 78 { 79 u32 value; 80 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 81 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 82 83 /* set PBL for each channels. Currently we affect same configuration 84 * on each channel 85 */ 86 value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 87 if (dma_cfg->pblx8) 88 value = value | DMA_BUS_MODE_PBL; 89 writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 90 91 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 92 value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 93 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 94 95 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 96 value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 97 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 98 99 /* Mask interrupts by writing to CSR7 */ 100 writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 101 102 writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 103 writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 104 } 105 106 static void dwmac4_dma_init(void __iomem *ioaddr, 107 struct stmmac_dma_cfg *dma_cfg, 108 u32 dma_tx, u32 dma_rx, int atds) 109 { 110 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 111 int i; 112 113 /* Set the Fixed burst mode */ 114 if (dma_cfg->fixed_burst) 115 value |= DMA_SYS_BUS_FB; 116 117 /* Mixed Burst has no effect when fb is set */ 118 if (dma_cfg->mixed_burst) 119 value |= DMA_SYS_BUS_MB; 120 121 if (dma_cfg->aal) 122 value |= DMA_SYS_BUS_AAL; 123 124 writel(value, ioaddr + DMA_SYS_BUS_MODE); 125 126 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 127 dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i); 128 } 129 130 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 131 u32 *reg_space) 132 { 133 reg_space[DMA_CHAN_CONTROL(channel) / 4] = 134 readl(ioaddr + DMA_CHAN_CONTROL(channel)); 135 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 136 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 137 reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 138 readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 139 reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 140 readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 141 reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 142 readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 143 reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 144 readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 145 reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 146 readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 147 reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 148 readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 149 reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 150 readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 151 reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 152 readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 153 reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 154 readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 155 reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 156 readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 157 reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 158 readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 159 reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 160 readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 161 reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 162 readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 163 reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 164 readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 165 reg_space[DMA_CHAN_STATUS(channel) / 4] = 166 readl(ioaddr + DMA_CHAN_STATUS(channel)); 167 } 168 169 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 170 { 171 int i; 172 173 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 174 _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 175 } 176 177 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 178 { 179 int i; 180 181 for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 182 writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 183 } 184 185 static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, 186 int rxmode, u32 channel, int rxfifosz) 187 { 188 unsigned int rqs = rxfifosz / 256 - 1; 189 u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; 190 191 /* Following code only done for channel 0, other channels not yet 192 * supported. 193 */ 194 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 195 196 if (txmode == SF_DMA_MODE) { 197 pr_debug("GMAC: enable TX store and forward mode\n"); 198 /* Transmit COE type 2 cannot be done in cut-through mode. */ 199 mtl_tx_op |= MTL_OP_MODE_TSF; 200 } else { 201 pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode); 202 mtl_tx_op &= ~MTL_OP_MODE_TSF; 203 mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 204 /* Set the transmit threshold */ 205 if (txmode <= 32) 206 mtl_tx_op |= MTL_OP_MODE_TTC_32; 207 else if (txmode <= 64) 208 mtl_tx_op |= MTL_OP_MODE_TTC_64; 209 else if (txmode <= 96) 210 mtl_tx_op |= MTL_OP_MODE_TTC_96; 211 else if (txmode <= 128) 212 mtl_tx_op |= MTL_OP_MODE_TTC_128; 213 else if (txmode <= 192) 214 mtl_tx_op |= MTL_OP_MODE_TTC_192; 215 else if (txmode <= 256) 216 mtl_tx_op |= MTL_OP_MODE_TTC_256; 217 else if (txmode <= 384) 218 mtl_tx_op |= MTL_OP_MODE_TTC_384; 219 else 220 mtl_tx_op |= MTL_OP_MODE_TTC_512; 221 } 222 /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 223 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 224 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 225 * with reset values: TXQEN off, TQS 256 bytes. 226 * 227 * Write the bits in both cases, since it will have no effect when RO. 228 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 229 * be RO, however, writing the whole TQS field will result in a value 230 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 231 */ 232 mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 233 writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 234 235 mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 236 237 if (rxmode == SF_DMA_MODE) { 238 pr_debug("GMAC: enable RX store and forward mode\n"); 239 mtl_rx_op |= MTL_OP_MODE_RSF; 240 } else { 241 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode); 242 mtl_rx_op &= ~MTL_OP_MODE_RSF; 243 mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 244 if (rxmode <= 32) 245 mtl_rx_op |= MTL_OP_MODE_RTC_32; 246 else if (rxmode <= 64) 247 mtl_rx_op |= MTL_OP_MODE_RTC_64; 248 else if (rxmode <= 96) 249 mtl_rx_op |= MTL_OP_MODE_RTC_96; 250 else 251 mtl_rx_op |= MTL_OP_MODE_RTC_128; 252 } 253 254 mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 255 mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 256 257 /* enable flow control only if each channel gets 4 KiB or more FIFO */ 258 if (rxfifosz >= 4096) { 259 unsigned int rfd, rfa; 260 261 mtl_rx_op |= MTL_OP_MODE_EHFC; 262 263 /* Set Threshold for Activating Flow Control to min 2 frames, 264 * i.e. 1500 * 2 = 3000 bytes. 265 * 266 * Set Threshold for Deactivating Flow Control to min 1 frame, 267 * i.e. 1500 bytes. 268 */ 269 switch (rxfifosz) { 270 case 4096: 271 /* This violates the above formula because of FIFO size 272 * limit therefore overflow may occur in spite of this. 273 */ 274 rfd = 0x03; /* Full-2.5K */ 275 rfa = 0x01; /* Full-1.5K */ 276 break; 277 278 case 8192: 279 rfd = 0x06; /* Full-4K */ 280 rfa = 0x0a; /* Full-6K */ 281 break; 282 283 case 16384: 284 rfd = 0x06; /* Full-4K */ 285 rfa = 0x12; /* Full-10K */ 286 break; 287 288 default: 289 rfd = 0x06; /* Full-4K */ 290 rfa = 0x1e; /* Full-16K */ 291 break; 292 } 293 294 mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 295 mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 296 297 mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 298 mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 299 } 300 301 writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 302 303 /* Enable MTL RX overflow */ 304 mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 305 writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 306 ioaddr + MTL_CHAN_INT_CTRL(channel)); 307 } 308 309 static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, 310 int rxmode, int rxfifosz) 311 { 312 /* Only Channel 0 is actually configured and used */ 313 dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0, rxfifosz); 314 } 315 316 static void dwmac4_get_hw_feature(void __iomem *ioaddr, 317 struct dma_features *dma_cap) 318 { 319 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 320 321 /* MAC HW feature0 */ 322 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 323 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 324 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 325 dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 326 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 327 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 328 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 329 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 330 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 331 /* MMC */ 332 dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 333 /* IEEE 1588-2008 */ 334 dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 335 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 336 dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 337 /* TX and RX csum */ 338 dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 339 dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 340 341 /* MAC HW feature1 */ 342 hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 343 dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 344 dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 345 /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 346 * shifting and store the sizes in bytes. 347 */ 348 dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 349 dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 350 /* MAC HW feature2 */ 351 hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 352 /* TX and RX number of channels */ 353 dma_cap->number_rx_channel = 354 ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 355 dma_cap->number_tx_channel = 356 ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 357 /* TX and RX number of queues */ 358 dma_cap->number_rx_queues = 359 ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 360 dma_cap->number_tx_queues = 361 ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 362 363 /* IEEE 1588-2002 */ 364 dma_cap->time_stamp = 0; 365 } 366 367 /* Enable/disable TSO feature and set MSS */ 368 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 369 { 370 u32 value; 371 372 if (en) { 373 /* enable TSO */ 374 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 375 writel(value | DMA_CONTROL_TSE, 376 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 377 } else { 378 /* enable TSO */ 379 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 380 writel(value & ~DMA_CONTROL_TSE, 381 ioaddr + DMA_CHAN_TX_CONTROL(chan)); 382 } 383 } 384 385 const struct stmmac_dma_ops dwmac4_dma_ops = { 386 .reset = dwmac4_dma_reset, 387 .init = dwmac4_dma_init, 388 .axi = dwmac4_dma_axi, 389 .dump_regs = dwmac4_dump_dma_regs, 390 .dma_mode = dwmac4_dma_operation_mode, 391 .enable_dma_irq = dwmac4_enable_dma_irq, 392 .disable_dma_irq = dwmac4_disable_dma_irq, 393 .start_tx = dwmac4_dma_start_tx, 394 .stop_tx = dwmac4_dma_stop_tx, 395 .start_rx = dwmac4_dma_start_rx, 396 .stop_rx = dwmac4_dma_stop_rx, 397 .dma_interrupt = dwmac4_dma_interrupt, 398 .get_hw_feature = dwmac4_get_hw_feature, 399 .rx_watchdog = dwmac4_rx_watchdog, 400 .set_rx_ring_len = dwmac4_set_rx_ring_len, 401 .set_tx_ring_len = dwmac4_set_tx_ring_len, 402 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 403 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 404 .enable_tso = dwmac4_enable_tso, 405 }; 406 407 const struct stmmac_dma_ops dwmac410_dma_ops = { 408 .reset = dwmac4_dma_reset, 409 .init = dwmac4_dma_init, 410 .axi = dwmac4_dma_axi, 411 .dump_regs = dwmac4_dump_dma_regs, 412 .dma_mode = dwmac4_dma_operation_mode, 413 .enable_dma_irq = dwmac410_enable_dma_irq, 414 .disable_dma_irq = dwmac4_disable_dma_irq, 415 .start_tx = dwmac4_dma_start_tx, 416 .stop_tx = dwmac4_dma_stop_tx, 417 .start_rx = dwmac4_dma_start_rx, 418 .stop_rx = dwmac4_dma_stop_rx, 419 .dma_interrupt = dwmac4_dma_interrupt, 420 .get_hw_feature = dwmac4_get_hw_feature, 421 .rx_watchdog = dwmac4_rx_watchdog, 422 .set_rx_ring_len = dwmac4_set_rx_ring_len, 423 .set_tx_ring_len = dwmac4_set_tx_ring_len, 424 .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 425 .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 426 .enable_tso = dwmac4_enable_tso, 427 }; 428