1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4  * DWC Ether MAC version 4.xx  has been used for  developing this code.
5  *
6  * This contains the functions to handle the dma.
7  *
8  * Copyright (C) 2015  STMicroelectronics Ltd
9  *
10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
11  */
12 
13 #include <linux/io.h>
14 #include "dwmac4.h"
15 #include "dwmac4_dma.h"
16 
17 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
18 {
19 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
20 	int i;
21 
22 	pr_info("dwmac4: Master AXI performs %s burst length\n",
23 		(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
24 
25 	if (axi->axi_lpi_en)
26 		value |= DMA_AXI_EN_LPI;
27 	if (axi->axi_xit_frm)
28 		value |= DMA_AXI_LPI_XIT_FRM;
29 
30 	value &= ~DMA_AXI_WR_OSR_LMT;
31 	value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
32 		 DMA_AXI_WR_OSR_LMT_SHIFT;
33 
34 	value &= ~DMA_AXI_RD_OSR_LMT;
35 	value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
36 		 DMA_AXI_RD_OSR_LMT_SHIFT;
37 
38 	/* Depending on the UNDEF bit the Master AXI will perform any burst
39 	 * length according to the BLEN programmed (by default all BLEN are
40 	 * set).
41 	 */
42 	for (i = 0; i < AXI_BLEN; i++) {
43 		switch (axi->axi_blen[i]) {
44 		case 256:
45 			value |= DMA_AXI_BLEN256;
46 			break;
47 		case 128:
48 			value |= DMA_AXI_BLEN128;
49 			break;
50 		case 64:
51 			value |= DMA_AXI_BLEN64;
52 			break;
53 		case 32:
54 			value |= DMA_AXI_BLEN32;
55 			break;
56 		case 16:
57 			value |= DMA_AXI_BLEN16;
58 			break;
59 		case 8:
60 			value |= DMA_AXI_BLEN8;
61 			break;
62 		case 4:
63 			value |= DMA_AXI_BLEN4;
64 			break;
65 		}
66 	}
67 
68 	writel(value, ioaddr + DMA_SYS_BUS_MODE);
69 }
70 
71 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
72 				    struct stmmac_dma_cfg *dma_cfg,
73 				    dma_addr_t dma_rx_phy, u32 chan)
74 {
75 	u32 value;
76 	u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
77 
78 	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
79 	value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
80 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
81 
82 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
83 		writel(upper_32_bits(dma_rx_phy),
84 		       ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
85 
86 	writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
87 }
88 
89 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
90 				    struct stmmac_dma_cfg *dma_cfg,
91 				    dma_addr_t dma_tx_phy, u32 chan)
92 {
93 	u32 value;
94 	u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
95 
96 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
97 	value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
98 
99 	/* Enable OSP to get best performance */
100 	value |= DMA_CONTROL_OSP;
101 
102 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
103 
104 	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
105 		writel(upper_32_bits(dma_tx_phy),
106 		       ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
107 
108 	writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
109 }
110 
111 static void dwmac4_dma_init_channel(void __iomem *ioaddr,
112 				    struct stmmac_dma_cfg *dma_cfg, u32 chan)
113 {
114 	u32 value;
115 
116 	/* common channel control register config */
117 	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
118 	if (dma_cfg->pblx8)
119 		value = value | DMA_BUS_MODE_PBL;
120 	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
121 
122 	/* Mask interrupts by writing to CSR7 */
123 	writel(DMA_CHAN_INTR_DEFAULT_MASK,
124 	       ioaddr + DMA_CHAN_INTR_ENA(chan));
125 }
126 
127 static void dwmac410_dma_init_channel(void __iomem *ioaddr,
128 				      struct stmmac_dma_cfg *dma_cfg, u32 chan)
129 {
130 	u32 value;
131 
132 	/* common channel control register config */
133 	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
134 	if (dma_cfg->pblx8)
135 		value = value | DMA_BUS_MODE_PBL;
136 
137 	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
138 
139 	/* Mask interrupts by writing to CSR7 */
140 	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
141 	       ioaddr + DMA_CHAN_INTR_ENA(chan));
142 }
143 
144 static void dwmac4_dma_init(void __iomem *ioaddr,
145 			    struct stmmac_dma_cfg *dma_cfg, int atds)
146 {
147 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
148 
149 	/* Set the Fixed burst mode */
150 	if (dma_cfg->fixed_burst)
151 		value |= DMA_SYS_BUS_FB;
152 
153 	/* Mixed Burst has no effect when fb is set */
154 	if (dma_cfg->mixed_burst)
155 		value |= DMA_SYS_BUS_MB;
156 
157 	if (dma_cfg->aal)
158 		value |= DMA_SYS_BUS_AAL;
159 
160 	if (dma_cfg->eame)
161 		value |= DMA_SYS_BUS_EAME;
162 
163 	writel(value, ioaddr + DMA_SYS_BUS_MODE);
164 
165 	value = readl(ioaddr + DMA_BUS_MODE);
166 
167 	if (dma_cfg->multi_msi_en) {
168 		value &= ~DMA_BUS_MODE_INTM_MASK;
169 		value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
170 	}
171 
172 	if (dma_cfg->dche)
173 		value |= DMA_BUS_MODE_DCHE;
174 
175 	writel(value, ioaddr + DMA_BUS_MODE);
176 
177 }
178 
179 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
180 				  u32 *reg_space)
181 {
182 	reg_space[DMA_CHAN_CONTROL(channel) / 4] =
183 		readl(ioaddr + DMA_CHAN_CONTROL(channel));
184 	reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
185 		readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
186 	reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
187 		readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
188 	reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
189 		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
190 	reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
191 		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
192 	reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
193 		readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
194 	reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
195 		readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
196 	reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
197 		readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
198 	reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
199 		readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
200 	reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
201 		readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
202 	reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
203 		readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
204 	reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
205 		readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
206 	reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
207 		readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
208 	reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
209 		readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
210 	reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
211 		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
212 	reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
213 		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
214 	reg_space[DMA_CHAN_STATUS(channel) / 4] =
215 		readl(ioaddr + DMA_CHAN_STATUS(channel));
216 }
217 
218 static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
219 {
220 	int i;
221 
222 	for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
223 		_dwmac4_dump_dma_regs(ioaddr, i, reg_space);
224 }
225 
226 static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 queue)
227 {
228 	writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
229 }
230 
231 static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
232 				       u32 channel, int fifosz, u8 qmode)
233 {
234 	unsigned int rqs = fifosz / 256 - 1;
235 	u32 mtl_rx_op;
236 
237 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
238 
239 	if (mode == SF_DMA_MODE) {
240 		pr_debug("GMAC: enable RX store and forward mode\n");
241 		mtl_rx_op |= MTL_OP_MODE_RSF;
242 	} else {
243 		pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
244 		mtl_rx_op &= ~MTL_OP_MODE_RSF;
245 		mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
246 		if (mode <= 32)
247 			mtl_rx_op |= MTL_OP_MODE_RTC_32;
248 		else if (mode <= 64)
249 			mtl_rx_op |= MTL_OP_MODE_RTC_64;
250 		else if (mode <= 96)
251 			mtl_rx_op |= MTL_OP_MODE_RTC_96;
252 		else
253 			mtl_rx_op |= MTL_OP_MODE_RTC_128;
254 	}
255 
256 	mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
257 	mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
258 
259 	/* Enable flow control only if each channel gets 4 KiB or more FIFO and
260 	 * only if channel is not an AVB channel.
261 	 */
262 	if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
263 		unsigned int rfd, rfa;
264 
265 		mtl_rx_op |= MTL_OP_MODE_EHFC;
266 
267 		/* Set Threshold for Activating Flow Control to min 2 frames,
268 		 * i.e. 1500 * 2 = 3000 bytes.
269 		 *
270 		 * Set Threshold for Deactivating Flow Control to min 1 frame,
271 		 * i.e. 1500 bytes.
272 		 */
273 		switch (fifosz) {
274 		case 4096:
275 			/* This violates the above formula because of FIFO size
276 			 * limit therefore overflow may occur in spite of this.
277 			 */
278 			rfd = 0x03; /* Full-2.5K */
279 			rfa = 0x01; /* Full-1.5K */
280 			break;
281 
282 		default:
283 			rfd = 0x07; /* Full-4.5K */
284 			rfa = 0x04; /* Full-3K */
285 			break;
286 		}
287 
288 		mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
289 		mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
290 
291 		mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
292 		mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
293 	}
294 
295 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
296 }
297 
298 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
299 				       u32 channel, int fifosz, u8 qmode)
300 {
301 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
302 	unsigned int tqs = fifosz / 256 - 1;
303 
304 	if (mode == SF_DMA_MODE) {
305 		pr_debug("GMAC: enable TX store and forward mode\n");
306 		/* Transmit COE type 2 cannot be done in cut-through mode. */
307 		mtl_tx_op |= MTL_OP_MODE_TSF;
308 	} else {
309 		pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
310 		mtl_tx_op &= ~MTL_OP_MODE_TSF;
311 		mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
312 		/* Set the transmit threshold */
313 		if (mode <= 32)
314 			mtl_tx_op |= MTL_OP_MODE_TTC_32;
315 		else if (mode <= 64)
316 			mtl_tx_op |= MTL_OP_MODE_TTC_64;
317 		else if (mode <= 96)
318 			mtl_tx_op |= MTL_OP_MODE_TTC_96;
319 		else if (mode <= 128)
320 			mtl_tx_op |= MTL_OP_MODE_TTC_128;
321 		else if (mode <= 192)
322 			mtl_tx_op |= MTL_OP_MODE_TTC_192;
323 		else if (mode <= 256)
324 			mtl_tx_op |= MTL_OP_MODE_TTC_256;
325 		else if (mode <= 384)
326 			mtl_tx_op |= MTL_OP_MODE_TTC_384;
327 		else
328 			mtl_tx_op |= MTL_OP_MODE_TTC_512;
329 	}
330 	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
331 	 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
332 	 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
333 	 * with reset values: TXQEN off, TQS 256 bytes.
334 	 *
335 	 * TXQEN must be written for multi-channel operation and TQS must
336 	 * reflect the available fifo size per queue (total fifo size / number
337 	 * of enabled queues).
338 	 */
339 	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
340 	if (qmode != MTL_QUEUE_AVB)
341 		mtl_tx_op |= MTL_OP_MODE_TXQEN;
342 	else
343 		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
344 	mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
345 	mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
346 
347 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
348 }
349 
350 static int dwmac4_get_hw_feature(void __iomem *ioaddr,
351 				 struct dma_features *dma_cap)
352 {
353 	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
354 
355 	/*  MAC HW feature0 */
356 	dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
357 	dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
358 	dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
359 	dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
360 	dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
361 	dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
362 	dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
363 	dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
364 	dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
365 	/* MMC */
366 	dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
367 	/* IEEE 1588-2008 */
368 	dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
369 	/* 802.3az - Energy-Efficient Ethernet (EEE) */
370 	dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
371 	/* TX and RX csum */
372 	dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
373 	dma_cap->rx_coe =  (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
374 	dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
375 	dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
376 
377 	/* MAC HW feature1 */
378 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
379 	dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
380 	dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
381 	dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
382 	dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
383 	dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
384 
385 	dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
386 	switch (dma_cap->addr64) {
387 	case 0:
388 		dma_cap->addr64 = 32;
389 		break;
390 	case 1:
391 		dma_cap->addr64 = 40;
392 		break;
393 	case 2:
394 		dma_cap->addr64 = 48;
395 		break;
396 	default:
397 		dma_cap->addr64 = 32;
398 		break;
399 	}
400 
401 	/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
402 	 * shifting and store the sizes in bytes.
403 	 */
404 	dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
405 	dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
406 	/* MAC HW feature2 */
407 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
408 	/* TX and RX number of channels */
409 	dma_cap->number_rx_channel =
410 		((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
411 	dma_cap->number_tx_channel =
412 		((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
413 	/* TX and RX number of queues */
414 	dma_cap->number_rx_queues =
415 		((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
416 	dma_cap->number_tx_queues =
417 		((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
418 	/* PPS output */
419 	dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
420 
421 	/* IEEE 1588-2002 */
422 	dma_cap->time_stamp = 0;
423 	/* Number of Auxiliary Snapshot Inputs */
424 	dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;
425 
426 	/* MAC HW feature3 */
427 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
428 
429 	/* 5.10 Features */
430 	dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
431 	dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
432 	dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
433 	dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
434 	dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
435 	dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
436 	dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
437 	dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
438 	dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
439 	dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
440 
441 	return 0;
442 }
443 
444 /* Enable/disable TSO feature and set MSS */
445 static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
446 {
447 	u32 value;
448 
449 	if (en) {
450 		/* enable TSO */
451 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
452 		writel(value | DMA_CONTROL_TSE,
453 		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
454 	} else {
455 		/* enable TSO */
456 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
457 		writel(value & ~DMA_CONTROL_TSE,
458 		       ioaddr + DMA_CHAN_TX_CONTROL(chan));
459 	}
460 }
461 
462 static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
463 {
464 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
465 
466 	mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
467 	if (qmode != MTL_QUEUE_AVB)
468 		mtl_tx_op |= MTL_OP_MODE_TXQEN;
469 	else
470 		mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
471 
472 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
473 }
474 
475 static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
476 {
477 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
478 
479 	value &= ~DMA_RBSZ_MASK;
480 	value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
481 
482 	writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
483 }
484 
485 static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
486 {
487 	u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
488 
489 	value &= ~GMAC_CONFIG_HDSMS;
490 	value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
491 	writel(value, ioaddr + GMAC_EXT_CONFIG);
492 
493 	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
494 	if (en)
495 		value |= DMA_CONTROL_SPH;
496 	else
497 		value &= ~DMA_CONTROL_SPH;
498 	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
499 }
500 
501 static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
502 {
503 	u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
504 
505 	if (en)
506 		value |= DMA_CONTROL_EDSE;
507 	else
508 		value &= ~DMA_CONTROL_EDSE;
509 
510 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
511 
512 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;
513 	if (en && !value)
514 		return -EIO;
515 
516 	writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
517 	return 0;
518 }
519 
520 const struct stmmac_dma_ops dwmac4_dma_ops = {
521 	.reset = dwmac4_dma_reset,
522 	.init = dwmac4_dma_init,
523 	.init_chan = dwmac4_dma_init_channel,
524 	.init_rx_chan = dwmac4_dma_init_rx_chan,
525 	.init_tx_chan = dwmac4_dma_init_tx_chan,
526 	.axi = dwmac4_dma_axi,
527 	.dump_regs = dwmac4_dump_dma_regs,
528 	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
529 	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
530 	.enable_dma_irq = dwmac4_enable_dma_irq,
531 	.disable_dma_irq = dwmac4_disable_dma_irq,
532 	.start_tx = dwmac4_dma_start_tx,
533 	.stop_tx = dwmac4_dma_stop_tx,
534 	.start_rx = dwmac4_dma_start_rx,
535 	.stop_rx = dwmac4_dma_stop_rx,
536 	.dma_interrupt = dwmac4_dma_interrupt,
537 	.get_hw_feature = dwmac4_get_hw_feature,
538 	.rx_watchdog = dwmac4_rx_watchdog,
539 	.set_rx_ring_len = dwmac4_set_rx_ring_len,
540 	.set_tx_ring_len = dwmac4_set_tx_ring_len,
541 	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
542 	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
543 	.enable_tso = dwmac4_enable_tso,
544 	.qmode = dwmac4_qmode,
545 	.set_bfsize = dwmac4_set_bfsize,
546 	.enable_sph = dwmac4_enable_sph,
547 };
548 
549 const struct stmmac_dma_ops dwmac410_dma_ops = {
550 	.reset = dwmac4_dma_reset,
551 	.init = dwmac4_dma_init,
552 	.init_chan = dwmac410_dma_init_channel,
553 	.init_rx_chan = dwmac4_dma_init_rx_chan,
554 	.init_tx_chan = dwmac4_dma_init_tx_chan,
555 	.axi = dwmac4_dma_axi,
556 	.dump_regs = dwmac4_dump_dma_regs,
557 	.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
558 	.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
559 	.enable_dma_irq = dwmac410_enable_dma_irq,
560 	.disable_dma_irq = dwmac4_disable_dma_irq,
561 	.start_tx = dwmac4_dma_start_tx,
562 	.stop_tx = dwmac4_dma_stop_tx,
563 	.start_rx = dwmac4_dma_start_rx,
564 	.stop_rx = dwmac4_dma_stop_rx,
565 	.dma_interrupt = dwmac4_dma_interrupt,
566 	.get_hw_feature = dwmac4_get_hw_feature,
567 	.rx_watchdog = dwmac4_rx_watchdog,
568 	.set_rx_ring_len = dwmac4_set_rx_ring_len,
569 	.set_tx_ring_len = dwmac4_set_tx_ring_len,
570 	.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
571 	.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
572 	.enable_tso = dwmac4_enable_tso,
573 	.qmode = dwmac4_qmode,
574 	.set_bfsize = dwmac4_set_bfsize,
575 	.enable_sph = dwmac4_enable_sph,
576 	.enable_tbs = dwmac4_enable_tbs,
577 };
578