175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 248863ce5SAlexandre TORGUE /* 348863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 448863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 548863ce5SAlexandre TORGUE * 648863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 748863ce5SAlexandre TORGUE * 848863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 948863ce5SAlexandre TORGUE * 1048863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1148863ce5SAlexandre TORGUE */ 1248863ce5SAlexandre TORGUE 1348863ce5SAlexandre TORGUE #include <linux/io.h> 1448863ce5SAlexandre TORGUE #include "dwmac4.h" 1548863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1648863ce5SAlexandre TORGUE 1748863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 1848863ce5SAlexandre TORGUE { 1948863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2048863ce5SAlexandre TORGUE int i; 2148863ce5SAlexandre TORGUE 2248863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2348863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2648863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 2748863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 2848863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 2948863ce5SAlexandre TORGUE 306b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3148863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3248863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3348863ce5SAlexandre TORGUE 346b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3548863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3648863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 3748863ce5SAlexandre TORGUE 3848863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 3948863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4048863ce5SAlexandre TORGUE * set). 4148863ce5SAlexandre TORGUE */ 4248863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4348863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4448863ce5SAlexandre TORGUE case 256: 4548863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4648863ce5SAlexandre TORGUE break; 4748863ce5SAlexandre TORGUE case 128: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 64: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 32: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 16: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 8: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 4: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE } 6648863ce5SAlexandre TORGUE } 6748863ce5SAlexandre TORGUE 6848863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7172de4655SColin Ian King static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, 7289caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 7306a80a7dSJose Abreu dma_addr_t dma_rx_phy, u32 chan) 7448863ce5SAlexandre TORGUE { 7548863ce5SAlexandre TORGUE u32 value; 7647f2a9ceSJoao Pinto u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 7748863ce5SAlexandre TORGUE 7847f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 7947f2a9ceSJoao Pinto value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 8047f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 8147f2a9ceSJoao Pinto 8206a80a7dSJose Abreu writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); 8347f2a9ceSJoao Pinto } 8447f2a9ceSJoao Pinto 8572de4655SColin Ian King static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, 8647f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, 8706a80a7dSJose Abreu dma_addr_t dma_tx_phy, u32 chan) 8847f2a9ceSJoao Pinto { 8947f2a9ceSJoao Pinto u32 value; 9047f2a9ceSJoao Pinto u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 9147f2a9ceSJoao Pinto 9247f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 9347f2a9ceSJoao Pinto value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 9467e1c406SJose Abreu 9567e1c406SJose Abreu /* Enable OSP to get best performance */ 9667e1c406SJose Abreu value |= DMA_CONTROL_OSP; 9767e1c406SJose Abreu 9847f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 9947f2a9ceSJoao Pinto 10006a80a7dSJose Abreu writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); 10147f2a9ceSJoao Pinto } 10247f2a9ceSJoao Pinto 10372de4655SColin Ian King static void dwmac4_dma_init_channel(void __iomem *ioaddr, 10447f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, u32 chan) 10547f2a9ceSJoao Pinto { 10647f2a9ceSJoao Pinto u32 value; 10747f2a9ceSJoao Pinto 10847f2a9ceSJoao Pinto /* common channel control register config */ 10947f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 1104022d039SNiklas Cassel if (dma_cfg->pblx8) 11148863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 11247f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 11348863ce5SAlexandre TORGUE 11448863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 11547f2a9ceSJoao Pinto writel(DMA_CHAN_INTR_DEFAULT_MASK, 11647f2a9ceSJoao Pinto ioaddr + DMA_CHAN_INTR_ENA(chan)); 11748863ce5SAlexandre TORGUE } 11848863ce5SAlexandre TORGUE 11950ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 12024aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds) 12148863ce5SAlexandre TORGUE { 12248863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 12348863ce5SAlexandre TORGUE 12448863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 12550ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 12648863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 12748863ce5SAlexandre TORGUE 12848863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 12950ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 13048863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 13148863ce5SAlexandre TORGUE 13250ca903aSNiklas Cassel if (dma_cfg->aal) 13348863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 13448863ce5SAlexandre TORGUE 13548863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 13648863ce5SAlexandre TORGUE } 13748863ce5SAlexandre TORGUE 138fbf68229SLABBE Corentin static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 139fbf68229SLABBE Corentin u32 *reg_space) 14048863ce5SAlexandre TORGUE { 141fbf68229SLABBE Corentin reg_space[DMA_CHAN_CONTROL(channel) / 4] = 142fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CONTROL(channel)); 143fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 144fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 145fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 146fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 147fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 148fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 149fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 150fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 151fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 152fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 153fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 154fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 155fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 156fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 157fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 158fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 159fbf68229SLABBE Corentin reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 160fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 161fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 162fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 163fbf68229SLABBE Corentin reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 164fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 165fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 166fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 167fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 168fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 169fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 170fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 171fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 172fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 173fbf68229SLABBE Corentin reg_space[DMA_CHAN_STATUS(channel) / 4] = 174fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_STATUS(channel)); 17548863ce5SAlexandre TORGUE } 17648863ce5SAlexandre TORGUE 177fbf68229SLABBE Corentin static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 17848863ce5SAlexandre TORGUE { 17948863ce5SAlexandre TORGUE int i; 18048863ce5SAlexandre TORGUE 18148863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 182fbf68229SLABBE Corentin _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 18348863ce5SAlexandre TORGUE } 18448863ce5SAlexandre TORGUE 1853c55d4d0SJoao Pinto static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) 18648863ce5SAlexandre TORGUE { 1873c55d4d0SJoao Pinto u32 chan; 18848863ce5SAlexandre TORGUE 1893c55d4d0SJoao Pinto for (chan = 0; chan < number_chan; chan++) 1903c55d4d0SJoao Pinto writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan)); 19148863ce5SAlexandre TORGUE } 19248863ce5SAlexandre TORGUE 1936deee222SJoao Pinto static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 194a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 19548863ce5SAlexandre TORGUE { 1966deee222SJoao Pinto unsigned int rqs = fifosz / 256 - 1; 1976deee222SJoao Pinto u32 mtl_rx_op, mtl_rx_int; 19848863ce5SAlexandre TORGUE 19948863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 20048863ce5SAlexandre TORGUE 2016deee222SJoao Pinto if (mode == SF_DMA_MODE) { 20248863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 20348863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 20448863ce5SAlexandre TORGUE } else { 2056deee222SJoao Pinto pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 20648863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 20748863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 2086deee222SJoao Pinto if (mode <= 32) 20948863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 2106deee222SJoao Pinto else if (mode <= 64) 21148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 2126deee222SJoao Pinto else if (mode <= 96) 21348863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 21448863ce5SAlexandre TORGUE else 21548863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 21648863ce5SAlexandre TORGUE } 21748863ce5SAlexandre TORGUE 218356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 219356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 220356b7557SThierry Reding 221a0daae13SJose Abreu /* Enable flow control only if each channel gets 4 KiB or more FIFO and 222a0daae13SJose Abreu * only if channel is not an AVB channel. 223a0daae13SJose Abreu */ 224a0daae13SJose Abreu if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 225356b7557SThierry Reding unsigned int rfd, rfa; 226356b7557SThierry Reding 227356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC; 228356b7557SThierry Reding 229356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames, 230356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes. 231356b7557SThierry Reding * 232356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame, 233356b7557SThierry Reding * i.e. 1500 bytes. 234356b7557SThierry Reding */ 2356deee222SJoao Pinto switch (fifosz) { 236356b7557SThierry Reding case 4096: 237356b7557SThierry Reding /* This violates the above formula because of FIFO size 238356b7557SThierry Reding * limit therefore overflow may occur in spite of this. 239356b7557SThierry Reding */ 240356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */ 241356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */ 242356b7557SThierry Reding break; 243356b7557SThierry Reding 244356b7557SThierry Reding case 8192: 245356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 246356b7557SThierry Reding rfa = 0x0a; /* Full-6K */ 247356b7557SThierry Reding break; 248356b7557SThierry Reding 249356b7557SThierry Reding case 16384: 250356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 251356b7557SThierry Reding rfa = 0x12; /* Full-10K */ 252356b7557SThierry Reding break; 253356b7557SThierry Reding 254356b7557SThierry Reding default: 255356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 256356b7557SThierry Reding rfa = 0x1e; /* Full-16K */ 257356b7557SThierry Reding break; 258356b7557SThierry Reding } 259356b7557SThierry Reding 260356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 261356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 262356b7557SThierry Reding 263356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 264356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 265356b7557SThierry Reding } 266356b7557SThierry Reding 26748863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 26848863ce5SAlexandre TORGUE 26948863ce5SAlexandre TORGUE /* Enable MTL RX overflow */ 27048863ce5SAlexandre TORGUE mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 27148863ce5SAlexandre TORGUE writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 27248863ce5SAlexandre TORGUE ioaddr + MTL_CHAN_INT_CTRL(channel)); 27348863ce5SAlexandre TORGUE } 27448863ce5SAlexandre TORGUE 2756deee222SJoao Pinto static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 276a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 27748863ce5SAlexandre TORGUE { 2786deee222SJoao Pinto u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 27952a76235SJose Abreu unsigned int tqs = fifosz / 256 - 1; 2806deee222SJoao Pinto 2816deee222SJoao Pinto if (mode == SF_DMA_MODE) { 2826deee222SJoao Pinto pr_debug("GMAC: enable TX store and forward mode\n"); 2836deee222SJoao Pinto /* Transmit COE type 2 cannot be done in cut-through mode. */ 2846deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TSF; 2856deee222SJoao Pinto } else { 2866deee222SJoao Pinto pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 2876deee222SJoao Pinto mtl_tx_op &= ~MTL_OP_MODE_TSF; 2886deee222SJoao Pinto mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 2896deee222SJoao Pinto /* Set the transmit threshold */ 2906deee222SJoao Pinto if (mode <= 32) 2916deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_32; 2926deee222SJoao Pinto else if (mode <= 64) 2936deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_64; 2946deee222SJoao Pinto else if (mode <= 96) 2956deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_96; 2966deee222SJoao Pinto else if (mode <= 128) 2976deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_128; 2986deee222SJoao Pinto else if (mode <= 192) 2996deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_192; 3006deee222SJoao Pinto else if (mode <= 256) 3016deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_256; 3026deee222SJoao Pinto else if (mode <= 384) 3036deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_384; 3046deee222SJoao Pinto else 3056deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_512; 3066deee222SJoao Pinto } 3076deee222SJoao Pinto /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 3086deee222SJoao Pinto * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 3096deee222SJoao Pinto * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 3106deee222SJoao Pinto * with reset values: TXQEN off, TQS 256 bytes. 3116deee222SJoao Pinto * 31252a76235SJose Abreu * TXQEN must be written for multi-channel operation and TQS must 31352a76235SJose Abreu * reflect the available fifo size per queue (total fifo size / number 31452a76235SJose Abreu * of enabled queues). 3156deee222SJoao Pinto */ 316a0daae13SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 317a0daae13SJose Abreu if (qmode != MTL_QUEUE_AVB) 31852a76235SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 319a0daae13SJose Abreu else 320a0daae13SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 32152a76235SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; 32252a76235SJose Abreu mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; 32352a76235SJose Abreu 3246deee222SJoao Pinto writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 32548863ce5SAlexandre TORGUE } 32648863ce5SAlexandre TORGUE 32748863ce5SAlexandre TORGUE static void dwmac4_get_hw_feature(void __iomem *ioaddr, 32848863ce5SAlexandre TORGUE struct dma_features *dma_cap) 32948863ce5SAlexandre TORGUE { 33048863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 33148863ce5SAlexandre TORGUE 33248863ce5SAlexandre TORGUE /* MAC HW feature0 */ 33348863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 33448863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 33548863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 33648863ce5SAlexandre TORGUE dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 33748863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 33848863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 33948863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 34048863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 34148863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 34248863ce5SAlexandre TORGUE /* MMC */ 34348863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 34448863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 34548863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 34648863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 34748863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 34848863ce5SAlexandre TORGUE /* TX and RX csum */ 34948863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 35048863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 35148863ce5SAlexandre TORGUE 35248863ce5SAlexandre TORGUE /* MAC HW feature1 */ 35348863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 354b8ef7020SBiao Huang dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; 35548863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 35648863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 35711fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 35811fbf811SThierry Reding * shifting and store the sizes in bytes. 35911fbf811SThierry Reding */ 36011fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 36111fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 36248863ce5SAlexandre TORGUE /* MAC HW feature2 */ 36348863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 36448863ce5SAlexandre TORGUE /* TX and RX number of channels */ 36548863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 36648863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 36748863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 36848863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 3699eb12474Sjpinto /* TX and RX number of queues */ 3709eb12474Sjpinto dma_cap->number_rx_queues = 3719eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 3729eb12474Sjpinto dma_cap->number_tx_queues = 3739eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 3749a8a02c9SJose Abreu /* PPS output */ 3759a8a02c9SJose Abreu dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24; 37648863ce5SAlexandre TORGUE 37748863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 37848863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 3798bf993a5SJose Abreu 3808bf993a5SJose Abreu /* MAC HW feature3 */ 3818bf993a5SJose Abreu hw_cap = readl(ioaddr + GMAC_HW_FEATURE3); 3828bf993a5SJose Abreu 3838bf993a5SJose Abreu /* 5.10 Features */ 3848bf993a5SJose Abreu dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28; 3854dbbe8ddSJose Abreu dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13; 3864dbbe8ddSJose Abreu dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11; 3874dbbe8ddSJose Abreu dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10; 38848863ce5SAlexandre TORGUE } 38948863ce5SAlexandre TORGUE 39048863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 39148863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 39248863ce5SAlexandre TORGUE { 39348863ce5SAlexandre TORGUE u32 value; 39448863ce5SAlexandre TORGUE 39548863ce5SAlexandre TORGUE if (en) { 39648863ce5SAlexandre TORGUE /* enable TSO */ 39748863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 39848863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 39948863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 40048863ce5SAlexandre TORGUE } else { 40148863ce5SAlexandre TORGUE /* enable TSO */ 40248863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 40348863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 40448863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 40548863ce5SAlexandre TORGUE } 40648863ce5SAlexandre TORGUE } 40748863ce5SAlexandre TORGUE 4081f705bc6SJose Abreu static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 4091f705bc6SJose Abreu { 4101f705bc6SJose Abreu u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4111f705bc6SJose Abreu 4121f705bc6SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 4131f705bc6SJose Abreu if (qmode != MTL_QUEUE_AVB) 4141f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 4151f705bc6SJose Abreu else 4161f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 4171f705bc6SJose Abreu 4181f705bc6SJose Abreu writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4191f705bc6SJose Abreu } 4201f705bc6SJose Abreu 4214205c88eSJose Abreu static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 4224205c88eSJose Abreu { 4234205c88eSJose Abreu u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4244205c88eSJose Abreu 4254205c88eSJose Abreu value &= ~DMA_RBSZ_MASK; 4264205c88eSJose Abreu value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK; 4274205c88eSJose Abreu 4284205c88eSJose Abreu writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4294205c88eSJose Abreu } 4304205c88eSJose Abreu 43148863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 43248863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 43348863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 43447f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 43547f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 43647f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 43748863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 43848863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 4396deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 4406deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 44148863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 44248863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 44348863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 44448863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 44548863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 44648863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 44748863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 44848863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 44948863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 45048863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 45148863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 45248863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 45348863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 45448863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 4551f705bc6SJose Abreu .qmode = dwmac4_qmode, 4564205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 45748863ce5SAlexandre TORGUE }; 45848863ce5SAlexandre TORGUE 45948863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 46048863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 46148863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 46247f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 46347f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 46447f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 46548863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 46648863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 4676deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 4686deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 46948863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 47048863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 47148863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 47248863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 47348863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 47448863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 47548863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 47648863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 47748863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 47848863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 47948863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 48048863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 48148863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 48248863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 4831f705bc6SJose Abreu .qmode = dwmac4_qmode, 4844205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 48548863ce5SAlexandre TORGUE }; 486