148863ce5SAlexandre TORGUE /* 248863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 348863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 448863ce5SAlexandre TORGUE * 548863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 648863ce5SAlexandre TORGUE * 748863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 848863ce5SAlexandre TORGUE * 948863ce5SAlexandre TORGUE * This program is free software; you can redistribute it and/or modify it 1048863ce5SAlexandre TORGUE * under the terms and conditions of the GNU General Public License, 1148863ce5SAlexandre TORGUE * version 2, as published by the Free Software Foundation. 1248863ce5SAlexandre TORGUE * 1348863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1448863ce5SAlexandre TORGUE */ 1548863ce5SAlexandre TORGUE 1648863ce5SAlexandre TORGUE #include <linux/io.h> 1748863ce5SAlexandre TORGUE #include "dwmac4.h" 1848863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1948863ce5SAlexandre TORGUE 2048863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 2148863ce5SAlexandre TORGUE { 2248863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2348863ce5SAlexandre TORGUE int i; 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2648863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2748863ce5SAlexandre TORGUE 2848863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2948863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 3048863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 3148863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 3248863ce5SAlexandre TORGUE 336b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3448863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3548863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3648863ce5SAlexandre TORGUE 376b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3848863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3948863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 4048863ce5SAlexandre TORGUE 4148863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 4248863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4348863ce5SAlexandre TORGUE * set). 4448863ce5SAlexandre TORGUE */ 4548863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4648863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4748863ce5SAlexandre TORGUE case 256: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 128: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 64: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 32: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 16: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 8: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE case 4: 6648863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6748863ce5SAlexandre TORGUE break; 6848863ce5SAlexandre TORGUE } 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7148863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 7248863ce5SAlexandre TORGUE } 7348863ce5SAlexandre TORGUE 7472de4655SColin Ian King static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, 7589caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 7647f2a9ceSJoao Pinto u32 dma_rx_phy, u32 chan) 7748863ce5SAlexandre TORGUE { 7848863ce5SAlexandre TORGUE u32 value; 7947f2a9ceSJoao Pinto u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 8048863ce5SAlexandre TORGUE 8147f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 8247f2a9ceSJoao Pinto value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 8347f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 8447f2a9ceSJoao Pinto 8547f2a9ceSJoao Pinto writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); 8647f2a9ceSJoao Pinto } 8747f2a9ceSJoao Pinto 8872de4655SColin Ian King static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, 8947f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, 9047f2a9ceSJoao Pinto u32 dma_tx_phy, u32 chan) 9147f2a9ceSJoao Pinto { 9247f2a9ceSJoao Pinto u32 value; 9347f2a9ceSJoao Pinto u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 9447f2a9ceSJoao Pinto 9547f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 9647f2a9ceSJoao Pinto value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 9767e1c406SJose Abreu 9867e1c406SJose Abreu /* Enable OSP to get best performance */ 9967e1c406SJose Abreu value |= DMA_CONTROL_OSP; 10067e1c406SJose Abreu 10147f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 10247f2a9ceSJoao Pinto 10347f2a9ceSJoao Pinto writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); 10447f2a9ceSJoao Pinto } 10547f2a9ceSJoao Pinto 10672de4655SColin Ian King static void dwmac4_dma_init_channel(void __iomem *ioaddr, 10747f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, u32 chan) 10847f2a9ceSJoao Pinto { 10947f2a9ceSJoao Pinto u32 value; 11047f2a9ceSJoao Pinto 11147f2a9ceSJoao Pinto /* common channel control register config */ 11247f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 1134022d039SNiklas Cassel if (dma_cfg->pblx8) 11448863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 11547f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 11648863ce5SAlexandre TORGUE 11748863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 11847f2a9ceSJoao Pinto writel(DMA_CHAN_INTR_DEFAULT_MASK, 11947f2a9ceSJoao Pinto ioaddr + DMA_CHAN_INTR_ENA(chan)); 12048863ce5SAlexandre TORGUE } 12148863ce5SAlexandre TORGUE 12250ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 12324aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds) 12448863ce5SAlexandre TORGUE { 12548863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 12648863ce5SAlexandre TORGUE 12748863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 12850ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 12948863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 13048863ce5SAlexandre TORGUE 13148863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 13250ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 13348863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 13448863ce5SAlexandre TORGUE 13550ca903aSNiklas Cassel if (dma_cfg->aal) 13648863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 13748863ce5SAlexandre TORGUE 13848863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 13948863ce5SAlexandre TORGUE } 14048863ce5SAlexandre TORGUE 141fbf68229SLABBE Corentin static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 142fbf68229SLABBE Corentin u32 *reg_space) 14348863ce5SAlexandre TORGUE { 144fbf68229SLABBE Corentin reg_space[DMA_CHAN_CONTROL(channel) / 4] = 145fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CONTROL(channel)); 146fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 147fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 148fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 149fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 150fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 151fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 152fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 153fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 154fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 155fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 156fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 157fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 158fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 159fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 160fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 161fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 162fbf68229SLABBE Corentin reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 163fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 164fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 165fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 166fbf68229SLABBE Corentin reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 167fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 168fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 169fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 170fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 171fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 172fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 173fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 174fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 175fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 176fbf68229SLABBE Corentin reg_space[DMA_CHAN_STATUS(channel) / 4] = 177fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_STATUS(channel)); 17848863ce5SAlexandre TORGUE } 17948863ce5SAlexandre TORGUE 180fbf68229SLABBE Corentin static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 18148863ce5SAlexandre TORGUE { 18248863ce5SAlexandre TORGUE int i; 18348863ce5SAlexandre TORGUE 18448863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 185fbf68229SLABBE Corentin _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 18648863ce5SAlexandre TORGUE } 18748863ce5SAlexandre TORGUE 1883c55d4d0SJoao Pinto static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) 18948863ce5SAlexandre TORGUE { 1903c55d4d0SJoao Pinto u32 chan; 19148863ce5SAlexandre TORGUE 1923c55d4d0SJoao Pinto for (chan = 0; chan < number_chan; chan++) 1933c55d4d0SJoao Pinto writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan)); 19448863ce5SAlexandre TORGUE } 19548863ce5SAlexandre TORGUE 1966deee222SJoao Pinto static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 197a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 19848863ce5SAlexandre TORGUE { 1996deee222SJoao Pinto unsigned int rqs = fifosz / 256 - 1; 2006deee222SJoao Pinto u32 mtl_rx_op, mtl_rx_int; 20148863ce5SAlexandre TORGUE 20248863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 20348863ce5SAlexandre TORGUE 2046deee222SJoao Pinto if (mode == SF_DMA_MODE) { 20548863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 20648863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 20748863ce5SAlexandre TORGUE } else { 2086deee222SJoao Pinto pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 20948863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 21048863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 2116deee222SJoao Pinto if (mode <= 32) 21248863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 2136deee222SJoao Pinto else if (mode <= 64) 21448863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 2156deee222SJoao Pinto else if (mode <= 96) 21648863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 21748863ce5SAlexandre TORGUE else 21848863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 21948863ce5SAlexandre TORGUE } 22048863ce5SAlexandre TORGUE 221356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 222356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 223356b7557SThierry Reding 224a0daae13SJose Abreu /* Enable flow control only if each channel gets 4 KiB or more FIFO and 225a0daae13SJose Abreu * only if channel is not an AVB channel. 226a0daae13SJose Abreu */ 227a0daae13SJose Abreu if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 228356b7557SThierry Reding unsigned int rfd, rfa; 229356b7557SThierry Reding 230356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC; 231356b7557SThierry Reding 232356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames, 233356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes. 234356b7557SThierry Reding * 235356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame, 236356b7557SThierry Reding * i.e. 1500 bytes. 237356b7557SThierry Reding */ 2386deee222SJoao Pinto switch (fifosz) { 239356b7557SThierry Reding case 4096: 240356b7557SThierry Reding /* This violates the above formula because of FIFO size 241356b7557SThierry Reding * limit therefore overflow may occur in spite of this. 242356b7557SThierry Reding */ 243356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */ 244356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */ 245356b7557SThierry Reding break; 246356b7557SThierry Reding 247356b7557SThierry Reding case 8192: 248356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 249356b7557SThierry Reding rfa = 0x0a; /* Full-6K */ 250356b7557SThierry Reding break; 251356b7557SThierry Reding 252356b7557SThierry Reding case 16384: 253356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 254356b7557SThierry Reding rfa = 0x12; /* Full-10K */ 255356b7557SThierry Reding break; 256356b7557SThierry Reding 257356b7557SThierry Reding default: 258356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 259356b7557SThierry Reding rfa = 0x1e; /* Full-16K */ 260356b7557SThierry Reding break; 261356b7557SThierry Reding } 262356b7557SThierry Reding 263356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 264356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 265356b7557SThierry Reding 266356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 267356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 268356b7557SThierry Reding } 269356b7557SThierry Reding 27048863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 27148863ce5SAlexandre TORGUE 27248863ce5SAlexandre TORGUE /* Enable MTL RX overflow */ 27348863ce5SAlexandre TORGUE mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 27448863ce5SAlexandre TORGUE writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 27548863ce5SAlexandre TORGUE ioaddr + MTL_CHAN_INT_CTRL(channel)); 27648863ce5SAlexandre TORGUE } 27748863ce5SAlexandre TORGUE 2786deee222SJoao Pinto static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 279a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 28048863ce5SAlexandre TORGUE { 2816deee222SJoao Pinto u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 28252a76235SJose Abreu unsigned int tqs = fifosz / 256 - 1; 2836deee222SJoao Pinto 2846deee222SJoao Pinto if (mode == SF_DMA_MODE) { 2856deee222SJoao Pinto pr_debug("GMAC: enable TX store and forward mode\n"); 2866deee222SJoao Pinto /* Transmit COE type 2 cannot be done in cut-through mode. */ 2876deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TSF; 2886deee222SJoao Pinto } else { 2896deee222SJoao Pinto pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 2906deee222SJoao Pinto mtl_tx_op &= ~MTL_OP_MODE_TSF; 2916deee222SJoao Pinto mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 2926deee222SJoao Pinto /* Set the transmit threshold */ 2936deee222SJoao Pinto if (mode <= 32) 2946deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_32; 2956deee222SJoao Pinto else if (mode <= 64) 2966deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_64; 2976deee222SJoao Pinto else if (mode <= 96) 2986deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_96; 2996deee222SJoao Pinto else if (mode <= 128) 3006deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_128; 3016deee222SJoao Pinto else if (mode <= 192) 3026deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_192; 3036deee222SJoao Pinto else if (mode <= 256) 3046deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_256; 3056deee222SJoao Pinto else if (mode <= 384) 3066deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_384; 3076deee222SJoao Pinto else 3086deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_512; 3096deee222SJoao Pinto } 3106deee222SJoao Pinto /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 3116deee222SJoao Pinto * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 3126deee222SJoao Pinto * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 3136deee222SJoao Pinto * with reset values: TXQEN off, TQS 256 bytes. 3146deee222SJoao Pinto * 31552a76235SJose Abreu * TXQEN must be written for multi-channel operation and TQS must 31652a76235SJose Abreu * reflect the available fifo size per queue (total fifo size / number 31752a76235SJose Abreu * of enabled queues). 3186deee222SJoao Pinto */ 319a0daae13SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 320a0daae13SJose Abreu if (qmode != MTL_QUEUE_AVB) 32152a76235SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 322a0daae13SJose Abreu else 323a0daae13SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 32452a76235SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; 32552a76235SJose Abreu mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; 32652a76235SJose Abreu 3276deee222SJoao Pinto writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 32848863ce5SAlexandre TORGUE } 32948863ce5SAlexandre TORGUE 33048863ce5SAlexandre TORGUE static void dwmac4_get_hw_feature(void __iomem *ioaddr, 33148863ce5SAlexandre TORGUE struct dma_features *dma_cap) 33248863ce5SAlexandre TORGUE { 33348863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 33448863ce5SAlexandre TORGUE 33548863ce5SAlexandre TORGUE /* MAC HW feature0 */ 33648863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 33748863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 33848863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 33948863ce5SAlexandre TORGUE dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 34048863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 34148863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 34248863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 34348863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 34448863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 34548863ce5SAlexandre TORGUE /* MMC */ 34648863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 34748863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 34848863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 34948863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 35048863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 35148863ce5SAlexandre TORGUE /* TX and RX csum */ 35248863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 35348863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 35448863ce5SAlexandre TORGUE 35548863ce5SAlexandre TORGUE /* MAC HW feature1 */ 35648863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 35748863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 35848863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 35911fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 36011fbf811SThierry Reding * shifting and store the sizes in bytes. 36111fbf811SThierry Reding */ 36211fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 36311fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 36448863ce5SAlexandre TORGUE /* MAC HW feature2 */ 36548863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 36648863ce5SAlexandre TORGUE /* TX and RX number of channels */ 36748863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 36848863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 36948863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 37048863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 3719eb12474Sjpinto /* TX and RX number of queues */ 3729eb12474Sjpinto dma_cap->number_rx_queues = 3739eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 3749eb12474Sjpinto dma_cap->number_tx_queues = 3759eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 3769a8a02c9SJose Abreu /* PPS output */ 3779a8a02c9SJose Abreu dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24; 37848863ce5SAlexandre TORGUE 37948863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 38048863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 3818bf993a5SJose Abreu 3828bf993a5SJose Abreu /* MAC HW feature3 */ 3838bf993a5SJose Abreu hw_cap = readl(ioaddr + GMAC_HW_FEATURE3); 3848bf993a5SJose Abreu 3858bf993a5SJose Abreu /* 5.10 Features */ 3868bf993a5SJose Abreu dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28; 3874dbbe8ddSJose Abreu dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13; 3884dbbe8ddSJose Abreu dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11; 3894dbbe8ddSJose Abreu dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10; 39048863ce5SAlexandre TORGUE } 39148863ce5SAlexandre TORGUE 39248863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 39348863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 39448863ce5SAlexandre TORGUE { 39548863ce5SAlexandre TORGUE u32 value; 39648863ce5SAlexandre TORGUE 39748863ce5SAlexandre TORGUE if (en) { 39848863ce5SAlexandre TORGUE /* enable TSO */ 39948863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 40048863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 40148863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 40248863ce5SAlexandre TORGUE } else { 40348863ce5SAlexandre TORGUE /* enable TSO */ 40448863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 40548863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 40648863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 40748863ce5SAlexandre TORGUE } 40848863ce5SAlexandre TORGUE } 40948863ce5SAlexandre TORGUE 41048863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 41148863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 41248863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 41347f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 41447f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 41547f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 41648863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 41748863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 4186deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 4196deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 42048863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 42148863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 42248863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 42348863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 42448863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 42548863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 42648863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 42748863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 42848863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 42948863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 43048863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 43148863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 43248863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 43348863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 43448863ce5SAlexandre TORGUE }; 43548863ce5SAlexandre TORGUE 43648863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 43748863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 43848863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 43947f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 44047f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 44147f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 44248863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 44348863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 4446deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 4456deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 44648863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 44748863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 44848863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 44948863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 45048863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 45148863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 45248863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 45348863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 45448863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 45548863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 45648863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 45748863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 45848863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 45948863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 46048863ce5SAlexandre TORGUE }; 461