175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 248863ce5SAlexandre TORGUE /* 348863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 448863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 548863ce5SAlexandre TORGUE * 648863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 748863ce5SAlexandre TORGUE * 848863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 948863ce5SAlexandre TORGUE * 1048863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1148863ce5SAlexandre TORGUE */ 1248863ce5SAlexandre TORGUE 1348863ce5SAlexandre TORGUE #include <linux/io.h> 1448863ce5SAlexandre TORGUE #include "dwmac4.h" 1548863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1648863ce5SAlexandre TORGUE 1748863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 1848863ce5SAlexandre TORGUE { 1948863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2048863ce5SAlexandre TORGUE int i; 2148863ce5SAlexandre TORGUE 2248863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2348863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2648863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 2748863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 2848863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 2948863ce5SAlexandre TORGUE 306b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3148863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3248863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3348863ce5SAlexandre TORGUE 346b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3548863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3648863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 3748863ce5SAlexandre TORGUE 3848863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 3948863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4048863ce5SAlexandre TORGUE * set). 4148863ce5SAlexandre TORGUE */ 4248863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4348863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4448863ce5SAlexandre TORGUE case 256: 4548863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4648863ce5SAlexandre TORGUE break; 4748863ce5SAlexandre TORGUE case 128: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 64: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 32: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 16: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 8: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 4: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE } 6648863ce5SAlexandre TORGUE } 6748863ce5SAlexandre TORGUE 6848863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7172de4655SColin Ian King static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, 7289caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 7306a80a7dSJose Abreu dma_addr_t dma_rx_phy, u32 chan) 7448863ce5SAlexandre TORGUE { 7548863ce5SAlexandre TORGUE u32 value; 7647f2a9ceSJoao Pinto u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 7748863ce5SAlexandre TORGUE 7847f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 7947f2a9ceSJoao Pinto value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 8047f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 8147f2a9ceSJoao Pinto 82560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 83560c07cbSThierry Reding writel(upper_32_bits(dma_rx_phy), 84560c07cbSThierry Reding ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); 85560c07cbSThierry Reding 8606a80a7dSJose Abreu writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); 8747f2a9ceSJoao Pinto } 8847f2a9ceSJoao Pinto 8972de4655SColin Ian King static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, 9047f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, 9106a80a7dSJose Abreu dma_addr_t dma_tx_phy, u32 chan) 9247f2a9ceSJoao Pinto { 9347f2a9ceSJoao Pinto u32 value; 9447f2a9ceSJoao Pinto u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 9547f2a9ceSJoao Pinto 9647f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 9747f2a9ceSJoao Pinto value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 9867e1c406SJose Abreu 9967e1c406SJose Abreu /* Enable OSP to get best performance */ 10067e1c406SJose Abreu value |= DMA_CONTROL_OSP; 10167e1c406SJose Abreu 10247f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 10347f2a9ceSJoao Pinto 104560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 105560c07cbSThierry Reding writel(upper_32_bits(dma_tx_phy), 106560c07cbSThierry Reding ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan)); 107560c07cbSThierry Reding 10806a80a7dSJose Abreu writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); 10947f2a9ceSJoao Pinto } 11047f2a9ceSJoao Pinto 11172de4655SColin Ian King static void dwmac4_dma_init_channel(void __iomem *ioaddr, 11247f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, u32 chan) 11347f2a9ceSJoao Pinto { 11447f2a9ceSJoao Pinto u32 value; 11547f2a9ceSJoao Pinto 11647f2a9ceSJoao Pinto /* common channel control register config */ 11747f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 1184022d039SNiklas Cassel if (dma_cfg->pblx8) 11948863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 12047f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 12148863ce5SAlexandre TORGUE 12248863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 12347f2a9ceSJoao Pinto writel(DMA_CHAN_INTR_DEFAULT_MASK, 12447f2a9ceSJoao Pinto ioaddr + DMA_CHAN_INTR_ENA(chan)); 12548863ce5SAlexandre TORGUE } 12648863ce5SAlexandre TORGUE 127*879c348cSOng Boon Leong static void dwmac410_dma_init_channel(void __iomem *ioaddr, 128*879c348cSOng Boon Leong struct stmmac_dma_cfg *dma_cfg, u32 chan) 129*879c348cSOng Boon Leong { 130*879c348cSOng Boon Leong u32 value; 131*879c348cSOng Boon Leong 132*879c348cSOng Boon Leong /* common channel control register config */ 133*879c348cSOng Boon Leong value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 134*879c348cSOng Boon Leong if (dma_cfg->pblx8) 135*879c348cSOng Boon Leong value = value | DMA_BUS_MODE_PBL; 136*879c348cSOng Boon Leong 137*879c348cSOng Boon Leong writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 138*879c348cSOng Boon Leong 139*879c348cSOng Boon Leong /* Mask interrupts by writing to CSR7 */ 140*879c348cSOng Boon Leong writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10, 141*879c348cSOng Boon Leong ioaddr + DMA_CHAN_INTR_ENA(chan)); 142*879c348cSOng Boon Leong } 143*879c348cSOng Boon Leong 14450ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 14524aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds) 14648863ce5SAlexandre TORGUE { 14748863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 14848863ce5SAlexandre TORGUE 14948863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 15050ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 15148863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 15248863ce5SAlexandre TORGUE 15348863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 15450ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 15548863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 15648863ce5SAlexandre TORGUE 15750ca903aSNiklas Cassel if (dma_cfg->aal) 15848863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 15948863ce5SAlexandre TORGUE 160560c07cbSThierry Reding if (dma_cfg->eame) 161560c07cbSThierry Reding value |= DMA_SYS_BUS_EAME; 162560c07cbSThierry Reding 16348863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 16448863ce5SAlexandre TORGUE } 16548863ce5SAlexandre TORGUE 166fbf68229SLABBE Corentin static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 167fbf68229SLABBE Corentin u32 *reg_space) 16848863ce5SAlexandre TORGUE { 169fbf68229SLABBE Corentin reg_space[DMA_CHAN_CONTROL(channel) / 4] = 170fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CONTROL(channel)); 171fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 172fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 173fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 174fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 175fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 176fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 177fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 178fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 179fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 180fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 181fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 182fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 183fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 184fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 185fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 186fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 187fbf68229SLABBE Corentin reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 188fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 189fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 190fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 191fbf68229SLABBE Corentin reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 192fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 193fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 194fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 195fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 196fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 197fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 198fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 199fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 200fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 201fbf68229SLABBE Corentin reg_space[DMA_CHAN_STATUS(channel) / 4] = 202fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_STATUS(channel)); 20348863ce5SAlexandre TORGUE } 20448863ce5SAlexandre TORGUE 205fbf68229SLABBE Corentin static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 20648863ce5SAlexandre TORGUE { 20748863ce5SAlexandre TORGUE int i; 20848863ce5SAlexandre TORGUE 20948863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 210fbf68229SLABBE Corentin _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 21148863ce5SAlexandre TORGUE } 21248863ce5SAlexandre TORGUE 2133c55d4d0SJoao Pinto static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) 21448863ce5SAlexandre TORGUE { 2153c55d4d0SJoao Pinto u32 chan; 21648863ce5SAlexandre TORGUE 2173c55d4d0SJoao Pinto for (chan = 0; chan < number_chan; chan++) 2183c55d4d0SJoao Pinto writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan)); 21948863ce5SAlexandre TORGUE } 22048863ce5SAlexandre TORGUE 2216deee222SJoao Pinto static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 222a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 22348863ce5SAlexandre TORGUE { 2246deee222SJoao Pinto unsigned int rqs = fifosz / 256 - 1; 2256deee222SJoao Pinto u32 mtl_rx_op, mtl_rx_int; 22648863ce5SAlexandre TORGUE 22748863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 22848863ce5SAlexandre TORGUE 2296deee222SJoao Pinto if (mode == SF_DMA_MODE) { 23048863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 23148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 23248863ce5SAlexandre TORGUE } else { 2336deee222SJoao Pinto pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 23448863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 23548863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 2366deee222SJoao Pinto if (mode <= 32) 23748863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 2386deee222SJoao Pinto else if (mode <= 64) 23948863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 2406deee222SJoao Pinto else if (mode <= 96) 24148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 24248863ce5SAlexandre TORGUE else 24348863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 24448863ce5SAlexandre TORGUE } 24548863ce5SAlexandre TORGUE 246356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 247356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 248356b7557SThierry Reding 249a0daae13SJose Abreu /* Enable flow control only if each channel gets 4 KiB or more FIFO and 250a0daae13SJose Abreu * only if channel is not an AVB channel. 251a0daae13SJose Abreu */ 252a0daae13SJose Abreu if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 253356b7557SThierry Reding unsigned int rfd, rfa; 254356b7557SThierry Reding 255356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC; 256356b7557SThierry Reding 257356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames, 258356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes. 259356b7557SThierry Reding * 260356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame, 261356b7557SThierry Reding * i.e. 1500 bytes. 262356b7557SThierry Reding */ 2636deee222SJoao Pinto switch (fifosz) { 264356b7557SThierry Reding case 4096: 265356b7557SThierry Reding /* This violates the above formula because of FIFO size 266356b7557SThierry Reding * limit therefore overflow may occur in spite of this. 267356b7557SThierry Reding */ 268356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */ 269356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */ 270356b7557SThierry Reding break; 271356b7557SThierry Reding 272356b7557SThierry Reding default: 273854248e5SJose Abreu rfd = 0x07; /* Full-4.5K */ 274854248e5SJose Abreu rfa = 0x04; /* Full-3K */ 275356b7557SThierry Reding break; 276356b7557SThierry Reding } 277356b7557SThierry Reding 278356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 279356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 280356b7557SThierry Reding 281356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 282356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 283356b7557SThierry Reding } 284356b7557SThierry Reding 28548863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 28648863ce5SAlexandre TORGUE 28748863ce5SAlexandre TORGUE /* Enable MTL RX overflow */ 28848863ce5SAlexandre TORGUE mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 28948863ce5SAlexandre TORGUE writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 29048863ce5SAlexandre TORGUE ioaddr + MTL_CHAN_INT_CTRL(channel)); 29148863ce5SAlexandre TORGUE } 29248863ce5SAlexandre TORGUE 2936deee222SJoao Pinto static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 294a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 29548863ce5SAlexandre TORGUE { 2966deee222SJoao Pinto u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 29752a76235SJose Abreu unsigned int tqs = fifosz / 256 - 1; 2986deee222SJoao Pinto 2996deee222SJoao Pinto if (mode == SF_DMA_MODE) { 3006deee222SJoao Pinto pr_debug("GMAC: enable TX store and forward mode\n"); 3016deee222SJoao Pinto /* Transmit COE type 2 cannot be done in cut-through mode. */ 3026deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TSF; 3036deee222SJoao Pinto } else { 3046deee222SJoao Pinto pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 3056deee222SJoao Pinto mtl_tx_op &= ~MTL_OP_MODE_TSF; 3066deee222SJoao Pinto mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 3076deee222SJoao Pinto /* Set the transmit threshold */ 3086deee222SJoao Pinto if (mode <= 32) 3096deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_32; 3106deee222SJoao Pinto else if (mode <= 64) 3116deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_64; 3126deee222SJoao Pinto else if (mode <= 96) 3136deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_96; 3146deee222SJoao Pinto else if (mode <= 128) 3156deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_128; 3166deee222SJoao Pinto else if (mode <= 192) 3176deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_192; 3186deee222SJoao Pinto else if (mode <= 256) 3196deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_256; 3206deee222SJoao Pinto else if (mode <= 384) 3216deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_384; 3226deee222SJoao Pinto else 3236deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_512; 3246deee222SJoao Pinto } 3256deee222SJoao Pinto /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 3266deee222SJoao Pinto * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 3276deee222SJoao Pinto * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 3286deee222SJoao Pinto * with reset values: TXQEN off, TQS 256 bytes. 3296deee222SJoao Pinto * 33052a76235SJose Abreu * TXQEN must be written for multi-channel operation and TQS must 33152a76235SJose Abreu * reflect the available fifo size per queue (total fifo size / number 33252a76235SJose Abreu * of enabled queues). 3336deee222SJoao Pinto */ 334a0daae13SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 335a0daae13SJose Abreu if (qmode != MTL_QUEUE_AVB) 33652a76235SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 337a0daae13SJose Abreu else 338a0daae13SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 33952a76235SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; 34052a76235SJose Abreu mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; 34152a76235SJose Abreu 3426deee222SJoao Pinto writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 34348863ce5SAlexandre TORGUE } 34448863ce5SAlexandre TORGUE 34548863ce5SAlexandre TORGUE static void dwmac4_get_hw_feature(void __iomem *ioaddr, 34648863ce5SAlexandre TORGUE struct dma_features *dma_cap) 34748863ce5SAlexandre TORGUE { 34848863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 34948863ce5SAlexandre TORGUE 35048863ce5SAlexandre TORGUE /* MAC HW feature0 */ 35148863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 35248863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 35348863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 354c1be0022SJose Abreu dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 35548863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 35648863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 35748863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 35848863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 35948863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 36048863ce5SAlexandre TORGUE /* MMC */ 36148863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 36248863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 36348863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 36448863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 36548863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 36648863ce5SAlexandre TORGUE /* TX and RX csum */ 36748863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 36848863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 3691d982e93SJose Abreu dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27; 370c9b10043SJose Abreu dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9; 37148863ce5SAlexandre TORGUE 37248863ce5SAlexandre TORGUE /* MAC HW feature1 */ 37348863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 374dc07f5fdSJose Abreu dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27; 375b8ef7020SBiao Huang dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; 37648863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 37748863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 3788c6fc097SJose Abreu dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17; 379560c07cbSThierry Reding 380560c07cbSThierry Reding dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14; 381560c07cbSThierry Reding switch (dma_cap->addr64) { 382560c07cbSThierry Reding case 0: 383560c07cbSThierry Reding dma_cap->addr64 = 32; 384560c07cbSThierry Reding break; 385560c07cbSThierry Reding case 1: 386560c07cbSThierry Reding dma_cap->addr64 = 40; 387560c07cbSThierry Reding break; 388560c07cbSThierry Reding case 2: 389560c07cbSThierry Reding dma_cap->addr64 = 48; 390560c07cbSThierry Reding break; 391560c07cbSThierry Reding default: 392560c07cbSThierry Reding dma_cap->addr64 = 32; 393560c07cbSThierry Reding break; 394560c07cbSThierry Reding } 395560c07cbSThierry Reding 39611fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 39711fbf811SThierry Reding * shifting and store the sizes in bytes. 39811fbf811SThierry Reding */ 39911fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 40011fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 40148863ce5SAlexandre TORGUE /* MAC HW feature2 */ 40248863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 40348863ce5SAlexandre TORGUE /* TX and RX number of channels */ 40448863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 40548863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 40648863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 40748863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 4089eb12474Sjpinto /* TX and RX number of queues */ 4099eb12474Sjpinto dma_cap->number_rx_queues = 4109eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 4119eb12474Sjpinto dma_cap->number_tx_queues = 4129eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 4139a8a02c9SJose Abreu /* PPS output */ 4149a8a02c9SJose Abreu dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24; 41548863ce5SAlexandre TORGUE 41648863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 41748863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 4188bf993a5SJose Abreu 4198bf993a5SJose Abreu /* MAC HW feature3 */ 4208bf993a5SJose Abreu hw_cap = readl(ioaddr + GMAC_HW_FEATURE3); 4218bf993a5SJose Abreu 4228bf993a5SJose Abreu /* 5.10 Features */ 4238bf993a5SJose Abreu dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28; 42458ae9281SJose Abreu dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27; 4257c728274SJose Abreu dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26; 426504723afSJose Abreu dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20; 427504723afSJose Abreu dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17; 428504723afSJose Abreu dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16; 4294dbbe8ddSJose Abreu dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13; 4304dbbe8ddSJose Abreu dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11; 4314dbbe8ddSJose Abreu dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10; 432e94e3f3bSJose Abreu dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5; 43348863ce5SAlexandre TORGUE } 43448863ce5SAlexandre TORGUE 43548863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 43648863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 43748863ce5SAlexandre TORGUE { 43848863ce5SAlexandre TORGUE u32 value; 43948863ce5SAlexandre TORGUE 44048863ce5SAlexandre TORGUE if (en) { 44148863ce5SAlexandre TORGUE /* enable TSO */ 44248863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 44348863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 44448863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 44548863ce5SAlexandre TORGUE } else { 44648863ce5SAlexandre TORGUE /* enable TSO */ 44748863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 44848863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 44948863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 45048863ce5SAlexandre TORGUE } 45148863ce5SAlexandre TORGUE } 45248863ce5SAlexandre TORGUE 4531f705bc6SJose Abreu static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 4541f705bc6SJose Abreu { 4551f705bc6SJose Abreu u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4561f705bc6SJose Abreu 4571f705bc6SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 4581f705bc6SJose Abreu if (qmode != MTL_QUEUE_AVB) 4591f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 4601f705bc6SJose Abreu else 4611f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 4621f705bc6SJose Abreu 4631f705bc6SJose Abreu writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4641f705bc6SJose Abreu } 4651f705bc6SJose Abreu 4664205c88eSJose Abreu static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 4674205c88eSJose Abreu { 4684205c88eSJose Abreu u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4694205c88eSJose Abreu 4704205c88eSJose Abreu value &= ~DMA_RBSZ_MASK; 4714205c88eSJose Abreu value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK; 4724205c88eSJose Abreu 4734205c88eSJose Abreu writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4744205c88eSJose Abreu } 4754205c88eSJose Abreu 4768c6fc097SJose Abreu static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan) 4778c6fc097SJose Abreu { 4788c6fc097SJose Abreu u32 value = readl(ioaddr + GMAC_EXT_CONFIG); 4798c6fc097SJose Abreu 4808c6fc097SJose Abreu value &= ~GMAC_CONFIG_HDSMS; 4818c6fc097SJose Abreu value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ 4828c6fc097SJose Abreu writel(value, ioaddr + GMAC_EXT_CONFIG); 4838c6fc097SJose Abreu 4848c6fc097SJose Abreu value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 4858c6fc097SJose Abreu if (en) 4868c6fc097SJose Abreu value |= DMA_CONTROL_SPH; 4878c6fc097SJose Abreu else 4888c6fc097SJose Abreu value &= ~DMA_CONTROL_SPH; 4898c6fc097SJose Abreu writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 4908c6fc097SJose Abreu } 4918c6fc097SJose Abreu 49258ae9281SJose Abreu static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) 49358ae9281SJose Abreu { 49458ae9281SJose Abreu u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 49558ae9281SJose Abreu 49658ae9281SJose Abreu if (en) 49758ae9281SJose Abreu value |= DMA_CONTROL_EDSE; 49858ae9281SJose Abreu else 49958ae9281SJose Abreu value &= ~DMA_CONTROL_EDSE; 50058ae9281SJose Abreu 50158ae9281SJose Abreu writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 50258ae9281SJose Abreu 50358ae9281SJose Abreu value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE; 50458ae9281SJose Abreu if (en && !value) 50558ae9281SJose Abreu return -EIO; 50658ae9281SJose Abreu 50758ae9281SJose Abreu writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL); 50858ae9281SJose Abreu return 0; 50958ae9281SJose Abreu } 51058ae9281SJose Abreu 51148863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 51248863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 51348863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 51447f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 51547f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 51647f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 51748863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 51848863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 5196deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 5206deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 52148863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 52248863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 52348863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 52448863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 52548863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 52648863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 52748863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 52848863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 52948863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 53048863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 53148863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 53248863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 53348863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 53448863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 5351f705bc6SJose Abreu .qmode = dwmac4_qmode, 5364205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 5378c6fc097SJose Abreu .enable_sph = dwmac4_enable_sph, 53848863ce5SAlexandre TORGUE }; 53948863ce5SAlexandre TORGUE 54048863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 54148863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 54248863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 543*879c348cSOng Boon Leong .init_chan = dwmac410_dma_init_channel, 54447f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 54547f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 54648863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 54748863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 5486deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 5496deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 55048863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 55148863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 55248863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 55348863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 55448863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 55548863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 55648863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 55748863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 55848863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 55948863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 56048863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 56148863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 56248863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 56348863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 5641f705bc6SJose Abreu .qmode = dwmac4_qmode, 5654205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 5668c6fc097SJose Abreu .enable_sph = dwmac4_enable_sph, 56758ae9281SJose Abreu .enable_tbs = dwmac4_enable_tbs, 56848863ce5SAlexandre TORGUE }; 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