148863ce5SAlexandre TORGUE /* 248863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 348863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 448863ce5SAlexandre TORGUE * 548863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 648863ce5SAlexandre TORGUE * 748863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 848863ce5SAlexandre TORGUE * 948863ce5SAlexandre TORGUE * This program is free software; you can redistribute it and/or modify it 1048863ce5SAlexandre TORGUE * under the terms and conditions of the GNU General Public License, 1148863ce5SAlexandre TORGUE * version 2, as published by the Free Software Foundation. 1248863ce5SAlexandre TORGUE * 1348863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1448863ce5SAlexandre TORGUE */ 1548863ce5SAlexandre TORGUE 1648863ce5SAlexandre TORGUE #include <linux/io.h> 1748863ce5SAlexandre TORGUE #include "dwmac4.h" 1848863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1948863ce5SAlexandre TORGUE 2048863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 2148863ce5SAlexandre TORGUE { 2248863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2348863ce5SAlexandre TORGUE int i; 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2648863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2748863ce5SAlexandre TORGUE 2848863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2948863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 3048863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 3148863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 3248863ce5SAlexandre TORGUE 336b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3448863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3548863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3648863ce5SAlexandre TORGUE 376b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3848863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3948863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 4048863ce5SAlexandre TORGUE 4148863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 4248863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4348863ce5SAlexandre TORGUE * set). 4448863ce5SAlexandre TORGUE */ 4548863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4648863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4748863ce5SAlexandre TORGUE case 256: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 128: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 64: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 32: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 16: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 8: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE case 4: 6648863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6748863ce5SAlexandre TORGUE break; 6848863ce5SAlexandre TORGUE } 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7148863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 7248863ce5SAlexandre TORGUE } 7348863ce5SAlexandre TORGUE 7489caaa2dSNiklas Cassel static void dwmac4_dma_init_channel(void __iomem *ioaddr, 7589caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 7648863ce5SAlexandre TORGUE u32 dma_tx_phy, u32 dma_rx_phy, 7748863ce5SAlexandre TORGUE u32 channel) 7848863ce5SAlexandre TORGUE { 7948863ce5SAlexandre TORGUE u32 value; 8089caaa2dSNiklas Cassel int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 8189caaa2dSNiklas Cassel int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 8248863ce5SAlexandre TORGUE 8348863ce5SAlexandre TORGUE /* set PBL for each channels. Currently we affect same configuration 8448863ce5SAlexandre TORGUE * on each channel 8548863ce5SAlexandre TORGUE */ 8648863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 874022d039SNiklas Cassel if (dma_cfg->pblx8) 8848863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 8948863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 9048863ce5SAlexandre TORGUE 9148863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 9289caaa2dSNiklas Cassel value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 9348863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 9448863ce5SAlexandre TORGUE 9548863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 9689caaa2dSNiklas Cassel value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 9748863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 9848863ce5SAlexandre TORGUE 9948863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 10048863ce5SAlexandre TORGUE writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 10148863ce5SAlexandre TORGUE 10248863ce5SAlexandre TORGUE writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 10348863ce5SAlexandre TORGUE writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 10448863ce5SAlexandre TORGUE } 10548863ce5SAlexandre TORGUE 10650ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 10750ca903aSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 10850ca903aSNiklas Cassel u32 dma_tx, u32 dma_rx, int atds) 10948863ce5SAlexandre TORGUE { 11048863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 11148863ce5SAlexandre TORGUE int i; 11248863ce5SAlexandre TORGUE 11348863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 11450ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 11548863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 11648863ce5SAlexandre TORGUE 11748863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 11850ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 11948863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 12048863ce5SAlexandre TORGUE 12150ca903aSNiklas Cassel if (dma_cfg->aal) 12248863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 12348863ce5SAlexandre TORGUE 12448863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 12548863ce5SAlexandre TORGUE 12648863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 12789caaa2dSNiklas Cassel dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i); 12848863ce5SAlexandre TORGUE } 12948863ce5SAlexandre TORGUE 130fbf68229SLABBE Corentin static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 131fbf68229SLABBE Corentin u32 *reg_space) 13248863ce5SAlexandre TORGUE { 133fbf68229SLABBE Corentin reg_space[DMA_CHAN_CONTROL(channel) / 4] = 134fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CONTROL(channel)); 135fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 136fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 137fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 138fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 139fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 140fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 141fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 142fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 143fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 144fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 145fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 146fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 147fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 148fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 149fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 150fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 151fbf68229SLABBE Corentin reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 152fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 153fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 154fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 155fbf68229SLABBE Corentin reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 156fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 157fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 158fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 159fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 160fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 161fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 162fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 163fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 164fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 165fbf68229SLABBE Corentin reg_space[DMA_CHAN_STATUS(channel) / 4] = 166fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_STATUS(channel)); 16748863ce5SAlexandre TORGUE } 16848863ce5SAlexandre TORGUE 169fbf68229SLABBE Corentin static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 17048863ce5SAlexandre TORGUE { 17148863ce5SAlexandre TORGUE int i; 17248863ce5SAlexandre TORGUE 17348863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 174fbf68229SLABBE Corentin _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 17548863ce5SAlexandre TORGUE } 17648863ce5SAlexandre TORGUE 17748863ce5SAlexandre TORGUE static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 17848863ce5SAlexandre TORGUE { 17948863ce5SAlexandre TORGUE int i; 18048863ce5SAlexandre TORGUE 18148863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 18248863ce5SAlexandre TORGUE writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 18348863ce5SAlexandre TORGUE } 18448863ce5SAlexandre TORGUE 1856deee222SJoao Pinto static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 1866deee222SJoao Pinto u32 channel, int fifosz) 18748863ce5SAlexandre TORGUE { 1886deee222SJoao Pinto unsigned int rqs = fifosz / 256 - 1; 1896deee222SJoao Pinto u32 mtl_rx_op, mtl_rx_int; 19048863ce5SAlexandre TORGUE 19148863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 19248863ce5SAlexandre TORGUE 1936deee222SJoao Pinto if (mode == SF_DMA_MODE) { 19448863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 19548863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 19648863ce5SAlexandre TORGUE } else { 1976deee222SJoao Pinto pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 19848863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 19948863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 2006deee222SJoao Pinto if (mode <= 32) 20148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 2026deee222SJoao Pinto else if (mode <= 64) 20348863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 2046deee222SJoao Pinto else if (mode <= 96) 20548863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 20648863ce5SAlexandre TORGUE else 20748863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 20848863ce5SAlexandre TORGUE } 20948863ce5SAlexandre TORGUE 210356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 211356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 212356b7557SThierry Reding 213356b7557SThierry Reding /* enable flow control only if each channel gets 4 KiB or more FIFO */ 2146deee222SJoao Pinto if (fifosz >= 4096) { 215356b7557SThierry Reding unsigned int rfd, rfa; 216356b7557SThierry Reding 217356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC; 218356b7557SThierry Reding 219356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames, 220356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes. 221356b7557SThierry Reding * 222356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame, 223356b7557SThierry Reding * i.e. 1500 bytes. 224356b7557SThierry Reding */ 2256deee222SJoao Pinto switch (fifosz) { 226356b7557SThierry Reding case 4096: 227356b7557SThierry Reding /* This violates the above formula because of FIFO size 228356b7557SThierry Reding * limit therefore overflow may occur in spite of this. 229356b7557SThierry Reding */ 230356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */ 231356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */ 232356b7557SThierry Reding break; 233356b7557SThierry Reding 234356b7557SThierry Reding case 8192: 235356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 236356b7557SThierry Reding rfa = 0x0a; /* Full-6K */ 237356b7557SThierry Reding break; 238356b7557SThierry Reding 239356b7557SThierry Reding case 16384: 240356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 241356b7557SThierry Reding rfa = 0x12; /* Full-10K */ 242356b7557SThierry Reding break; 243356b7557SThierry Reding 244356b7557SThierry Reding default: 245356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 246356b7557SThierry Reding rfa = 0x1e; /* Full-16K */ 247356b7557SThierry Reding break; 248356b7557SThierry Reding } 249356b7557SThierry Reding 250356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 251356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 252356b7557SThierry Reding 253356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 254356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 255356b7557SThierry Reding } 256356b7557SThierry Reding 25748863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 25848863ce5SAlexandre TORGUE 25948863ce5SAlexandre TORGUE /* Enable MTL RX overflow */ 26048863ce5SAlexandre TORGUE mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 26148863ce5SAlexandre TORGUE writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 26248863ce5SAlexandre TORGUE ioaddr + MTL_CHAN_INT_CTRL(channel)); 26348863ce5SAlexandre TORGUE } 26448863ce5SAlexandre TORGUE 2656deee222SJoao Pinto static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 2666deee222SJoao Pinto u32 channel) 26748863ce5SAlexandre TORGUE { 2686deee222SJoao Pinto u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 2696deee222SJoao Pinto 2706deee222SJoao Pinto if (mode == SF_DMA_MODE) { 2716deee222SJoao Pinto pr_debug("GMAC: enable TX store and forward mode\n"); 2726deee222SJoao Pinto /* Transmit COE type 2 cannot be done in cut-through mode. */ 2736deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TSF; 2746deee222SJoao Pinto } else { 2756deee222SJoao Pinto pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 2766deee222SJoao Pinto mtl_tx_op &= ~MTL_OP_MODE_TSF; 2776deee222SJoao Pinto mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 2786deee222SJoao Pinto /* Set the transmit threshold */ 2796deee222SJoao Pinto if (mode <= 32) 2806deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_32; 2816deee222SJoao Pinto else if (mode <= 64) 2826deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_64; 2836deee222SJoao Pinto else if (mode <= 96) 2846deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_96; 2856deee222SJoao Pinto else if (mode <= 128) 2866deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_128; 2876deee222SJoao Pinto else if (mode <= 192) 2886deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_192; 2896deee222SJoao Pinto else if (mode <= 256) 2906deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_256; 2916deee222SJoao Pinto else if (mode <= 384) 2926deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_384; 2936deee222SJoao Pinto else 2946deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_512; 2956deee222SJoao Pinto } 2966deee222SJoao Pinto /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 2976deee222SJoao Pinto * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 2986deee222SJoao Pinto * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 2996deee222SJoao Pinto * with reset values: TXQEN off, TQS 256 bytes. 3006deee222SJoao Pinto * 3016deee222SJoao Pinto * Write the bits in both cases, since it will have no effect when RO. 3026deee222SJoao Pinto * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 3036deee222SJoao Pinto * be RO, however, writing the whole TQS field will result in a value 3046deee222SJoao Pinto * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 3056deee222SJoao Pinto */ 3066deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 3076deee222SJoao Pinto writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 30848863ce5SAlexandre TORGUE } 30948863ce5SAlexandre TORGUE 31048863ce5SAlexandre TORGUE static void dwmac4_get_hw_feature(void __iomem *ioaddr, 31148863ce5SAlexandre TORGUE struct dma_features *dma_cap) 31248863ce5SAlexandre TORGUE { 31348863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 31448863ce5SAlexandre TORGUE 31548863ce5SAlexandre TORGUE /* MAC HW feature0 */ 31648863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 31748863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 31848863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 31948863ce5SAlexandre TORGUE dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 32048863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 32148863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 32248863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 32348863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 32448863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 32548863ce5SAlexandre TORGUE /* MMC */ 32648863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 32748863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 32848863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 32948863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 33048863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 33148863ce5SAlexandre TORGUE /* TX and RX csum */ 33248863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 33348863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 33448863ce5SAlexandre TORGUE 33548863ce5SAlexandre TORGUE /* MAC HW feature1 */ 33648863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 33748863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 33848863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 33911fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 34011fbf811SThierry Reding * shifting and store the sizes in bytes. 34111fbf811SThierry Reding */ 34211fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 34311fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 34448863ce5SAlexandre TORGUE /* MAC HW feature2 */ 34548863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 34648863ce5SAlexandre TORGUE /* TX and RX number of channels */ 34748863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 34848863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 34948863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 35048863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 3519eb12474Sjpinto /* TX and RX number of queues */ 3529eb12474Sjpinto dma_cap->number_rx_queues = 3539eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 3549eb12474Sjpinto dma_cap->number_tx_queues = 3559eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 35648863ce5SAlexandre TORGUE 35748863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 35848863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 35948863ce5SAlexandre TORGUE } 36048863ce5SAlexandre TORGUE 36148863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 36248863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 36348863ce5SAlexandre TORGUE { 36448863ce5SAlexandre TORGUE u32 value; 36548863ce5SAlexandre TORGUE 36648863ce5SAlexandre TORGUE if (en) { 36748863ce5SAlexandre TORGUE /* enable TSO */ 36848863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 36948863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 37048863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 37148863ce5SAlexandre TORGUE } else { 37248863ce5SAlexandre TORGUE /* enable TSO */ 37348863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 37448863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 37548863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 37648863ce5SAlexandre TORGUE } 37748863ce5SAlexandre TORGUE } 37848863ce5SAlexandre TORGUE 37948863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 38048863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 38148863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 38248863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 38348863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 3846deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 3856deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 38648863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 38748863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 38848863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 38948863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 39048863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 39148863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 39248863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 39348863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 39448863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 39548863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 39648863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 39748863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 39848863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 39948863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 40048863ce5SAlexandre TORGUE }; 40148863ce5SAlexandre TORGUE 40248863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 40348863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 40448863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 40548863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 40648863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 4076deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 4086deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 40948863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 41048863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 41148863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 41248863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 41348863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 41448863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 41548863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 41648863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 41748863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 41848863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 41948863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 42048863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 42148863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 42248863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 42348863ce5SAlexandre TORGUE }; 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