175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 248863ce5SAlexandre TORGUE /* 348863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 448863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 548863ce5SAlexandre TORGUE * 648863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 748863ce5SAlexandre TORGUE * 848863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 948863ce5SAlexandre TORGUE * 1048863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1148863ce5SAlexandre TORGUE */ 1248863ce5SAlexandre TORGUE 1348863ce5SAlexandre TORGUE #include <linux/io.h> 1448863ce5SAlexandre TORGUE #include "dwmac4.h" 1548863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1648863ce5SAlexandre TORGUE 1748863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 1848863ce5SAlexandre TORGUE { 1948863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2048863ce5SAlexandre TORGUE int i; 2148863ce5SAlexandre TORGUE 2248863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2348863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2648863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 2748863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 2848863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 2948863ce5SAlexandre TORGUE 306b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3148863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3248863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3348863ce5SAlexandre TORGUE 346b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3548863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3648863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 3748863ce5SAlexandre TORGUE 3848863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 3948863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4048863ce5SAlexandre TORGUE * set). 4148863ce5SAlexandre TORGUE */ 4248863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4348863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4448863ce5SAlexandre TORGUE case 256: 4548863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4648863ce5SAlexandre TORGUE break; 4748863ce5SAlexandre TORGUE case 128: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 64: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 32: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 16: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 8: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 4: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE } 6648863ce5SAlexandre TORGUE } 6748863ce5SAlexandre TORGUE 6848863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7172de4655SColin Ian King static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, 7289caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 7306a80a7dSJose Abreu dma_addr_t dma_rx_phy, u32 chan) 7448863ce5SAlexandre TORGUE { 7548863ce5SAlexandre TORGUE u32 value; 7647f2a9ceSJoao Pinto u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 7748863ce5SAlexandre TORGUE 7847f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 7947f2a9ceSJoao Pinto value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 8047f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 8147f2a9ceSJoao Pinto 82560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 83560c07cbSThierry Reding writel(upper_32_bits(dma_rx_phy), 84560c07cbSThierry Reding ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); 85560c07cbSThierry Reding 8606a80a7dSJose Abreu writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); 8747f2a9ceSJoao Pinto } 8847f2a9ceSJoao Pinto 8972de4655SColin Ian King static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, 9047f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, 9106a80a7dSJose Abreu dma_addr_t dma_tx_phy, u32 chan) 9247f2a9ceSJoao Pinto { 9347f2a9ceSJoao Pinto u32 value; 9447f2a9ceSJoao Pinto u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 9547f2a9ceSJoao Pinto 9647f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 9747f2a9ceSJoao Pinto value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 9867e1c406SJose Abreu 9967e1c406SJose Abreu /* Enable OSP to get best performance */ 10067e1c406SJose Abreu value |= DMA_CONTROL_OSP; 10167e1c406SJose Abreu 10247f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 10347f2a9ceSJoao Pinto 104560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 105560c07cbSThierry Reding writel(upper_32_bits(dma_tx_phy), 106560c07cbSThierry Reding ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan)); 107560c07cbSThierry Reding 10806a80a7dSJose Abreu writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); 10947f2a9ceSJoao Pinto } 11047f2a9ceSJoao Pinto 11172de4655SColin Ian King static void dwmac4_dma_init_channel(void __iomem *ioaddr, 11247f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, u32 chan) 11347f2a9ceSJoao Pinto { 11447f2a9ceSJoao Pinto u32 value; 11547f2a9ceSJoao Pinto 11647f2a9ceSJoao Pinto /* common channel control register config */ 11747f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 1184022d039SNiklas Cassel if (dma_cfg->pblx8) 11948863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 12047f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 12148863ce5SAlexandre TORGUE 12248863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 12347f2a9ceSJoao Pinto writel(DMA_CHAN_INTR_DEFAULT_MASK, 12447f2a9ceSJoao Pinto ioaddr + DMA_CHAN_INTR_ENA(chan)); 12548863ce5SAlexandre TORGUE } 12648863ce5SAlexandre TORGUE 12750ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 12824aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds) 12948863ce5SAlexandre TORGUE { 13048863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 13148863ce5SAlexandre TORGUE 13248863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 13350ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 13448863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 13548863ce5SAlexandre TORGUE 13648863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 13750ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 13848863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 13948863ce5SAlexandre TORGUE 14050ca903aSNiklas Cassel if (dma_cfg->aal) 14148863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 14248863ce5SAlexandre TORGUE 143560c07cbSThierry Reding if (dma_cfg->eame) 144560c07cbSThierry Reding value |= DMA_SYS_BUS_EAME; 145560c07cbSThierry Reding 14648863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 14748863ce5SAlexandre TORGUE } 14848863ce5SAlexandre TORGUE 149fbf68229SLABBE Corentin static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 150fbf68229SLABBE Corentin u32 *reg_space) 15148863ce5SAlexandre TORGUE { 152fbf68229SLABBE Corentin reg_space[DMA_CHAN_CONTROL(channel) / 4] = 153fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CONTROL(channel)); 154fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 155fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 156fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 157fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 158fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 159fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 160fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 161fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 162fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 163fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 164fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 165fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 166fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 167fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 168fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 169fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 170fbf68229SLABBE Corentin reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 171fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 172fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 173fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 174fbf68229SLABBE Corentin reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 175fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 176fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 177fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 178fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 179fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 180fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 181fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 182fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 183fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 184fbf68229SLABBE Corentin reg_space[DMA_CHAN_STATUS(channel) / 4] = 185fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_STATUS(channel)); 18648863ce5SAlexandre TORGUE } 18748863ce5SAlexandre TORGUE 188fbf68229SLABBE Corentin static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 18948863ce5SAlexandre TORGUE { 19048863ce5SAlexandre TORGUE int i; 19148863ce5SAlexandre TORGUE 19248863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 193fbf68229SLABBE Corentin _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 19448863ce5SAlexandre TORGUE } 19548863ce5SAlexandre TORGUE 1963c55d4d0SJoao Pinto static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) 19748863ce5SAlexandre TORGUE { 1983c55d4d0SJoao Pinto u32 chan; 19948863ce5SAlexandre TORGUE 2003c55d4d0SJoao Pinto for (chan = 0; chan < number_chan; chan++) 2013c55d4d0SJoao Pinto writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(chan)); 20248863ce5SAlexandre TORGUE } 20348863ce5SAlexandre TORGUE 2046deee222SJoao Pinto static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 205a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 20648863ce5SAlexandre TORGUE { 2076deee222SJoao Pinto unsigned int rqs = fifosz / 256 - 1; 2086deee222SJoao Pinto u32 mtl_rx_op, mtl_rx_int; 20948863ce5SAlexandre TORGUE 21048863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 21148863ce5SAlexandre TORGUE 2126deee222SJoao Pinto if (mode == SF_DMA_MODE) { 21348863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 21448863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 21548863ce5SAlexandre TORGUE } else { 2166deee222SJoao Pinto pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 21748863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 21848863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 2196deee222SJoao Pinto if (mode <= 32) 22048863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 2216deee222SJoao Pinto else if (mode <= 64) 22248863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 2236deee222SJoao Pinto else if (mode <= 96) 22448863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 22548863ce5SAlexandre TORGUE else 22648863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 22748863ce5SAlexandre TORGUE } 22848863ce5SAlexandre TORGUE 229356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 230356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 231356b7557SThierry Reding 232a0daae13SJose Abreu /* Enable flow control only if each channel gets 4 KiB or more FIFO and 233a0daae13SJose Abreu * only if channel is not an AVB channel. 234a0daae13SJose Abreu */ 235a0daae13SJose Abreu if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 236356b7557SThierry Reding unsigned int rfd, rfa; 237356b7557SThierry Reding 238356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC; 239356b7557SThierry Reding 240356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames, 241356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes. 242356b7557SThierry Reding * 243356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame, 244356b7557SThierry Reding * i.e. 1500 bytes. 245356b7557SThierry Reding */ 2466deee222SJoao Pinto switch (fifosz) { 247356b7557SThierry Reding case 4096: 248356b7557SThierry Reding /* This violates the above formula because of FIFO size 249356b7557SThierry Reding * limit therefore overflow may occur in spite of this. 250356b7557SThierry Reding */ 251356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */ 252356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */ 253356b7557SThierry Reding break; 254356b7557SThierry Reding 255356b7557SThierry Reding case 8192: 256356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 257356b7557SThierry Reding rfa = 0x0a; /* Full-6K */ 258356b7557SThierry Reding break; 259356b7557SThierry Reding 260356b7557SThierry Reding case 16384: 261356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 262356b7557SThierry Reding rfa = 0x12; /* Full-10K */ 263356b7557SThierry Reding break; 264356b7557SThierry Reding 265356b7557SThierry Reding default: 266356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 267356b7557SThierry Reding rfa = 0x1e; /* Full-16K */ 268356b7557SThierry Reding break; 269356b7557SThierry Reding } 270356b7557SThierry Reding 271356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 272356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 273356b7557SThierry Reding 274356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 275356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 276356b7557SThierry Reding } 277356b7557SThierry Reding 27848863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 27948863ce5SAlexandre TORGUE 28048863ce5SAlexandre TORGUE /* Enable MTL RX overflow */ 28148863ce5SAlexandre TORGUE mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 28248863ce5SAlexandre TORGUE writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 28348863ce5SAlexandre TORGUE ioaddr + MTL_CHAN_INT_CTRL(channel)); 28448863ce5SAlexandre TORGUE } 28548863ce5SAlexandre TORGUE 2866deee222SJoao Pinto static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 287a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 28848863ce5SAlexandre TORGUE { 2896deee222SJoao Pinto u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 29052a76235SJose Abreu unsigned int tqs = fifosz / 256 - 1; 2916deee222SJoao Pinto 2926deee222SJoao Pinto if (mode == SF_DMA_MODE) { 2936deee222SJoao Pinto pr_debug("GMAC: enable TX store and forward mode\n"); 2946deee222SJoao Pinto /* Transmit COE type 2 cannot be done in cut-through mode. */ 2956deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TSF; 2966deee222SJoao Pinto } else { 2976deee222SJoao Pinto pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 2986deee222SJoao Pinto mtl_tx_op &= ~MTL_OP_MODE_TSF; 2996deee222SJoao Pinto mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 3006deee222SJoao Pinto /* Set the transmit threshold */ 3016deee222SJoao Pinto if (mode <= 32) 3026deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_32; 3036deee222SJoao Pinto else if (mode <= 64) 3046deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_64; 3056deee222SJoao Pinto else if (mode <= 96) 3066deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_96; 3076deee222SJoao Pinto else if (mode <= 128) 3086deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_128; 3096deee222SJoao Pinto else if (mode <= 192) 3106deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_192; 3116deee222SJoao Pinto else if (mode <= 256) 3126deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_256; 3136deee222SJoao Pinto else if (mode <= 384) 3146deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_384; 3156deee222SJoao Pinto else 3166deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_512; 3176deee222SJoao Pinto } 3186deee222SJoao Pinto /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 3196deee222SJoao Pinto * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 3206deee222SJoao Pinto * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 3216deee222SJoao Pinto * with reset values: TXQEN off, TQS 256 bytes. 3226deee222SJoao Pinto * 32352a76235SJose Abreu * TXQEN must be written for multi-channel operation and TQS must 32452a76235SJose Abreu * reflect the available fifo size per queue (total fifo size / number 32552a76235SJose Abreu * of enabled queues). 3266deee222SJoao Pinto */ 327a0daae13SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 328a0daae13SJose Abreu if (qmode != MTL_QUEUE_AVB) 32952a76235SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 330a0daae13SJose Abreu else 331a0daae13SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 33252a76235SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; 33352a76235SJose Abreu mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; 33452a76235SJose Abreu 3356deee222SJoao Pinto writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 33648863ce5SAlexandre TORGUE } 33748863ce5SAlexandre TORGUE 33848863ce5SAlexandre TORGUE static void dwmac4_get_hw_feature(void __iomem *ioaddr, 33948863ce5SAlexandre TORGUE struct dma_features *dma_cap) 34048863ce5SAlexandre TORGUE { 34148863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 34248863ce5SAlexandre TORGUE 34348863ce5SAlexandre TORGUE /* MAC HW feature0 */ 34448863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 34548863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 34648863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 347c1be0022SJose Abreu dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 34848863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 34948863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 35048863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 35148863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 35248863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 35348863ce5SAlexandre TORGUE /* MMC */ 35448863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 35548863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 35648863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 35748863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 35848863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 35948863ce5SAlexandre TORGUE /* TX and RX csum */ 36048863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 36148863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 3621d982e93SJose Abreu dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27; 363c9b10043SJose Abreu dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9; 36448863ce5SAlexandre TORGUE 36548863ce5SAlexandre TORGUE /* MAC HW feature1 */ 36648863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 367b8ef7020SBiao Huang dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; 36848863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 36948863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 370560c07cbSThierry Reding 371560c07cbSThierry Reding dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14; 372560c07cbSThierry Reding switch (dma_cap->addr64) { 373560c07cbSThierry Reding case 0: 374560c07cbSThierry Reding dma_cap->addr64 = 32; 375560c07cbSThierry Reding break; 376560c07cbSThierry Reding case 1: 377560c07cbSThierry Reding dma_cap->addr64 = 40; 378560c07cbSThierry Reding break; 379560c07cbSThierry Reding case 2: 380560c07cbSThierry Reding dma_cap->addr64 = 48; 381560c07cbSThierry Reding break; 382560c07cbSThierry Reding default: 383560c07cbSThierry Reding dma_cap->addr64 = 32; 384560c07cbSThierry Reding break; 385560c07cbSThierry Reding } 386560c07cbSThierry Reding 38711fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 38811fbf811SThierry Reding * shifting and store the sizes in bytes. 38911fbf811SThierry Reding */ 39011fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 39111fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 39248863ce5SAlexandre TORGUE /* MAC HW feature2 */ 39348863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 39448863ce5SAlexandre TORGUE /* TX and RX number of channels */ 39548863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 39648863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 39748863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 39848863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 3999eb12474Sjpinto /* TX and RX number of queues */ 4009eb12474Sjpinto dma_cap->number_rx_queues = 4019eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 4029eb12474Sjpinto dma_cap->number_tx_queues = 4039eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 4049a8a02c9SJose Abreu /* PPS output */ 4059a8a02c9SJose Abreu dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24; 40648863ce5SAlexandre TORGUE 40748863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 40848863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 4098bf993a5SJose Abreu 4108bf993a5SJose Abreu /* MAC HW feature3 */ 4118bf993a5SJose Abreu hw_cap = readl(ioaddr + GMAC_HW_FEATURE3); 4128bf993a5SJose Abreu 4138bf993a5SJose Abreu /* 5.10 Features */ 4148bf993a5SJose Abreu dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28; 4154dbbe8ddSJose Abreu dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13; 4164dbbe8ddSJose Abreu dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11; 4174dbbe8ddSJose Abreu dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10; 418e94e3f3bSJose Abreu dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5; 41948863ce5SAlexandre TORGUE } 42048863ce5SAlexandre TORGUE 42148863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 42248863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 42348863ce5SAlexandre TORGUE { 42448863ce5SAlexandre TORGUE u32 value; 42548863ce5SAlexandre TORGUE 42648863ce5SAlexandre TORGUE if (en) { 42748863ce5SAlexandre TORGUE /* enable TSO */ 42848863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 42948863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 43048863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 43148863ce5SAlexandre TORGUE } else { 43248863ce5SAlexandre TORGUE /* enable TSO */ 43348863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 43448863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 43548863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 43648863ce5SAlexandre TORGUE } 43748863ce5SAlexandre TORGUE } 43848863ce5SAlexandre TORGUE 4391f705bc6SJose Abreu static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 4401f705bc6SJose Abreu { 4411f705bc6SJose Abreu u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4421f705bc6SJose Abreu 4431f705bc6SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 4441f705bc6SJose Abreu if (qmode != MTL_QUEUE_AVB) 4451f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 4461f705bc6SJose Abreu else 4471f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 4481f705bc6SJose Abreu 4491f705bc6SJose Abreu writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4501f705bc6SJose Abreu } 4511f705bc6SJose Abreu 4524205c88eSJose Abreu static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 4534205c88eSJose Abreu { 4544205c88eSJose Abreu u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4554205c88eSJose Abreu 4564205c88eSJose Abreu value &= ~DMA_RBSZ_MASK; 4574205c88eSJose Abreu value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK; 4584205c88eSJose Abreu 4594205c88eSJose Abreu writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4604205c88eSJose Abreu } 4614205c88eSJose Abreu 46248863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 46348863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 46448863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 46547f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 46647f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 46747f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 46848863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 46948863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 4706deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 4716deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 47248863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 47348863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 47448863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 47548863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 47648863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 47748863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 47848863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 47948863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 48048863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 48148863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 48248863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 48348863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 48448863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 48548863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 4861f705bc6SJose Abreu .qmode = dwmac4_qmode, 4874205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 48848863ce5SAlexandre TORGUE }; 48948863ce5SAlexandre TORGUE 49048863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 49148863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 49248863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 49347f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 49447f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 49547f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 49648863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 49748863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 4986deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 4996deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 50048863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 50148863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 50248863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 50348863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 50448863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 50548863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 50648863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 50748863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 50848863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 50948863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 51048863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 51148863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 51248863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 51348863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 5141f705bc6SJose Abreu .qmode = dwmac4_qmode, 5154205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 51648863ce5SAlexandre TORGUE }; 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