148863ce5SAlexandre TORGUE /* 248863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 348863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 448863ce5SAlexandre TORGUE * 548863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 648863ce5SAlexandre TORGUE * 748863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 848863ce5SAlexandre TORGUE * 948863ce5SAlexandre TORGUE * This program is free software; you can redistribute it and/or modify it 1048863ce5SAlexandre TORGUE * under the terms and conditions of the GNU General Public License, 1148863ce5SAlexandre TORGUE * version 2, as published by the Free Software Foundation. 1248863ce5SAlexandre TORGUE * 1348863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1448863ce5SAlexandre TORGUE */ 1548863ce5SAlexandre TORGUE 1648863ce5SAlexandre TORGUE #include <linux/io.h> 1748863ce5SAlexandre TORGUE #include "dwmac4.h" 1848863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1948863ce5SAlexandre TORGUE 2048863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 2148863ce5SAlexandre TORGUE { 2248863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2348863ce5SAlexandre TORGUE int i; 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2648863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2748863ce5SAlexandre TORGUE 2848863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2948863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 3048863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 3148863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 3248863ce5SAlexandre TORGUE 336b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3448863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3548863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3648863ce5SAlexandre TORGUE 376b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3848863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3948863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 4048863ce5SAlexandre TORGUE 4148863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 4248863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4348863ce5SAlexandre TORGUE * set). 4448863ce5SAlexandre TORGUE */ 4548863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4648863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4748863ce5SAlexandre TORGUE case 256: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 128: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 64: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 32: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 16: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 8: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE case 4: 6648863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6748863ce5SAlexandre TORGUE break; 6848863ce5SAlexandre TORGUE } 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7148863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 7248863ce5SAlexandre TORGUE } 7348863ce5SAlexandre TORGUE 7448863ce5SAlexandre TORGUE static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl, 7548863ce5SAlexandre TORGUE u32 dma_tx_phy, u32 dma_rx_phy, 7648863ce5SAlexandre TORGUE u32 channel) 7748863ce5SAlexandre TORGUE { 7848863ce5SAlexandre TORGUE u32 value; 7948863ce5SAlexandre TORGUE 8048863ce5SAlexandre TORGUE /* set PBL for each channels. Currently we affect same configuration 8148863ce5SAlexandre TORGUE * on each channel 8248863ce5SAlexandre TORGUE */ 8348863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 8448863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 8548863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 8648863ce5SAlexandre TORGUE 8748863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 8848863ce5SAlexandre TORGUE value = value | (pbl << DMA_BUS_MODE_PBL_SHIFT); 8948863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 9048863ce5SAlexandre TORGUE 9148863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 9248863ce5SAlexandre TORGUE value = value | (pbl << DMA_BUS_MODE_RPBL_SHIFT); 9348863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 9448863ce5SAlexandre TORGUE 9548863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 9648863ce5SAlexandre TORGUE writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 9748863ce5SAlexandre TORGUE 9848863ce5SAlexandre TORGUE writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 9948863ce5SAlexandre TORGUE writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 10048863ce5SAlexandre TORGUE } 10148863ce5SAlexandre TORGUE 10250ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 10350ca903aSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 10450ca903aSNiklas Cassel u32 dma_tx, u32 dma_rx, int atds) 10548863ce5SAlexandre TORGUE { 10648863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 10748863ce5SAlexandre TORGUE int i; 10848863ce5SAlexandre TORGUE 10948863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 11050ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 11148863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 11248863ce5SAlexandre TORGUE 11348863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 11450ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 11548863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 11648863ce5SAlexandre TORGUE 11750ca903aSNiklas Cassel if (dma_cfg->aal) 11848863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 11948863ce5SAlexandre TORGUE 12048863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 12148863ce5SAlexandre TORGUE 12248863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 12350ca903aSNiklas Cassel dwmac4_dma_init_channel(ioaddr, dma_cfg->pbl, 12450ca903aSNiklas Cassel dma_tx, dma_rx, i); 12548863ce5SAlexandre TORGUE } 12648863ce5SAlexandre TORGUE 12748863ce5SAlexandre TORGUE static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel) 12848863ce5SAlexandre TORGUE { 12948863ce5SAlexandre TORGUE pr_debug(" Channel %d\n", channel); 13048863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_CONTROL, offset: 0x%x, val: 0x%x\n", 0, 13148863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_CONTROL(channel))); 13248863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_TX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x4, 13348863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_TX_CONTROL(channel))); 13448863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_RX_CONTROL, offset: 0x%x, val: 0x%x\n", 0x8, 13548863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_RX_CONTROL(channel))); 13648863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_TX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x14, 13748863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel))); 13848863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_RX_BASE_ADDR, offset: 0x%x, val: 0x%x\n", 0x1c, 13948863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel))); 14048863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_TX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x20, 14148863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel))); 14248863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_RX_END_ADDR, offset: 0x%x, val: 0x%x\n", 0x28, 14348863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel))); 14448863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_TX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x2c, 14548863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel))); 14648863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_RX_RING_LEN, offset: 0x%x, val: 0x%x\n", 0x30, 14748863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel))); 14848863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_INTR_ENA, offset: 0x%x, val: 0x%x\n", 0x34, 14948863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_INTR_ENA(channel))); 15048863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_RX_WATCHDOG, offset: 0x%x, val: 0x%x\n", 0x38, 15148863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel))); 15248863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_SLOT_CTRL_STATUS, offset: 0x%x, val: 0x%x\n", 0x3c, 15348863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel))); 15448863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_CUR_TX_DESC, offset: 0x%x, val: 0x%x\n", 0x44, 15548863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel))); 15648863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_CUR_RX_DESC, offset: 0x%x, val: 0x%x\n", 0x4c, 15748863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel))); 15848863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_CUR_TX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x54, 15948863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel))); 16048863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_CUR_RX_BUF_ADDR, offset: 0x%x, val: 0x%x\n", 0x5c, 16148863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel))); 16248863ce5SAlexandre TORGUE pr_debug("\tDMA_CHAN_STATUS, offset: 0x%x, val: 0x%x\n", 0x60, 16348863ce5SAlexandre TORGUE readl(ioaddr + DMA_CHAN_STATUS(channel))); 16448863ce5SAlexandre TORGUE } 16548863ce5SAlexandre TORGUE 16648863ce5SAlexandre TORGUE static void dwmac4_dump_dma_regs(void __iomem *ioaddr) 16748863ce5SAlexandre TORGUE { 16848863ce5SAlexandre TORGUE int i; 16948863ce5SAlexandre TORGUE 17048863ce5SAlexandre TORGUE pr_debug(" GMAC4 DMA registers\n"); 17148863ce5SAlexandre TORGUE 17248863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 17348863ce5SAlexandre TORGUE _dwmac4_dump_dma_regs(ioaddr, i); 17448863ce5SAlexandre TORGUE } 17548863ce5SAlexandre TORGUE 17648863ce5SAlexandre TORGUE static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 17748863ce5SAlexandre TORGUE { 17848863ce5SAlexandre TORGUE int i; 17948863ce5SAlexandre TORGUE 18048863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 18148863ce5SAlexandre TORGUE writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 18248863ce5SAlexandre TORGUE } 18348863ce5SAlexandre TORGUE 18448863ce5SAlexandre TORGUE static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, 18548863ce5SAlexandre TORGUE int rxmode, u32 channel) 18648863ce5SAlexandre TORGUE { 18748863ce5SAlexandre TORGUE u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; 18848863ce5SAlexandre TORGUE 18948863ce5SAlexandre TORGUE /* Following code only done for channel 0, other channels not yet 19048863ce5SAlexandre TORGUE * supported. 19148863ce5SAlexandre TORGUE */ 19248863ce5SAlexandre TORGUE mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 19348863ce5SAlexandre TORGUE 19448863ce5SAlexandre TORGUE if (txmode == SF_DMA_MODE) { 19548863ce5SAlexandre TORGUE pr_debug("GMAC: enable TX store and forward mode\n"); 19648863ce5SAlexandre TORGUE /* Transmit COE type 2 cannot be done in cut-through mode. */ 19748863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TSF; 19848863ce5SAlexandre TORGUE } else { 19948863ce5SAlexandre TORGUE pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode); 20048863ce5SAlexandre TORGUE mtl_tx_op &= ~MTL_OP_MODE_TSF; 20148863ce5SAlexandre TORGUE mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 20248863ce5SAlexandre TORGUE /* Set the transmit threshold */ 20348863ce5SAlexandre TORGUE if (txmode <= 32) 20448863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_32; 20548863ce5SAlexandre TORGUE else if (txmode <= 64) 20648863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_64; 20748863ce5SAlexandre TORGUE else if (txmode <= 96) 20848863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_96; 20948863ce5SAlexandre TORGUE else if (txmode <= 128) 21048863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_128; 21148863ce5SAlexandre TORGUE else if (txmode <= 192) 21248863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_192; 21348863ce5SAlexandre TORGUE else if (txmode <= 256) 21448863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_256; 21548863ce5SAlexandre TORGUE else if (txmode <= 384) 21648863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_384; 21748863ce5SAlexandre TORGUE else 21848863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_512; 21948863ce5SAlexandre TORGUE } 220436feafeSNiklas Cassel /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 221436feafeSNiklas Cassel * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 222436feafeSNiklas Cassel * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 223436feafeSNiklas Cassel * with reset values: TXQEN off, TQS 256 bytes. 224436feafeSNiklas Cassel * 225436feafeSNiklas Cassel * Write the bits in both cases, since it will have no effect when RO. 226436feafeSNiklas Cassel * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 227436feafeSNiklas Cassel * be RO, however, writing the whole TQS field will result in a value 228436feafeSNiklas Cassel * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 229436feafeSNiklas Cassel */ 230436feafeSNiklas Cassel mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 23148863ce5SAlexandre TORGUE writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 23248863ce5SAlexandre TORGUE 23348863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 23448863ce5SAlexandre TORGUE 23548863ce5SAlexandre TORGUE if (rxmode == SF_DMA_MODE) { 23648863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 23748863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 23848863ce5SAlexandre TORGUE } else { 23948863ce5SAlexandre TORGUE pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode); 24048863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 24148863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 24248863ce5SAlexandre TORGUE if (rxmode <= 32) 24348863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 24448863ce5SAlexandre TORGUE else if (rxmode <= 64) 24548863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 24648863ce5SAlexandre TORGUE else if (rxmode <= 96) 24748863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 24848863ce5SAlexandre TORGUE else 24948863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 25048863ce5SAlexandre TORGUE } 25148863ce5SAlexandre TORGUE 25248863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 25348863ce5SAlexandre TORGUE 25448863ce5SAlexandre TORGUE /* Enable MTL RX overflow */ 25548863ce5SAlexandre TORGUE mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 25648863ce5SAlexandre TORGUE writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 25748863ce5SAlexandre TORGUE ioaddr + MTL_CHAN_INT_CTRL(channel)); 25848863ce5SAlexandre TORGUE } 25948863ce5SAlexandre TORGUE 26048863ce5SAlexandre TORGUE static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, 26148863ce5SAlexandre TORGUE int rxmode, int rxfifosz) 26248863ce5SAlexandre TORGUE { 26348863ce5SAlexandre TORGUE /* Only Channel 0 is actually configured and used */ 26448863ce5SAlexandre TORGUE dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0); 26548863ce5SAlexandre TORGUE } 26648863ce5SAlexandre TORGUE 26748863ce5SAlexandre TORGUE static void dwmac4_get_hw_feature(void __iomem *ioaddr, 26848863ce5SAlexandre TORGUE struct dma_features *dma_cap) 26948863ce5SAlexandre TORGUE { 27048863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 27148863ce5SAlexandre TORGUE 27248863ce5SAlexandre TORGUE /* MAC HW feature0 */ 27348863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 27448863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 27548863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 27648863ce5SAlexandre TORGUE dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 27748863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 27848863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 27948863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 28048863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 28148863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 28248863ce5SAlexandre TORGUE /* MMC */ 28348863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 28448863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 28548863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 28648863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 28748863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 28848863ce5SAlexandre TORGUE /* TX and RX csum */ 28948863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 29048863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 29148863ce5SAlexandre TORGUE 29248863ce5SAlexandre TORGUE /* MAC HW feature1 */ 29348863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 29448863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 29548863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 29648863ce5SAlexandre TORGUE /* MAC HW feature2 */ 29748863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 29848863ce5SAlexandre TORGUE /* TX and RX number of channels */ 29948863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 30048863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 30148863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 30248863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 30348863ce5SAlexandre TORGUE 30448863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 30548863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 30648863ce5SAlexandre TORGUE } 30748863ce5SAlexandre TORGUE 30848863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 30948863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 31048863ce5SAlexandre TORGUE { 31148863ce5SAlexandre TORGUE u32 value; 31248863ce5SAlexandre TORGUE 31348863ce5SAlexandre TORGUE if (en) { 31448863ce5SAlexandre TORGUE /* enable TSO */ 31548863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 31648863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 31748863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 31848863ce5SAlexandre TORGUE } else { 31948863ce5SAlexandre TORGUE /* enable TSO */ 32048863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 32148863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 32248863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 32348863ce5SAlexandre TORGUE } 32448863ce5SAlexandre TORGUE } 32548863ce5SAlexandre TORGUE 32648863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 32748863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 32848863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 32948863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 33048863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 33148863ce5SAlexandre TORGUE .dma_mode = dwmac4_dma_operation_mode, 33248863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 33348863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 33448863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 33548863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 33648863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 33748863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 33848863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 33948863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 34048863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 34148863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 34248863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 34348863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 34448863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 34548863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 34648863ce5SAlexandre TORGUE }; 34748863ce5SAlexandre TORGUE 34848863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 34948863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 35048863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 35148863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 35248863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 35348863ce5SAlexandre TORGUE .dma_mode = dwmac4_dma_operation_mode, 35448863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 35548863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 35648863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 35748863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 35848863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 35948863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 36048863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 36148863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 36248863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 36348863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 36448863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 36548863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 36648863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 36748863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 36848863ce5SAlexandre TORGUE }; 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