148863ce5SAlexandre TORGUE /* 248863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 348863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 448863ce5SAlexandre TORGUE * 548863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 648863ce5SAlexandre TORGUE * 748863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 848863ce5SAlexandre TORGUE * 948863ce5SAlexandre TORGUE * This program is free software; you can redistribute it and/or modify it 1048863ce5SAlexandre TORGUE * under the terms and conditions of the GNU General Public License, 1148863ce5SAlexandre TORGUE * version 2, as published by the Free Software Foundation. 1248863ce5SAlexandre TORGUE * 1348863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1448863ce5SAlexandre TORGUE */ 1548863ce5SAlexandre TORGUE 1648863ce5SAlexandre TORGUE #include <linux/io.h> 1748863ce5SAlexandre TORGUE #include "dwmac4.h" 1848863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1948863ce5SAlexandre TORGUE 2048863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 2148863ce5SAlexandre TORGUE { 2248863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2348863ce5SAlexandre TORGUE int i; 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2648863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2748863ce5SAlexandre TORGUE 2848863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2948863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 3048863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 3148863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 3248863ce5SAlexandre TORGUE 336b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3448863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3548863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3648863ce5SAlexandre TORGUE 376b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3848863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3948863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 4048863ce5SAlexandre TORGUE 4148863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 4248863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4348863ce5SAlexandre TORGUE * set). 4448863ce5SAlexandre TORGUE */ 4548863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4648863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4748863ce5SAlexandre TORGUE case 256: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 128: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 64: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 32: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 16: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 8: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE case 4: 6648863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6748863ce5SAlexandre TORGUE break; 6848863ce5SAlexandre TORGUE } 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7148863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 7248863ce5SAlexandre TORGUE } 7348863ce5SAlexandre TORGUE 7489caaa2dSNiklas Cassel static void dwmac4_dma_init_channel(void __iomem *ioaddr, 7589caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 7648863ce5SAlexandre TORGUE u32 dma_tx_phy, u32 dma_rx_phy, 7748863ce5SAlexandre TORGUE u32 channel) 7848863ce5SAlexandre TORGUE { 7948863ce5SAlexandre TORGUE u32 value; 8089caaa2dSNiklas Cassel int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 8189caaa2dSNiklas Cassel int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 8248863ce5SAlexandre TORGUE 8348863ce5SAlexandre TORGUE /* set PBL for each channels. Currently we affect same configuration 8448863ce5SAlexandre TORGUE * on each channel 8548863ce5SAlexandre TORGUE */ 8648863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_CONTROL(channel)); 874022d039SNiklas Cassel if (dma_cfg->pblx8) 8848863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 8948863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_CONTROL(channel)); 9048863ce5SAlexandre TORGUE 9148863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 9289caaa2dSNiklas Cassel value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 9348863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_TX_CONTROL(channel)); 9448863ce5SAlexandre TORGUE 9548863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 9689caaa2dSNiklas Cassel value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 9748863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_CHAN_RX_CONTROL(channel)); 9848863ce5SAlexandre TORGUE 9948863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 10048863ce5SAlexandre TORGUE writel(DMA_CHAN_INTR_DEFAULT_MASK, ioaddr + DMA_CHAN_INTR_ENA(channel)); 10148863ce5SAlexandre TORGUE 10248863ce5SAlexandre TORGUE writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 10348863ce5SAlexandre TORGUE writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 10448863ce5SAlexandre TORGUE } 10548863ce5SAlexandre TORGUE 10650ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 10750ca903aSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 10850ca903aSNiklas Cassel u32 dma_tx, u32 dma_rx, int atds) 10948863ce5SAlexandre TORGUE { 11048863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 11148863ce5SAlexandre TORGUE int i; 11248863ce5SAlexandre TORGUE 11348863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 11450ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 11548863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 11648863ce5SAlexandre TORGUE 11748863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 11850ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 11948863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 12048863ce5SAlexandre TORGUE 12150ca903aSNiklas Cassel if (dma_cfg->aal) 12248863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 12348863ce5SAlexandre TORGUE 12448863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 12548863ce5SAlexandre TORGUE 12648863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 12789caaa2dSNiklas Cassel dwmac4_dma_init_channel(ioaddr, dma_cfg, dma_tx, dma_rx, i); 12848863ce5SAlexandre TORGUE } 12948863ce5SAlexandre TORGUE 130fbf68229SLABBE Corentin static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 131fbf68229SLABBE Corentin u32 *reg_space) 13248863ce5SAlexandre TORGUE { 133fbf68229SLABBE Corentin reg_space[DMA_CHAN_CONTROL(channel) / 4] = 134fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CONTROL(channel)); 135fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 136fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 137fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 138fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 139fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 140fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 141fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 142fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 143fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 144fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 145fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 146fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 147fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 148fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 149fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 150fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 151fbf68229SLABBE Corentin reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 152fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 153fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 154fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 155fbf68229SLABBE Corentin reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 156fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 157fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 158fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 159fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 160fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 161fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 162fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 163fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 164fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 165fbf68229SLABBE Corentin reg_space[DMA_CHAN_STATUS(channel) / 4] = 166fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_STATUS(channel)); 16748863ce5SAlexandre TORGUE } 16848863ce5SAlexandre TORGUE 169fbf68229SLABBE Corentin static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 17048863ce5SAlexandre TORGUE { 17148863ce5SAlexandre TORGUE int i; 17248863ce5SAlexandre TORGUE 17348863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 174fbf68229SLABBE Corentin _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 17548863ce5SAlexandre TORGUE } 17648863ce5SAlexandre TORGUE 17748863ce5SAlexandre TORGUE static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt) 17848863ce5SAlexandre TORGUE { 17948863ce5SAlexandre TORGUE int i; 18048863ce5SAlexandre TORGUE 18148863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 18248863ce5SAlexandre TORGUE writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(i)); 18348863ce5SAlexandre TORGUE } 18448863ce5SAlexandre TORGUE 18548863ce5SAlexandre TORGUE static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, 186356b7557SThierry Reding int rxmode, u32 channel, int rxfifosz) 18748863ce5SAlexandre TORGUE { 188356b7557SThierry Reding unsigned int rqs = rxfifosz / 256 - 1; 18948863ce5SAlexandre TORGUE u32 mtl_tx_op, mtl_rx_op, mtl_rx_int; 19048863ce5SAlexandre TORGUE 19148863ce5SAlexandre TORGUE /* Following code only done for channel 0, other channels not yet 19248863ce5SAlexandre TORGUE * supported. 19348863ce5SAlexandre TORGUE */ 19448863ce5SAlexandre TORGUE mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 19548863ce5SAlexandre TORGUE 19648863ce5SAlexandre TORGUE if (txmode == SF_DMA_MODE) { 19748863ce5SAlexandre TORGUE pr_debug("GMAC: enable TX store and forward mode\n"); 19848863ce5SAlexandre TORGUE /* Transmit COE type 2 cannot be done in cut-through mode. */ 19948863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TSF; 20048863ce5SAlexandre TORGUE } else { 20148863ce5SAlexandre TORGUE pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode); 20248863ce5SAlexandre TORGUE mtl_tx_op &= ~MTL_OP_MODE_TSF; 20348863ce5SAlexandre TORGUE mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 20448863ce5SAlexandre TORGUE /* Set the transmit threshold */ 20548863ce5SAlexandre TORGUE if (txmode <= 32) 20648863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_32; 20748863ce5SAlexandre TORGUE else if (txmode <= 64) 20848863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_64; 20948863ce5SAlexandre TORGUE else if (txmode <= 96) 21048863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_96; 21148863ce5SAlexandre TORGUE else if (txmode <= 128) 21248863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_128; 21348863ce5SAlexandre TORGUE else if (txmode <= 192) 21448863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_192; 21548863ce5SAlexandre TORGUE else if (txmode <= 256) 21648863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_256; 21748863ce5SAlexandre TORGUE else if (txmode <= 384) 21848863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_384; 21948863ce5SAlexandre TORGUE else 22048863ce5SAlexandre TORGUE mtl_tx_op |= MTL_OP_MODE_TTC_512; 22148863ce5SAlexandre TORGUE } 222436feafeSNiklas Cassel /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 223436feafeSNiklas Cassel * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 224436feafeSNiklas Cassel * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 225436feafeSNiklas Cassel * with reset values: TXQEN off, TQS 256 bytes. 226436feafeSNiklas Cassel * 227436feafeSNiklas Cassel * Write the bits in both cases, since it will have no effect when RO. 228436feafeSNiklas Cassel * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might 229436feafeSNiklas Cassel * be RO, however, writing the whole TQS field will result in a value 230436feafeSNiklas Cassel * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1. 231436feafeSNiklas Cassel */ 232436feafeSNiklas Cassel mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK; 23348863ce5SAlexandre TORGUE writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 23448863ce5SAlexandre TORGUE 23548863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 23648863ce5SAlexandre TORGUE 23748863ce5SAlexandre TORGUE if (rxmode == SF_DMA_MODE) { 23848863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 23948863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 24048863ce5SAlexandre TORGUE } else { 24148863ce5SAlexandre TORGUE pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode); 24248863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 24348863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 24448863ce5SAlexandre TORGUE if (rxmode <= 32) 24548863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 24648863ce5SAlexandre TORGUE else if (rxmode <= 64) 24748863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 24848863ce5SAlexandre TORGUE else if (rxmode <= 96) 24948863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 25048863ce5SAlexandre TORGUE else 25148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 25248863ce5SAlexandre TORGUE } 25348863ce5SAlexandre TORGUE 254356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 255356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 256356b7557SThierry Reding 257356b7557SThierry Reding /* enable flow control only if each channel gets 4 KiB or more FIFO */ 258356b7557SThierry Reding if (rxfifosz >= 4096) { 259356b7557SThierry Reding unsigned int rfd, rfa; 260356b7557SThierry Reding 261356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC; 262356b7557SThierry Reding 263356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames, 264356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes. 265356b7557SThierry Reding * 266356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame, 267356b7557SThierry Reding * i.e. 1500 bytes. 268356b7557SThierry Reding */ 269356b7557SThierry Reding switch (rxfifosz) { 270356b7557SThierry Reding case 4096: 271356b7557SThierry Reding /* This violates the above formula because of FIFO size 272356b7557SThierry Reding * limit therefore overflow may occur in spite of this. 273356b7557SThierry Reding */ 274356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */ 275356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */ 276356b7557SThierry Reding break; 277356b7557SThierry Reding 278356b7557SThierry Reding case 8192: 279356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 280356b7557SThierry Reding rfa = 0x0a; /* Full-6K */ 281356b7557SThierry Reding break; 282356b7557SThierry Reding 283356b7557SThierry Reding case 16384: 284356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 285356b7557SThierry Reding rfa = 0x12; /* Full-10K */ 286356b7557SThierry Reding break; 287356b7557SThierry Reding 288356b7557SThierry Reding default: 289356b7557SThierry Reding rfd = 0x06; /* Full-4K */ 290356b7557SThierry Reding rfa = 0x1e; /* Full-16K */ 291356b7557SThierry Reding break; 292356b7557SThierry Reding } 293356b7557SThierry Reding 294356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 295356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 296356b7557SThierry Reding 297356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 298356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 299356b7557SThierry Reding } 300356b7557SThierry Reding 30148863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 30248863ce5SAlexandre TORGUE 30348863ce5SAlexandre TORGUE /* Enable MTL RX overflow */ 30448863ce5SAlexandre TORGUE mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); 30548863ce5SAlexandre TORGUE writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, 30648863ce5SAlexandre TORGUE ioaddr + MTL_CHAN_INT_CTRL(channel)); 30748863ce5SAlexandre TORGUE } 30848863ce5SAlexandre TORGUE 30948863ce5SAlexandre TORGUE static void dwmac4_dma_operation_mode(void __iomem *ioaddr, int txmode, 31048863ce5SAlexandre TORGUE int rxmode, int rxfifosz) 31148863ce5SAlexandre TORGUE { 31248863ce5SAlexandre TORGUE /* Only Channel 0 is actually configured and used */ 313356b7557SThierry Reding dwmac4_dma_chan_op_mode(ioaddr, txmode, rxmode, 0, rxfifosz); 31448863ce5SAlexandre TORGUE } 31548863ce5SAlexandre TORGUE 31648863ce5SAlexandre TORGUE static void dwmac4_get_hw_feature(void __iomem *ioaddr, 31748863ce5SAlexandre TORGUE struct dma_features *dma_cap) 31848863ce5SAlexandre TORGUE { 31948863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 32048863ce5SAlexandre TORGUE 32148863ce5SAlexandre TORGUE /* MAC HW feature0 */ 32248863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 32348863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 32448863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 32548863ce5SAlexandre TORGUE dma_cap->hash_filter = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 32648863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 32748863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 32848863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 32948863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 33048863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 33148863ce5SAlexandre TORGUE /* MMC */ 33248863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 33348863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 33448863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 33548863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 33648863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 33748863ce5SAlexandre TORGUE /* TX and RX csum */ 33848863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 33948863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 34048863ce5SAlexandre TORGUE 34148863ce5SAlexandre TORGUE /* MAC HW feature1 */ 34248863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 34348863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 34448863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 34511fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 34611fbf811SThierry Reding * shifting and store the sizes in bytes. 34711fbf811SThierry Reding */ 34811fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 34911fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 35048863ce5SAlexandre TORGUE /* MAC HW feature2 */ 35148863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 35248863ce5SAlexandre TORGUE /* TX and RX number of channels */ 35348863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 35448863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 35548863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 35648863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 3579eb12474Sjpinto /* TX and RX number of queues */ 3589eb12474Sjpinto dma_cap->number_rx_queues = 3599eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 3609eb12474Sjpinto dma_cap->number_tx_queues = 3619eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 36248863ce5SAlexandre TORGUE 36348863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 36448863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 36548863ce5SAlexandre TORGUE } 36648863ce5SAlexandre TORGUE 36748863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 36848863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 36948863ce5SAlexandre TORGUE { 37048863ce5SAlexandre TORGUE u32 value; 37148863ce5SAlexandre TORGUE 37248863ce5SAlexandre TORGUE if (en) { 37348863ce5SAlexandre TORGUE /* enable TSO */ 37448863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 37548863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 37648863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 37748863ce5SAlexandre TORGUE } else { 37848863ce5SAlexandre TORGUE /* enable TSO */ 37948863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 38048863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 38148863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 38248863ce5SAlexandre TORGUE } 38348863ce5SAlexandre TORGUE } 38448863ce5SAlexandre TORGUE 38548863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 38648863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 38748863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 38848863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 38948863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 39048863ce5SAlexandre TORGUE .dma_mode = dwmac4_dma_operation_mode, 39148863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 39248863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 39348863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 39448863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 39548863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 39648863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 39748863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 39848863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 39948863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 40048863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 40148863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 40248863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 40348863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 40448863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 40548863ce5SAlexandre TORGUE }; 40648863ce5SAlexandre TORGUE 40748863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 40848863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 40948863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 41048863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 41148863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 41248863ce5SAlexandre TORGUE .dma_mode = dwmac4_dma_operation_mode, 41348863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 41448863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 41548863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 41648863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 41748863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 41848863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 41948863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 42048863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 42148863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 42248863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 42348863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 42448863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 42548863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 42648863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 42748863ce5SAlexandre TORGUE }; 428