175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 248863ce5SAlexandre TORGUE /* 348863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 448863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code. 548863ce5SAlexandre TORGUE * 648863ce5SAlexandre TORGUE * This contains the functions to handle the dma. 748863ce5SAlexandre TORGUE * 848863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd 948863ce5SAlexandre TORGUE * 1048863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com> 1148863ce5SAlexandre TORGUE */ 1248863ce5SAlexandre TORGUE 1348863ce5SAlexandre TORGUE #include <linux/io.h> 1448863ce5SAlexandre TORGUE #include "dwmac4.h" 1548863ce5SAlexandre TORGUE #include "dwmac4_dma.h" 1648863ce5SAlexandre TORGUE 1748863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) 1848863ce5SAlexandre TORGUE { 1948863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 2048863ce5SAlexandre TORGUE int i; 2148863ce5SAlexandre TORGUE 2248863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n", 2348863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); 2448863ce5SAlexandre TORGUE 2548863ce5SAlexandre TORGUE if (axi->axi_lpi_en) 2648863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI; 2748863ce5SAlexandre TORGUE if (axi->axi_xit_frm) 2848863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM; 2948863ce5SAlexandre TORGUE 306b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT; 3148863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << 3248863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT; 3348863ce5SAlexandre TORGUE 346b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT; 3548863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << 3648863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT; 3748863ce5SAlexandre TORGUE 3848863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst 3948863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are 4048863ce5SAlexandre TORGUE * set). 4148863ce5SAlexandre TORGUE */ 4248863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) { 4348863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) { 4448863ce5SAlexandre TORGUE case 256: 4548863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256; 4648863ce5SAlexandre TORGUE break; 4748863ce5SAlexandre TORGUE case 128: 4848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128; 4948863ce5SAlexandre TORGUE break; 5048863ce5SAlexandre TORGUE case 64: 5148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64; 5248863ce5SAlexandre TORGUE break; 5348863ce5SAlexandre TORGUE case 32: 5448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32; 5548863ce5SAlexandre TORGUE break; 5648863ce5SAlexandre TORGUE case 16: 5748863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16; 5848863ce5SAlexandre TORGUE break; 5948863ce5SAlexandre TORGUE case 8: 6048863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8; 6148863ce5SAlexandre TORGUE break; 6248863ce5SAlexandre TORGUE case 4: 6348863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4; 6448863ce5SAlexandre TORGUE break; 6548863ce5SAlexandre TORGUE } 6648863ce5SAlexandre TORGUE } 6748863ce5SAlexandre TORGUE 6848863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 6948863ce5SAlexandre TORGUE } 7048863ce5SAlexandre TORGUE 7172de4655SColin Ian King static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, 7289caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg, 7306a80a7dSJose Abreu dma_addr_t dma_rx_phy, u32 chan) 7448863ce5SAlexandre TORGUE { 7548863ce5SAlexandre TORGUE u32 value; 7647f2a9ceSJoao Pinto u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 7748863ce5SAlexandre TORGUE 7847f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 7947f2a9ceSJoao Pinto value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 8047f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 8147f2a9ceSJoao Pinto 82560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 83560c07cbSThierry Reding writel(upper_32_bits(dma_rx_phy), 84560c07cbSThierry Reding ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); 85560c07cbSThierry Reding 8606a80a7dSJose Abreu writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); 8747f2a9ceSJoao Pinto } 8847f2a9ceSJoao Pinto 8972de4655SColin Ian King static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, 9047f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, 9106a80a7dSJose Abreu dma_addr_t dma_tx_phy, u32 chan) 9247f2a9ceSJoao Pinto { 9347f2a9ceSJoao Pinto u32 value; 9447f2a9ceSJoao Pinto u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 9547f2a9ceSJoao Pinto 9647f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 9747f2a9ceSJoao Pinto value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT); 9867e1c406SJose Abreu 9967e1c406SJose Abreu /* Enable OSP to get best performance */ 10067e1c406SJose Abreu value |= DMA_CONTROL_OSP; 10167e1c406SJose Abreu 10247f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 10347f2a9ceSJoao Pinto 104560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame)) 105560c07cbSThierry Reding writel(upper_32_bits(dma_tx_phy), 106560c07cbSThierry Reding ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan)); 107560c07cbSThierry Reding 10806a80a7dSJose Abreu writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan)); 10947f2a9ceSJoao Pinto } 11047f2a9ceSJoao Pinto 11172de4655SColin Ian King static void dwmac4_dma_init_channel(void __iomem *ioaddr, 11247f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, u32 chan) 11347f2a9ceSJoao Pinto { 11447f2a9ceSJoao Pinto u32 value; 11547f2a9ceSJoao Pinto 11647f2a9ceSJoao Pinto /* common channel control register config */ 11747f2a9ceSJoao Pinto value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 1184022d039SNiklas Cassel if (dma_cfg->pblx8) 11948863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL; 12047f2a9ceSJoao Pinto writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 12148863ce5SAlexandre TORGUE 12248863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */ 12347f2a9ceSJoao Pinto writel(DMA_CHAN_INTR_DEFAULT_MASK, 12447f2a9ceSJoao Pinto ioaddr + DMA_CHAN_INTR_ENA(chan)); 12548863ce5SAlexandre TORGUE } 12648863ce5SAlexandre TORGUE 127879c348cSOng Boon Leong static void dwmac410_dma_init_channel(void __iomem *ioaddr, 128879c348cSOng Boon Leong struct stmmac_dma_cfg *dma_cfg, u32 chan) 129879c348cSOng Boon Leong { 130879c348cSOng Boon Leong u32 value; 131879c348cSOng Boon Leong 132879c348cSOng Boon Leong /* common channel control register config */ 133879c348cSOng Boon Leong value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 134879c348cSOng Boon Leong if (dma_cfg->pblx8) 135879c348cSOng Boon Leong value = value | DMA_BUS_MODE_PBL; 136879c348cSOng Boon Leong 137879c348cSOng Boon Leong writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 138879c348cSOng Boon Leong 139879c348cSOng Boon Leong /* Mask interrupts by writing to CSR7 */ 140879c348cSOng Boon Leong writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10, 141879c348cSOng Boon Leong ioaddr + DMA_CHAN_INTR_ENA(chan)); 142879c348cSOng Boon Leong } 143879c348cSOng Boon Leong 14450ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr, 14524aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds) 14648863ce5SAlexandre TORGUE { 14748863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 14848863ce5SAlexandre TORGUE 14948863ce5SAlexandre TORGUE /* Set the Fixed burst mode */ 15050ca903aSNiklas Cassel if (dma_cfg->fixed_burst) 15148863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB; 15248863ce5SAlexandre TORGUE 15348863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */ 15450ca903aSNiklas Cassel if (dma_cfg->mixed_burst) 15548863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB; 15648863ce5SAlexandre TORGUE 15750ca903aSNiklas Cassel if (dma_cfg->aal) 15848863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL; 15948863ce5SAlexandre TORGUE 160560c07cbSThierry Reding if (dma_cfg->eame) 161560c07cbSThierry Reding value |= DMA_SYS_BUS_EAME; 162560c07cbSThierry Reding 16348863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE); 1646ccf12aeSWong, Vee Khee 1656ccf12aeSWong, Vee Khee value = readl(ioaddr + DMA_BUS_MODE); 16696874c61SMohammad Athari Bin Ismail 16796874c61SMohammad Athari Bin Ismail if (dma_cfg->multi_msi_en) { 1686ccf12aeSWong, Vee Khee value &= ~DMA_BUS_MODE_INTM_MASK; 1696ccf12aeSWong, Vee Khee value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT); 1706ccf12aeSWong, Vee Khee } 17196874c61SMohammad Athari Bin Ismail 17296874c61SMohammad Athari Bin Ismail if (dma_cfg->dche) 17396874c61SMohammad Athari Bin Ismail value |= DMA_BUS_MODE_DCHE; 17496874c61SMohammad Athari Bin Ismail 17596874c61SMohammad Athari Bin Ismail writel(value, ioaddr + DMA_BUS_MODE); 17696874c61SMohammad Athari Bin Ismail 17748863ce5SAlexandre TORGUE } 17848863ce5SAlexandre TORGUE 179fbf68229SLABBE Corentin static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, 180fbf68229SLABBE Corentin u32 *reg_space) 18148863ce5SAlexandre TORGUE { 182fbf68229SLABBE Corentin reg_space[DMA_CHAN_CONTROL(channel) / 4] = 183fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CONTROL(channel)); 184fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = 185fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); 186fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] = 187fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_CONTROL(channel)); 188fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] = 189fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel)); 190fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] = 191fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); 192fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] = 193fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel)); 194fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] = 195fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel)); 196fbf68229SLABBE Corentin reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] = 197fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel)); 198fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] = 199fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel)); 200fbf68229SLABBE Corentin reg_space[DMA_CHAN_INTR_ENA(channel) / 4] = 201fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_INTR_ENA(channel)); 202fbf68229SLABBE Corentin reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] = 203fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel)); 204fbf68229SLABBE Corentin reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] = 205fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel)); 206fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] = 207fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel)); 208fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] = 209fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel)); 210fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] = 211fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel)); 212fbf68229SLABBE Corentin reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] = 213fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel)); 214fbf68229SLABBE Corentin reg_space[DMA_CHAN_STATUS(channel) / 4] = 215fbf68229SLABBE Corentin readl(ioaddr + DMA_CHAN_STATUS(channel)); 21648863ce5SAlexandre TORGUE } 21748863ce5SAlexandre TORGUE 218fbf68229SLABBE Corentin static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) 21948863ce5SAlexandre TORGUE { 22048863ce5SAlexandre TORGUE int i; 22148863ce5SAlexandre TORGUE 22248863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) 223fbf68229SLABBE Corentin _dwmac4_dump_dma_regs(ioaddr, i, reg_space); 22448863ce5SAlexandre TORGUE } 22548863ce5SAlexandre TORGUE 226db2f2842SOng Boon Leong static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 queue) 22748863ce5SAlexandre TORGUE { 228db2f2842SOng Boon Leong writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue)); 22948863ce5SAlexandre TORGUE } 23048863ce5SAlexandre TORGUE 2316deee222SJoao Pinto static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, 232a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 23348863ce5SAlexandre TORGUE { 2346deee222SJoao Pinto unsigned int rqs = fifosz / 256 - 1; 2358a7cb245SYannick Vignon u32 mtl_rx_op; 23648863ce5SAlexandre TORGUE 23748863ce5SAlexandre TORGUE mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 23848863ce5SAlexandre TORGUE 2396deee222SJoao Pinto if (mode == SF_DMA_MODE) { 24048863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n"); 24148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF; 24248863ce5SAlexandre TORGUE } else { 2436deee222SJoao Pinto pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode); 24448863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF; 24548863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK; 2466deee222SJoao Pinto if (mode <= 32) 24748863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32; 2486deee222SJoao Pinto else if (mode <= 64) 24948863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64; 2506deee222SJoao Pinto else if (mode <= 96) 25148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96; 25248863ce5SAlexandre TORGUE else 25348863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128; 25448863ce5SAlexandre TORGUE } 25548863ce5SAlexandre TORGUE 256356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK; 257356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT; 258356b7557SThierry Reding 259a0daae13SJose Abreu /* Enable flow control only if each channel gets 4 KiB or more FIFO and 260a0daae13SJose Abreu * only if channel is not an AVB channel. 261a0daae13SJose Abreu */ 262a0daae13SJose Abreu if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) { 263356b7557SThierry Reding unsigned int rfd, rfa; 264356b7557SThierry Reding 265356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC; 266356b7557SThierry Reding 267356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames, 268356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes. 269356b7557SThierry Reding * 270356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame, 271356b7557SThierry Reding * i.e. 1500 bytes. 272356b7557SThierry Reding */ 2736deee222SJoao Pinto switch (fifosz) { 274356b7557SThierry Reding case 4096: 275356b7557SThierry Reding /* This violates the above formula because of FIFO size 276356b7557SThierry Reding * limit therefore overflow may occur in spite of this. 277356b7557SThierry Reding */ 278356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */ 279356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */ 280356b7557SThierry Reding break; 281356b7557SThierry Reding 282356b7557SThierry Reding default: 283854248e5SJose Abreu rfd = 0x07; /* Full-4.5K */ 284854248e5SJose Abreu rfa = 0x04; /* Full-3K */ 285356b7557SThierry Reding break; 286356b7557SThierry Reding } 287356b7557SThierry Reding 288356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK; 289356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT; 290356b7557SThierry Reding 291356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK; 292356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT; 293356b7557SThierry Reding } 294356b7557SThierry Reding 29548863ce5SAlexandre TORGUE writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); 29648863ce5SAlexandre TORGUE } 29748863ce5SAlexandre TORGUE 2986deee222SJoao Pinto static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, 299a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode) 30048863ce5SAlexandre TORGUE { 3016deee222SJoao Pinto u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 30252a76235SJose Abreu unsigned int tqs = fifosz / 256 - 1; 3036deee222SJoao Pinto 3046deee222SJoao Pinto if (mode == SF_DMA_MODE) { 3056deee222SJoao Pinto pr_debug("GMAC: enable TX store and forward mode\n"); 3066deee222SJoao Pinto /* Transmit COE type 2 cannot be done in cut-through mode. */ 3076deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TSF; 3086deee222SJoao Pinto } else { 3096deee222SJoao Pinto pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode); 3106deee222SJoao Pinto mtl_tx_op &= ~MTL_OP_MODE_TSF; 3116deee222SJoao Pinto mtl_tx_op &= MTL_OP_MODE_TTC_MASK; 3126deee222SJoao Pinto /* Set the transmit threshold */ 3136deee222SJoao Pinto if (mode <= 32) 3146deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_32; 3156deee222SJoao Pinto else if (mode <= 64) 3166deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_64; 3176deee222SJoao Pinto else if (mode <= 96) 3186deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_96; 3196deee222SJoao Pinto else if (mode <= 128) 3206deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_128; 3216deee222SJoao Pinto else if (mode <= 192) 3226deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_192; 3236deee222SJoao Pinto else if (mode <= 256) 3246deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_256; 3256deee222SJoao Pinto else if (mode <= 384) 3266deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_384; 3276deee222SJoao Pinto else 3286deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_512; 3296deee222SJoao Pinto } 3306deee222SJoao Pinto /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO 3316deee222SJoao Pinto * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE. 3326deee222SJoao Pinto * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W 3336deee222SJoao Pinto * with reset values: TXQEN off, TQS 256 bytes. 3346deee222SJoao Pinto * 33552a76235SJose Abreu * TXQEN must be written for multi-channel operation and TQS must 33652a76235SJose Abreu * reflect the available fifo size per queue (total fifo size / number 33752a76235SJose Abreu * of enabled queues). 3386deee222SJoao Pinto */ 339a0daae13SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 340a0daae13SJose Abreu if (qmode != MTL_QUEUE_AVB) 34152a76235SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 342a0daae13SJose Abreu else 343a0daae13SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 34452a76235SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK; 34552a76235SJose Abreu mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT; 34652a76235SJose Abreu 3476deee222SJoao Pinto writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 34848863ce5SAlexandre TORGUE } 34948863ce5SAlexandre TORGUE 350*075da584SHerve Codina static int dwmac4_get_hw_feature(void __iomem *ioaddr, 35148863ce5SAlexandre TORGUE struct dma_features *dma_cap) 35248863ce5SAlexandre TORGUE { 35348863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); 35448863ce5SAlexandre TORGUE 35548863ce5SAlexandre TORGUE /* MAC HW feature0 */ 35648863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); 35748863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; 35848863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; 359c1be0022SJose Abreu dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; 36048863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; 36148863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; 36248863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; 36348863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; 36448863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; 36548863ce5SAlexandre TORGUE /* MMC */ 36648863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8; 36748863ce5SAlexandre TORGUE /* IEEE 1588-2008 */ 36848863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12; 36948863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */ 37048863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13; 37148863ce5SAlexandre TORGUE /* TX and RX csum */ 37248863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14; 37348863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16; 3741d982e93SJose Abreu dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27; 375c9b10043SJose Abreu dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9; 37648863ce5SAlexandre TORGUE 37748863ce5SAlexandre TORGUE /* MAC HW feature1 */ 37848863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1); 379dc07f5fdSJose Abreu dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27; 380b8ef7020SBiao Huang dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24; 38148863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20; 38248863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18; 3838c6fc097SJose Abreu dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17; 384560c07cbSThierry Reding 385560c07cbSThierry Reding dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14; 386560c07cbSThierry Reding switch (dma_cap->addr64) { 387560c07cbSThierry Reding case 0: 388560c07cbSThierry Reding dma_cap->addr64 = 32; 389560c07cbSThierry Reding break; 390560c07cbSThierry Reding case 1: 391560c07cbSThierry Reding dma_cap->addr64 = 40; 392560c07cbSThierry Reding break; 393560c07cbSThierry Reding case 2: 394560c07cbSThierry Reding dma_cap->addr64 = 48; 395560c07cbSThierry Reding break; 396560c07cbSThierry Reding default: 397560c07cbSThierry Reding dma_cap->addr64 = 32; 398560c07cbSThierry Reding break; 399560c07cbSThierry Reding } 400560c07cbSThierry Reding 40111fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by 40211fbf811SThierry Reding * shifting and store the sizes in bytes. 40311fbf811SThierry Reding */ 40411fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6); 40511fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0); 40648863ce5SAlexandre TORGUE /* MAC HW feature2 */ 40748863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2); 40848863ce5SAlexandre TORGUE /* TX and RX number of channels */ 40948863ce5SAlexandre TORGUE dma_cap->number_rx_channel = 41048863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1; 41148863ce5SAlexandre TORGUE dma_cap->number_tx_channel = 41248863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1; 4139eb12474Sjpinto /* TX and RX number of queues */ 4149eb12474Sjpinto dma_cap->number_rx_queues = 4159eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1; 4169eb12474Sjpinto dma_cap->number_tx_queues = 4179eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1; 4189a8a02c9SJose Abreu /* PPS output */ 4199a8a02c9SJose Abreu dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24; 42048863ce5SAlexandre TORGUE 42148863ce5SAlexandre TORGUE /* IEEE 1588-2002 */ 42248863ce5SAlexandre TORGUE dma_cap->time_stamp = 0; 423341f67e4STan Tee Min /* Number of Auxiliary Snapshot Inputs */ 424341f67e4STan Tee Min dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28; 4258bf993a5SJose Abreu 4268bf993a5SJose Abreu /* MAC HW feature3 */ 4278bf993a5SJose Abreu hw_cap = readl(ioaddr + GMAC_HW_FEATURE3); 4288bf993a5SJose Abreu 4298bf993a5SJose Abreu /* 5.10 Features */ 4308bf993a5SJose Abreu dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28; 43158ae9281SJose Abreu dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27; 4327c728274SJose Abreu dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26; 433504723afSJose Abreu dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20; 434504723afSJose Abreu dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17; 435504723afSJose Abreu dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16; 4364dbbe8ddSJose Abreu dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13; 4374dbbe8ddSJose Abreu dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11; 4384dbbe8ddSJose Abreu dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10; 439e94e3f3bSJose Abreu dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5; 440*075da584SHerve Codina 441*075da584SHerve Codina return 0; 44248863ce5SAlexandre TORGUE } 44348863ce5SAlexandre TORGUE 44448863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */ 44548863ce5SAlexandre TORGUE static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) 44648863ce5SAlexandre TORGUE { 44748863ce5SAlexandre TORGUE u32 value; 44848863ce5SAlexandre TORGUE 44948863ce5SAlexandre TORGUE if (en) { 45048863ce5SAlexandre TORGUE /* enable TSO */ 45148863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 45248863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE, 45348863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 45448863ce5SAlexandre TORGUE } else { 45548863ce5SAlexandre TORGUE /* enable TSO */ 45648863ce5SAlexandre TORGUE value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 45748863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE, 45848863ce5SAlexandre TORGUE ioaddr + DMA_CHAN_TX_CONTROL(chan)); 45948863ce5SAlexandre TORGUE } 46048863ce5SAlexandre TORGUE } 46148863ce5SAlexandre TORGUE 4621f705bc6SJose Abreu static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) 4631f705bc6SJose Abreu { 4641f705bc6SJose Abreu u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4651f705bc6SJose Abreu 4661f705bc6SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK; 4671f705bc6SJose Abreu if (qmode != MTL_QUEUE_AVB) 4681f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN; 4691f705bc6SJose Abreu else 4701f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV; 4711f705bc6SJose Abreu 4721f705bc6SJose Abreu writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel)); 4731f705bc6SJose Abreu } 4741f705bc6SJose Abreu 4754205c88eSJose Abreu static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) 4764205c88eSJose Abreu { 4774205c88eSJose Abreu u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4784205c88eSJose Abreu 4794205c88eSJose Abreu value &= ~DMA_RBSZ_MASK; 4804205c88eSJose Abreu value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK; 4814205c88eSJose Abreu 4824205c88eSJose Abreu writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); 4834205c88eSJose Abreu } 4844205c88eSJose Abreu 4858c6fc097SJose Abreu static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan) 4868c6fc097SJose Abreu { 4878c6fc097SJose Abreu u32 value = readl(ioaddr + GMAC_EXT_CONFIG); 4888c6fc097SJose Abreu 4898c6fc097SJose Abreu value &= ~GMAC_CONFIG_HDSMS; 4908c6fc097SJose Abreu value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ 4918c6fc097SJose Abreu writel(value, ioaddr + GMAC_EXT_CONFIG); 4928c6fc097SJose Abreu 4938c6fc097SJose Abreu value = readl(ioaddr + DMA_CHAN_CONTROL(chan)); 4948c6fc097SJose Abreu if (en) 4958c6fc097SJose Abreu value |= DMA_CONTROL_SPH; 4968c6fc097SJose Abreu else 4978c6fc097SJose Abreu value &= ~DMA_CONTROL_SPH; 4988c6fc097SJose Abreu writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); 4998c6fc097SJose Abreu } 5008c6fc097SJose Abreu 50158ae9281SJose Abreu static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) 50258ae9281SJose Abreu { 50358ae9281SJose Abreu u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); 50458ae9281SJose Abreu 50558ae9281SJose Abreu if (en) 50658ae9281SJose Abreu value |= DMA_CONTROL_EDSE; 50758ae9281SJose Abreu else 50858ae9281SJose Abreu value &= ~DMA_CONTROL_EDSE; 50958ae9281SJose Abreu 51058ae9281SJose Abreu writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); 51158ae9281SJose Abreu 51258ae9281SJose Abreu value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE; 51358ae9281SJose Abreu if (en && !value) 51458ae9281SJose Abreu return -EIO; 51558ae9281SJose Abreu 51658ae9281SJose Abreu writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL); 51758ae9281SJose Abreu return 0; 51858ae9281SJose Abreu } 51958ae9281SJose Abreu 52048863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = { 52148863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 52248863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 52347f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel, 52447f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 52547f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 52648863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 52748863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 5286deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 5296deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 53048863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq, 53148863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 53248863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 53348863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 53448863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 53548863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 53648863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 53748863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 53848863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 53948863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 54048863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 54148863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 54248863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 54348863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 5441f705bc6SJose Abreu .qmode = dwmac4_qmode, 5454205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 5468c6fc097SJose Abreu .enable_sph = dwmac4_enable_sph, 54748863ce5SAlexandre TORGUE }; 54848863ce5SAlexandre TORGUE 54948863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = { 55048863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset, 55148863ce5SAlexandre TORGUE .init = dwmac4_dma_init, 552879c348cSOng Boon Leong .init_chan = dwmac410_dma_init_channel, 55347f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan, 55447f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan, 55548863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi, 55648863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs, 5576deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode, 5586deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode, 55948863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq, 56048863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq, 56148863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx, 56248863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx, 56348863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx, 56448863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx, 56548863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt, 56648863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature, 56748863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog, 56848863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len, 56948863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len, 57048863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr, 57148863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr, 57248863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso, 5731f705bc6SJose Abreu .qmode = dwmac4_qmode, 5744205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize, 5758c6fc097SJose Abreu .enable_sph = dwmac4_enable_sph, 57658ae9281SJose Abreu .enable_tbs = dwmac4_enable_tbs, 57748863ce5SAlexandre TORGUE }; 578