175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
248863ce5SAlexandre TORGUE /*
348863ce5SAlexandre TORGUE * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
448863ce5SAlexandre TORGUE * DWC Ether MAC version 4.xx has been used for developing this code.
548863ce5SAlexandre TORGUE *
648863ce5SAlexandre TORGUE * This contains the functions to handle the dma.
748863ce5SAlexandre TORGUE *
848863ce5SAlexandre TORGUE * Copyright (C) 2015 STMicroelectronics Ltd
948863ce5SAlexandre TORGUE *
1048863ce5SAlexandre TORGUE * Author: Alexandre Torgue <alexandre.torgue@st.com>
1148863ce5SAlexandre TORGUE */
1248863ce5SAlexandre TORGUE
1348863ce5SAlexandre TORGUE #include <linux/io.h>
1448863ce5SAlexandre TORGUE #include "dwmac4.h"
1548863ce5SAlexandre TORGUE #include "dwmac4_dma.h"
16*33719b57SAndrew Halaney #include "stmmac.h"
1748863ce5SAlexandre TORGUE
dwmac4_dma_axi(void __iomem * ioaddr,struct stmmac_axi * axi)1848863ce5SAlexandre TORGUE static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
1948863ce5SAlexandre TORGUE {
2048863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
2148863ce5SAlexandre TORGUE int i;
2248863ce5SAlexandre TORGUE
2348863ce5SAlexandre TORGUE pr_info("dwmac4: Master AXI performs %s burst length\n",
2448863ce5SAlexandre TORGUE (value & DMA_SYS_BUS_FB) ? "fixed" : "any");
2548863ce5SAlexandre TORGUE
2648863ce5SAlexandre TORGUE if (axi->axi_lpi_en)
2748863ce5SAlexandre TORGUE value |= DMA_AXI_EN_LPI;
2848863ce5SAlexandre TORGUE if (axi->axi_xit_frm)
2948863ce5SAlexandre TORGUE value |= DMA_AXI_LPI_XIT_FRM;
3048863ce5SAlexandre TORGUE
316b3374cbSNiklas Cassel value &= ~DMA_AXI_WR_OSR_LMT;
3248863ce5SAlexandre TORGUE value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
3348863ce5SAlexandre TORGUE DMA_AXI_WR_OSR_LMT_SHIFT;
3448863ce5SAlexandre TORGUE
356b3374cbSNiklas Cassel value &= ~DMA_AXI_RD_OSR_LMT;
3648863ce5SAlexandre TORGUE value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
3748863ce5SAlexandre TORGUE DMA_AXI_RD_OSR_LMT_SHIFT;
3848863ce5SAlexandre TORGUE
3948863ce5SAlexandre TORGUE /* Depending on the UNDEF bit the Master AXI will perform any burst
4048863ce5SAlexandre TORGUE * length according to the BLEN programmed (by default all BLEN are
4148863ce5SAlexandre TORGUE * set).
4248863ce5SAlexandre TORGUE */
4348863ce5SAlexandre TORGUE for (i = 0; i < AXI_BLEN; i++) {
4448863ce5SAlexandre TORGUE switch (axi->axi_blen[i]) {
4548863ce5SAlexandre TORGUE case 256:
4648863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN256;
4748863ce5SAlexandre TORGUE break;
4848863ce5SAlexandre TORGUE case 128:
4948863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN128;
5048863ce5SAlexandre TORGUE break;
5148863ce5SAlexandre TORGUE case 64:
5248863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN64;
5348863ce5SAlexandre TORGUE break;
5448863ce5SAlexandre TORGUE case 32:
5548863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN32;
5648863ce5SAlexandre TORGUE break;
5748863ce5SAlexandre TORGUE case 16:
5848863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN16;
5948863ce5SAlexandre TORGUE break;
6048863ce5SAlexandre TORGUE case 8:
6148863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN8;
6248863ce5SAlexandre TORGUE break;
6348863ce5SAlexandre TORGUE case 4:
6448863ce5SAlexandre TORGUE value |= DMA_AXI_BLEN4;
6548863ce5SAlexandre TORGUE break;
6648863ce5SAlexandre TORGUE }
6748863ce5SAlexandre TORGUE }
6848863ce5SAlexandre TORGUE
6948863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE);
7048863ce5SAlexandre TORGUE }
7148863ce5SAlexandre TORGUE
dwmac4_dma_init_rx_chan(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_rx_phy,u32 chan)721d84b487SAndrew Halaney static void dwmac4_dma_init_rx_chan(struct stmmac_priv *priv,
731d84b487SAndrew Halaney void __iomem *ioaddr,
7489caaa2dSNiklas Cassel struct stmmac_dma_cfg *dma_cfg,
7506a80a7dSJose Abreu dma_addr_t dma_rx_phy, u32 chan)
7648863ce5SAlexandre TORGUE {
77*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
7848863ce5SAlexandre TORGUE u32 value;
7947f2a9ceSJoao Pinto u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
8048863ce5SAlexandre TORGUE
81*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
8247f2a9ceSJoao Pinto value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
83*33719b57SAndrew Halaney writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
8447f2a9ceSJoao Pinto
85560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
86560c07cbSThierry Reding writel(upper_32_bits(dma_rx_phy),
87*33719b57SAndrew Halaney ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, chan));
88560c07cbSThierry Reding
89*33719b57SAndrew Halaney writel(lower_32_bits(dma_rx_phy),
90*33719b57SAndrew Halaney ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, chan));
9147f2a9ceSJoao Pinto }
9247f2a9ceSJoao Pinto
dwmac4_dma_init_tx_chan(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,dma_addr_t dma_tx_phy,u32 chan)931d84b487SAndrew Halaney static void dwmac4_dma_init_tx_chan(struct stmmac_priv *priv,
941d84b487SAndrew Halaney void __iomem *ioaddr,
9547f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg,
9606a80a7dSJose Abreu dma_addr_t dma_tx_phy, u32 chan)
9747f2a9ceSJoao Pinto {
98*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
9947f2a9ceSJoao Pinto u32 value;
10047f2a9ceSJoao Pinto u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
10147f2a9ceSJoao Pinto
102*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
10347f2a9ceSJoao Pinto value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
10467e1c406SJose Abreu
10567e1c406SJose Abreu /* Enable OSP to get best performance */
10667e1c406SJose Abreu value |= DMA_CONTROL_OSP;
10767e1c406SJose Abreu
108*33719b57SAndrew Halaney writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
10947f2a9ceSJoao Pinto
110560c07cbSThierry Reding if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
111560c07cbSThierry Reding writel(upper_32_bits(dma_tx_phy),
112*33719b57SAndrew Halaney ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, chan));
113560c07cbSThierry Reding
114*33719b57SAndrew Halaney writel(lower_32_bits(dma_tx_phy),
115*33719b57SAndrew Halaney ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, chan));
11647f2a9ceSJoao Pinto }
11747f2a9ceSJoao Pinto
dwmac4_dma_init_channel(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)1181d84b487SAndrew Halaney static void dwmac4_dma_init_channel(struct stmmac_priv *priv,
1191d84b487SAndrew Halaney void __iomem *ioaddr,
12047f2a9ceSJoao Pinto struct stmmac_dma_cfg *dma_cfg, u32 chan)
12147f2a9ceSJoao Pinto {
122*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
12347f2a9ceSJoao Pinto u32 value;
12447f2a9ceSJoao Pinto
12547f2a9ceSJoao Pinto /* common channel control register config */
126*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
1274022d039SNiklas Cassel if (dma_cfg->pblx8)
12848863ce5SAlexandre TORGUE value = value | DMA_BUS_MODE_PBL;
129*33719b57SAndrew Halaney writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
13048863ce5SAlexandre TORGUE
13148863ce5SAlexandre TORGUE /* Mask interrupts by writing to CSR7 */
13247f2a9ceSJoao Pinto writel(DMA_CHAN_INTR_DEFAULT_MASK,
133*33719b57SAndrew Halaney ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
13448863ce5SAlexandre TORGUE }
13548863ce5SAlexandre TORGUE
dwmac410_dma_init_channel(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)1361d84b487SAndrew Halaney static void dwmac410_dma_init_channel(struct stmmac_priv *priv,
1371d84b487SAndrew Halaney void __iomem *ioaddr,
138879c348cSOng Boon Leong struct stmmac_dma_cfg *dma_cfg, u32 chan)
139879c348cSOng Boon Leong {
140*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
141879c348cSOng Boon Leong u32 value;
142879c348cSOng Boon Leong
143879c348cSOng Boon Leong /* common channel control register config */
144*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
145879c348cSOng Boon Leong if (dma_cfg->pblx8)
146879c348cSOng Boon Leong value = value | DMA_BUS_MODE_PBL;
147879c348cSOng Boon Leong
148*33719b57SAndrew Halaney writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
149879c348cSOng Boon Leong
150879c348cSOng Boon Leong /* Mask interrupts by writing to CSR7 */
151879c348cSOng Boon Leong writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
152*33719b57SAndrew Halaney ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
153879c348cSOng Boon Leong }
154879c348cSOng Boon Leong
dwmac4_dma_init(void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,int atds)15550ca903aSNiklas Cassel static void dwmac4_dma_init(void __iomem *ioaddr,
15624aaed0cSJose Abreu struct stmmac_dma_cfg *dma_cfg, int atds)
15748863ce5SAlexandre TORGUE {
15848863ce5SAlexandre TORGUE u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
15948863ce5SAlexandre TORGUE
16048863ce5SAlexandre TORGUE /* Set the Fixed burst mode */
16150ca903aSNiklas Cassel if (dma_cfg->fixed_burst)
16248863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_FB;
16348863ce5SAlexandre TORGUE
16448863ce5SAlexandre TORGUE /* Mixed Burst has no effect when fb is set */
16550ca903aSNiklas Cassel if (dma_cfg->mixed_burst)
16648863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_MB;
16748863ce5SAlexandre TORGUE
16850ca903aSNiklas Cassel if (dma_cfg->aal)
16948863ce5SAlexandre TORGUE value |= DMA_SYS_BUS_AAL;
17048863ce5SAlexandre TORGUE
171560c07cbSThierry Reding if (dma_cfg->eame)
172560c07cbSThierry Reding value |= DMA_SYS_BUS_EAME;
173560c07cbSThierry Reding
17448863ce5SAlexandre TORGUE writel(value, ioaddr + DMA_SYS_BUS_MODE);
1756ccf12aeSWong, Vee Khee
1766ccf12aeSWong, Vee Khee value = readl(ioaddr + DMA_BUS_MODE);
17796874c61SMohammad Athari Bin Ismail
17896874c61SMohammad Athari Bin Ismail if (dma_cfg->multi_msi_en) {
1796ccf12aeSWong, Vee Khee value &= ~DMA_BUS_MODE_INTM_MASK;
1806ccf12aeSWong, Vee Khee value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
1816ccf12aeSWong, Vee Khee }
18296874c61SMohammad Athari Bin Ismail
18396874c61SMohammad Athari Bin Ismail if (dma_cfg->dche)
18496874c61SMohammad Athari Bin Ismail value |= DMA_BUS_MODE_DCHE;
18596874c61SMohammad Athari Bin Ismail
18696874c61SMohammad Athari Bin Ismail writel(value, ioaddr + DMA_BUS_MODE);
18796874c61SMohammad Athari Bin Ismail
18848863ce5SAlexandre TORGUE }
18948863ce5SAlexandre TORGUE
_dwmac4_dump_dma_regs(struct stmmac_priv * priv,void __iomem * ioaddr,u32 channel,u32 * reg_space)1901d84b487SAndrew Halaney static void _dwmac4_dump_dma_regs(struct stmmac_priv *priv,
1911d84b487SAndrew Halaney void __iomem *ioaddr, u32 channel,
192fbf68229SLABBE Corentin u32 *reg_space)
19348863ce5SAlexandre TORGUE {
194*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
195*33719b57SAndrew Halaney const struct dwmac4_addrs *default_addrs = NULL;
196*33719b57SAndrew Halaney
197*33719b57SAndrew Halaney /* Purposely save the registers in the "normal" layout, regardless of
198*33719b57SAndrew Halaney * platform modifications, to keep reg_space size constant
199*33719b57SAndrew Halaney */
200*33719b57SAndrew Halaney reg_space[DMA_CHAN_CONTROL(default_addrs, channel) / 4] =
201*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel));
202*33719b57SAndrew Halaney reg_space[DMA_CHAN_TX_CONTROL(default_addrs, channel) / 4] =
203*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel));
204*33719b57SAndrew Halaney reg_space[DMA_CHAN_RX_CONTROL(default_addrs, channel) / 4] =
205*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel));
206*33719b57SAndrew Halaney reg_space[DMA_CHAN_TX_BASE_ADDR(default_addrs, channel) / 4] =
207*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel));
208*33719b57SAndrew Halaney reg_space[DMA_CHAN_RX_BASE_ADDR(default_addrs, channel) / 4] =
209*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel));
210*33719b57SAndrew Halaney reg_space[DMA_CHAN_TX_END_ADDR(default_addrs, channel) / 4] =
211*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, channel));
212*33719b57SAndrew Halaney reg_space[DMA_CHAN_RX_END_ADDR(default_addrs, channel) / 4] =
213*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, channel));
214*33719b57SAndrew Halaney reg_space[DMA_CHAN_TX_RING_LEN(default_addrs, channel) / 4] =
215*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_TX_RING_LEN(dwmac4_addrs, channel));
216*33719b57SAndrew Halaney reg_space[DMA_CHAN_RX_RING_LEN(default_addrs, channel) / 4] =
217*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_RX_RING_LEN(dwmac4_addrs, channel));
218*33719b57SAndrew Halaney reg_space[DMA_CHAN_INTR_ENA(default_addrs, channel) / 4] =
219*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, channel));
220*33719b57SAndrew Halaney reg_space[DMA_CHAN_RX_WATCHDOG(default_addrs, channel) / 4] =
221*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, channel));
222*33719b57SAndrew Halaney reg_space[DMA_CHAN_SLOT_CTRL_STATUS(default_addrs, channel) / 4] =
223*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(dwmac4_addrs, channel));
224*33719b57SAndrew Halaney reg_space[DMA_CHAN_CUR_TX_DESC(default_addrs, channel) / 4] =
225*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel));
226*33719b57SAndrew Halaney reg_space[DMA_CHAN_CUR_RX_DESC(default_addrs, channel) / 4] =
227*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel));
228*33719b57SAndrew Halaney reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(default_addrs, channel) / 4] =
229*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel));
230*33719b57SAndrew Halaney reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(default_addrs, channel) / 4] =
231*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel));
232*33719b57SAndrew Halaney reg_space[DMA_CHAN_STATUS(default_addrs, channel) / 4] =
233*33719b57SAndrew Halaney readl(ioaddr + DMA_CHAN_STATUS(dwmac4_addrs, channel));
23448863ce5SAlexandre TORGUE }
23548863ce5SAlexandre TORGUE
dwmac4_dump_dma_regs(struct stmmac_priv * priv,void __iomem * ioaddr,u32 * reg_space)2361d84b487SAndrew Halaney static void dwmac4_dump_dma_regs(struct stmmac_priv *priv, void __iomem *ioaddr,
2371d84b487SAndrew Halaney u32 *reg_space)
23848863ce5SAlexandre TORGUE {
23948863ce5SAlexandre TORGUE int i;
24048863ce5SAlexandre TORGUE
24148863ce5SAlexandre TORGUE for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
2421d84b487SAndrew Halaney _dwmac4_dump_dma_regs(priv, ioaddr, i, reg_space);
24348863ce5SAlexandre TORGUE }
24448863ce5SAlexandre TORGUE
dwmac4_rx_watchdog(struct stmmac_priv * priv,void __iomem * ioaddr,u32 riwt,u32 queue)2451d84b487SAndrew Halaney static void dwmac4_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr,
2461d84b487SAndrew Halaney u32 riwt, u32 queue)
24748863ce5SAlexandre TORGUE {
248*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
249*33719b57SAndrew Halaney
250*33719b57SAndrew Halaney writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(dwmac4_addrs, queue));
25148863ce5SAlexandre TORGUE }
25248863ce5SAlexandre TORGUE
dwmac4_dma_rx_chan_op_mode(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)2531d84b487SAndrew Halaney static void dwmac4_dma_rx_chan_op_mode(struct stmmac_priv *priv,
2541d84b487SAndrew Halaney void __iomem *ioaddr, int mode,
255a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode)
25648863ce5SAlexandre TORGUE {
257*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
2586deee222SJoao Pinto unsigned int rqs = fifosz / 256 - 1;
2598a7cb245SYannick Vignon u32 mtl_rx_op;
26048863ce5SAlexandre TORGUE
261*33719b57SAndrew Halaney mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
26248863ce5SAlexandre TORGUE
2636deee222SJoao Pinto if (mode == SF_DMA_MODE) {
26448863ce5SAlexandre TORGUE pr_debug("GMAC: enable RX store and forward mode\n");
26548863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RSF;
26648863ce5SAlexandre TORGUE } else {
2676deee222SJoao Pinto pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
26848863ce5SAlexandre TORGUE mtl_rx_op &= ~MTL_OP_MODE_RSF;
26948863ce5SAlexandre TORGUE mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
2706deee222SJoao Pinto if (mode <= 32)
27148863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_32;
2726deee222SJoao Pinto else if (mode <= 64)
27348863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_64;
2746deee222SJoao Pinto else if (mode <= 96)
27548863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_96;
27648863ce5SAlexandre TORGUE else
27748863ce5SAlexandre TORGUE mtl_rx_op |= MTL_OP_MODE_RTC_128;
27848863ce5SAlexandre TORGUE }
27948863ce5SAlexandre TORGUE
280356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
281356b7557SThierry Reding mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
282356b7557SThierry Reding
283a0daae13SJose Abreu /* Enable flow control only if each channel gets 4 KiB or more FIFO and
284a0daae13SJose Abreu * only if channel is not an AVB channel.
285a0daae13SJose Abreu */
286a0daae13SJose Abreu if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
287356b7557SThierry Reding unsigned int rfd, rfa;
288356b7557SThierry Reding
289356b7557SThierry Reding mtl_rx_op |= MTL_OP_MODE_EHFC;
290356b7557SThierry Reding
291356b7557SThierry Reding /* Set Threshold for Activating Flow Control to min 2 frames,
292356b7557SThierry Reding * i.e. 1500 * 2 = 3000 bytes.
293356b7557SThierry Reding *
294356b7557SThierry Reding * Set Threshold for Deactivating Flow Control to min 1 frame,
295356b7557SThierry Reding * i.e. 1500 bytes.
296356b7557SThierry Reding */
2976deee222SJoao Pinto switch (fifosz) {
298356b7557SThierry Reding case 4096:
299356b7557SThierry Reding /* This violates the above formula because of FIFO size
300356b7557SThierry Reding * limit therefore overflow may occur in spite of this.
301356b7557SThierry Reding */
302356b7557SThierry Reding rfd = 0x03; /* Full-2.5K */
303356b7557SThierry Reding rfa = 0x01; /* Full-1.5K */
304356b7557SThierry Reding break;
305356b7557SThierry Reding
306356b7557SThierry Reding default:
307854248e5SJose Abreu rfd = 0x07; /* Full-4.5K */
308854248e5SJose Abreu rfa = 0x04; /* Full-3K */
309356b7557SThierry Reding break;
310356b7557SThierry Reding }
311356b7557SThierry Reding
312356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
313356b7557SThierry Reding mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
314356b7557SThierry Reding
315356b7557SThierry Reding mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
316356b7557SThierry Reding mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
317356b7557SThierry Reding }
318356b7557SThierry Reding
319*33719b57SAndrew Halaney writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(dwmac4_addrs, channel));
32048863ce5SAlexandre TORGUE }
32148863ce5SAlexandre TORGUE
dwmac4_dma_tx_chan_op_mode(struct stmmac_priv * priv,void __iomem * ioaddr,int mode,u32 channel,int fifosz,u8 qmode)3221d84b487SAndrew Halaney static void dwmac4_dma_tx_chan_op_mode(struct stmmac_priv *priv,
3231d84b487SAndrew Halaney void __iomem *ioaddr, int mode,
324a0daae13SJose Abreu u32 channel, int fifosz, u8 qmode)
32548863ce5SAlexandre TORGUE {
326*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
327*33719b57SAndrew Halaney u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,
328*33719b57SAndrew Halaney channel));
32952a76235SJose Abreu unsigned int tqs = fifosz / 256 - 1;
3306deee222SJoao Pinto
3316deee222SJoao Pinto if (mode == SF_DMA_MODE) {
3326deee222SJoao Pinto pr_debug("GMAC: enable TX store and forward mode\n");
3336deee222SJoao Pinto /* Transmit COE type 2 cannot be done in cut-through mode. */
3346deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TSF;
3356deee222SJoao Pinto } else {
3366deee222SJoao Pinto pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
3376deee222SJoao Pinto mtl_tx_op &= ~MTL_OP_MODE_TSF;
3386deee222SJoao Pinto mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
3396deee222SJoao Pinto /* Set the transmit threshold */
3406deee222SJoao Pinto if (mode <= 32)
3416deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_32;
3426deee222SJoao Pinto else if (mode <= 64)
3436deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_64;
3446deee222SJoao Pinto else if (mode <= 96)
3456deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_96;
3466deee222SJoao Pinto else if (mode <= 128)
3476deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_128;
3486deee222SJoao Pinto else if (mode <= 192)
3496deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_192;
3506deee222SJoao Pinto else if (mode <= 256)
3516deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_256;
3526deee222SJoao Pinto else if (mode <= 384)
3536deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_384;
3546deee222SJoao Pinto else
3556deee222SJoao Pinto mtl_tx_op |= MTL_OP_MODE_TTC_512;
3566deee222SJoao Pinto }
3576deee222SJoao Pinto /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
3586deee222SJoao Pinto * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
3596deee222SJoao Pinto * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
3606deee222SJoao Pinto * with reset values: TXQEN off, TQS 256 bytes.
3616deee222SJoao Pinto *
36252a76235SJose Abreu * TXQEN must be written for multi-channel operation and TQS must
36352a76235SJose Abreu * reflect the available fifo size per queue (total fifo size / number
36452a76235SJose Abreu * of enabled queues).
3656deee222SJoao Pinto */
366a0daae13SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
367a0daae13SJose Abreu if (qmode != MTL_QUEUE_AVB)
36852a76235SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN;
369a0daae13SJose Abreu else
370a0daae13SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
37152a76235SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
37252a76235SJose Abreu mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
37352a76235SJose Abreu
374*33719b57SAndrew Halaney writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
37548863ce5SAlexandre TORGUE }
37648863ce5SAlexandre TORGUE
dwmac4_get_hw_feature(void __iomem * ioaddr,struct dma_features * dma_cap)377075da584SHerve Codina static int dwmac4_get_hw_feature(void __iomem *ioaddr,
37848863ce5SAlexandre TORGUE struct dma_features *dma_cap)
37948863ce5SAlexandre TORGUE {
38048863ce5SAlexandre TORGUE u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
38148863ce5SAlexandre TORGUE
38248863ce5SAlexandre TORGUE /* MAC HW feature0 */
38348863ce5SAlexandre TORGUE dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
38448863ce5SAlexandre TORGUE dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
38548863ce5SAlexandre TORGUE dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
386c1be0022SJose Abreu dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
38748863ce5SAlexandre TORGUE dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
38848863ce5SAlexandre TORGUE dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
38948863ce5SAlexandre TORGUE dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
39048863ce5SAlexandre TORGUE dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
39148863ce5SAlexandre TORGUE dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
39248863ce5SAlexandre TORGUE /* MMC */
39348863ce5SAlexandre TORGUE dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
39448863ce5SAlexandre TORGUE /* IEEE 1588-2008 */
39548863ce5SAlexandre TORGUE dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
39648863ce5SAlexandre TORGUE /* 802.3az - Energy-Efficient Ethernet (EEE) */
39748863ce5SAlexandre TORGUE dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
39848863ce5SAlexandre TORGUE /* TX and RX csum */
39948863ce5SAlexandre TORGUE dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
40048863ce5SAlexandre TORGUE dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
4011d982e93SJose Abreu dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
402c9b10043SJose Abreu dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
40348863ce5SAlexandre TORGUE
40448863ce5SAlexandre TORGUE /* MAC HW feature1 */
40548863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
406dc07f5fdSJose Abreu dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
407b8ef7020SBiao Huang dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
40848863ce5SAlexandre TORGUE dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
40948863ce5SAlexandre TORGUE dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
4108c6fc097SJose Abreu dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
411560c07cbSThierry Reding
412560c07cbSThierry Reding dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
413560c07cbSThierry Reding switch (dma_cap->addr64) {
414560c07cbSThierry Reding case 0:
415560c07cbSThierry Reding dma_cap->addr64 = 32;
416560c07cbSThierry Reding break;
417560c07cbSThierry Reding case 1:
418560c07cbSThierry Reding dma_cap->addr64 = 40;
419560c07cbSThierry Reding break;
420560c07cbSThierry Reding case 2:
421560c07cbSThierry Reding dma_cap->addr64 = 48;
422560c07cbSThierry Reding break;
423560c07cbSThierry Reding default:
424560c07cbSThierry Reding dma_cap->addr64 = 32;
425560c07cbSThierry Reding break;
426560c07cbSThierry Reding }
427560c07cbSThierry Reding
42811fbf811SThierry Reding /* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
42911fbf811SThierry Reding * shifting and store the sizes in bytes.
43011fbf811SThierry Reding */
43111fbf811SThierry Reding dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
43211fbf811SThierry Reding dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
43348863ce5SAlexandre TORGUE /* MAC HW feature2 */
43448863ce5SAlexandre TORGUE hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
43548863ce5SAlexandre TORGUE /* TX and RX number of channels */
43648863ce5SAlexandre TORGUE dma_cap->number_rx_channel =
43748863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
43848863ce5SAlexandre TORGUE dma_cap->number_tx_channel =
43948863ce5SAlexandre TORGUE ((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
4409eb12474Sjpinto /* TX and RX number of queues */
4419eb12474Sjpinto dma_cap->number_rx_queues =
4429eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
4439eb12474Sjpinto dma_cap->number_tx_queues =
4449eb12474Sjpinto ((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
4459a8a02c9SJose Abreu /* PPS output */
4469a8a02c9SJose Abreu dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
44748863ce5SAlexandre TORGUE
44848863ce5SAlexandre TORGUE /* IEEE 1588-2002 */
44948863ce5SAlexandre TORGUE dma_cap->time_stamp = 0;
450341f67e4STan Tee Min /* Number of Auxiliary Snapshot Inputs */
451341f67e4STan Tee Min dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;
4528bf993a5SJose Abreu
4538bf993a5SJose Abreu /* MAC HW feature3 */
4548bf993a5SJose Abreu hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
4558bf993a5SJose Abreu
4568bf993a5SJose Abreu /* 5.10 Features */
4578bf993a5SJose Abreu dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
45858ae9281SJose Abreu dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
4597c728274SJose Abreu dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
460504723afSJose Abreu dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
461504723afSJose Abreu dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
462504723afSJose Abreu dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
4634dbbe8ddSJose Abreu dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
4644dbbe8ddSJose Abreu dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
4654dbbe8ddSJose Abreu dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
466e94e3f3bSJose Abreu dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
467075da584SHerve Codina
468075da584SHerve Codina return 0;
46948863ce5SAlexandre TORGUE }
47048863ce5SAlexandre TORGUE
47148863ce5SAlexandre TORGUE /* Enable/disable TSO feature and set MSS */
dwmac4_enable_tso(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)4721d84b487SAndrew Halaney static void dwmac4_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr,
4731d84b487SAndrew Halaney bool en, u32 chan)
47448863ce5SAlexandre TORGUE {
475*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
47648863ce5SAlexandre TORGUE u32 value;
47748863ce5SAlexandre TORGUE
47848863ce5SAlexandre TORGUE if (en) {
47948863ce5SAlexandre TORGUE /* enable TSO */
480*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48148863ce5SAlexandre TORGUE writel(value | DMA_CONTROL_TSE,
482*33719b57SAndrew Halaney ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48348863ce5SAlexandre TORGUE } else {
48448863ce5SAlexandre TORGUE /* enable TSO */
485*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48648863ce5SAlexandre TORGUE writel(value & ~DMA_CONTROL_TSE,
487*33719b57SAndrew Halaney ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
48848863ce5SAlexandre TORGUE }
48948863ce5SAlexandre TORGUE }
49048863ce5SAlexandre TORGUE
dwmac4_qmode(struct stmmac_priv * priv,void __iomem * ioaddr,u32 channel,u8 qmode)4911d84b487SAndrew Halaney static void dwmac4_qmode(struct stmmac_priv *priv, void __iomem *ioaddr,
4921d84b487SAndrew Halaney u32 channel, u8 qmode)
4931f705bc6SJose Abreu {
494*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
495*33719b57SAndrew Halaney u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs,
496*33719b57SAndrew Halaney channel));
4971f705bc6SJose Abreu
4981f705bc6SJose Abreu mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
4991f705bc6SJose Abreu if (qmode != MTL_QUEUE_AVB)
5001f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN;
5011f705bc6SJose Abreu else
5021f705bc6SJose Abreu mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
5031f705bc6SJose Abreu
504*33719b57SAndrew Halaney writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(dwmac4_addrs, channel));
5051f705bc6SJose Abreu }
5061f705bc6SJose Abreu
dwmac4_set_bfsize(struct stmmac_priv * priv,void __iomem * ioaddr,int bfsize,u32 chan)5071d84b487SAndrew Halaney static void dwmac4_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr,
5081d84b487SAndrew Halaney int bfsize, u32 chan)
5094205c88eSJose Abreu {
510*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
511*33719b57SAndrew Halaney u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
5124205c88eSJose Abreu
5134205c88eSJose Abreu value &= ~DMA_RBSZ_MASK;
5144205c88eSJose Abreu value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
5154205c88eSJose Abreu
516*33719b57SAndrew Halaney writel(value, ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan));
5174205c88eSJose Abreu }
5184205c88eSJose Abreu
dwmac4_enable_sph(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)5191d84b487SAndrew Halaney static void dwmac4_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr,
5201d84b487SAndrew Halaney bool en, u32 chan)
5218c6fc097SJose Abreu {
522*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
5238c6fc097SJose Abreu u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
5248c6fc097SJose Abreu
5258c6fc097SJose Abreu value &= ~GMAC_CONFIG_HDSMS;
5268c6fc097SJose Abreu value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
5278c6fc097SJose Abreu writel(value, ioaddr + GMAC_EXT_CONFIG);
5288c6fc097SJose Abreu
529*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
5308c6fc097SJose Abreu if (en)
5318c6fc097SJose Abreu value |= DMA_CONTROL_SPH;
5328c6fc097SJose Abreu else
5338c6fc097SJose Abreu value &= ~DMA_CONTROL_SPH;
534*33719b57SAndrew Halaney writel(value, ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan));
5358c6fc097SJose Abreu }
5368c6fc097SJose Abreu
dwmac4_enable_tbs(struct stmmac_priv * priv,void __iomem * ioaddr,bool en,u32 chan)5371d84b487SAndrew Halaney static int dwmac4_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr,
5381d84b487SAndrew Halaney bool en, u32 chan)
53958ae9281SJose Abreu {
540*33719b57SAndrew Halaney const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
541*33719b57SAndrew Halaney u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
54258ae9281SJose Abreu
54358ae9281SJose Abreu if (en)
54458ae9281SJose Abreu value |= DMA_CONTROL_EDSE;
54558ae9281SJose Abreu else
54658ae9281SJose Abreu value &= ~DMA_CONTROL_EDSE;
54758ae9281SJose Abreu
548*33719b57SAndrew Halaney writel(value, ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan));
54958ae9281SJose Abreu
550*33719b57SAndrew Halaney value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs,
551*33719b57SAndrew Halaney chan)) & DMA_CONTROL_EDSE;
55258ae9281SJose Abreu if (en && !value)
55358ae9281SJose Abreu return -EIO;
55458ae9281SJose Abreu
55558ae9281SJose Abreu writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
55658ae9281SJose Abreu return 0;
55758ae9281SJose Abreu }
55858ae9281SJose Abreu
55948863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac4_dma_ops = {
56048863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset,
56148863ce5SAlexandre TORGUE .init = dwmac4_dma_init,
56247f2a9ceSJoao Pinto .init_chan = dwmac4_dma_init_channel,
56347f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan,
56447f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan,
56548863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi,
56648863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs,
5676deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
5686deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
56948863ce5SAlexandre TORGUE .enable_dma_irq = dwmac4_enable_dma_irq,
57048863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq,
57148863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx,
57248863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx,
57348863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx,
57448863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx,
57548863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt,
57648863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature,
57748863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog,
57848863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len,
57948863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len,
58048863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
58148863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
58248863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso,
5831f705bc6SJose Abreu .qmode = dwmac4_qmode,
5844205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize,
5858c6fc097SJose Abreu .enable_sph = dwmac4_enable_sph,
58648863ce5SAlexandre TORGUE };
58748863ce5SAlexandre TORGUE
58848863ce5SAlexandre TORGUE const struct stmmac_dma_ops dwmac410_dma_ops = {
58948863ce5SAlexandre TORGUE .reset = dwmac4_dma_reset,
59048863ce5SAlexandre TORGUE .init = dwmac4_dma_init,
591879c348cSOng Boon Leong .init_chan = dwmac410_dma_init_channel,
59247f2a9ceSJoao Pinto .init_rx_chan = dwmac4_dma_init_rx_chan,
59347f2a9ceSJoao Pinto .init_tx_chan = dwmac4_dma_init_tx_chan,
59448863ce5SAlexandre TORGUE .axi = dwmac4_dma_axi,
59548863ce5SAlexandre TORGUE .dump_regs = dwmac4_dump_dma_regs,
5966deee222SJoao Pinto .dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
5976deee222SJoao Pinto .dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
59848863ce5SAlexandre TORGUE .enable_dma_irq = dwmac410_enable_dma_irq,
59948863ce5SAlexandre TORGUE .disable_dma_irq = dwmac4_disable_dma_irq,
60048863ce5SAlexandre TORGUE .start_tx = dwmac4_dma_start_tx,
60148863ce5SAlexandre TORGUE .stop_tx = dwmac4_dma_stop_tx,
60248863ce5SAlexandre TORGUE .start_rx = dwmac4_dma_start_rx,
60348863ce5SAlexandre TORGUE .stop_rx = dwmac4_dma_stop_rx,
60448863ce5SAlexandre TORGUE .dma_interrupt = dwmac4_dma_interrupt,
60548863ce5SAlexandre TORGUE .get_hw_feature = dwmac4_get_hw_feature,
60648863ce5SAlexandre TORGUE .rx_watchdog = dwmac4_rx_watchdog,
60748863ce5SAlexandre TORGUE .set_rx_ring_len = dwmac4_set_rx_ring_len,
60848863ce5SAlexandre TORGUE .set_tx_ring_len = dwmac4_set_tx_ring_len,
60948863ce5SAlexandre TORGUE .set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
61048863ce5SAlexandre TORGUE .set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
61148863ce5SAlexandre TORGUE .enable_tso = dwmac4_enable_tso,
6121f705bc6SJose Abreu .qmode = dwmac4_qmode,
6134205c88eSJose Abreu .set_bfsize = dwmac4_set_bfsize,
6148c6fc097SJose Abreu .enable_sph = dwmac4_enable_sph,
61558ae9281SJose Abreu .enable_tbs = dwmac4_enable_tbs,
61648863ce5SAlexandre TORGUE };
617