1 /* 2 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 3 * 4 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 5 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/platform_device.h> 17 #include <linux/stmmac.h> 18 #include <linux/phy.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/regmap.h> 22 #include <linux/clk.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 26 #include "stmmac_platform.h" 27 28 #define DWMAC_125MHZ 125000000 29 #define DWMAC_50MHZ 50000000 30 #define DWMAC_25MHZ 25000000 31 #define DWMAC_2_5MHZ 2500000 32 33 #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 34 iface == PHY_INTERFACE_MODE_RGMII_ID || \ 35 iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 36 iface == PHY_INTERFACE_MODE_RGMII_TXID) 37 38 #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 39 iface == PHY_INTERFACE_MODE_GMII) 40 41 /* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families) 42 * 43 * Below table summarizes the clock requirement and clock sources for 44 * supported phy interface modes with link speeds. 45 * ________________________________________________ 46 *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 47 * ------------------------------------------------ 48 *| MII | n/a | 25Mhz | 49 *| | | txclk | 50 * ------------------------------------------------ 51 *| GMII | 125Mhz | 25Mhz | 52 *| | clk-125/txclk | txclk | 53 * ------------------------------------------------ 54 *| RGMII | 125Mhz | 25Mhz | 55 *| | clk-125/txclk | clkgen | 56 *| | clkgen | | 57 * ------------------------------------------------ 58 *| RMII | n/a | 25Mhz | 59 *| | |clkgen/phyclk-in | 60 * ------------------------------------------------ 61 * 62 * Register Configuration 63 *------------------------------- 64 * src |BIT(8)| BIT(7)| BIT(6)| 65 *------------------------------- 66 * txclk | 0 | n/a | 1 | 67 *------------------------------- 68 * ck_125| 0 | n/a | 0 | 69 *------------------------------- 70 * phyclk| 1 | 0 | n/a | 71 *------------------------------- 72 * clkgen| 1 | 1 | n/a | 73 *------------------------------- 74 */ 75 76 #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 77 #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 78 #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 79 #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 80 81 /* STiD127 register definitions 82 *----------------------- 83 * src |BIT(6)| BIT(7)| 84 *----------------------- 85 * MII | 1 | n/a | 86 *----------------------- 87 * RMII | n/a | 1 | 88 * clkgen| | | 89 *----------------------- 90 * RMII | n/a | 0 | 91 * phyclk| | | 92 *----------------------- 93 * RGMII | 1 | n/a | 94 * clkgen| | | 95 *----------------------- 96 */ 97 98 #define STID127_RETIME_SRC_MASK GENMASK(7, 6) 99 #define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 100 #define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) 101 102 #define ENMII_MASK GENMASK(5, 5) 103 #define ENMII BIT(5) 104 #define EN_MASK GENMASK(1, 1) 105 #define EN BIT(1) 106 107 /* 108 * 3 bits [4:2] 109 * 000-GMII/MII 110 * 001-RGMII 111 * 010-SGMII 112 * 100-RMII 113 */ 114 #define MII_PHY_SEL_MASK GENMASK(4, 2) 115 #define ETH_PHY_SEL_RMII BIT(4) 116 #define ETH_PHY_SEL_SGMII BIT(3) 117 #define ETH_PHY_SEL_RGMII BIT(2) 118 #define ETH_PHY_SEL_GMII 0x0 119 #define ETH_PHY_SEL_MII 0x0 120 121 struct sti_dwmac { 122 int interface; /* MII interface */ 123 bool ext_phyclk; /* Clock from external PHY */ 124 u32 tx_retime_src; /* TXCLK Retiming*/ 125 struct clk *clk; /* PHY clock */ 126 u32 ctrl_reg; /* GMAC glue-logic control register */ 127 int clk_sel_reg; /* GMAC ext clk selection register */ 128 struct device *dev; 129 struct regmap *regmap; 130 u32 speed; 131 }; 132 133 static u32 phy_intf_sels[] = { 134 [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 135 [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 136 [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 137 [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 138 [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 139 [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 140 }; 141 142 enum { 143 TX_RETIME_SRC_NA = 0, 144 TX_RETIME_SRC_TXCLK = 1, 145 TX_RETIME_SRC_CLK_125, 146 TX_RETIME_SRC_PHYCLK, 147 TX_RETIME_SRC_CLKGEN, 148 }; 149 150 static u32 stih4xx_tx_retime_val[] = { 151 [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 152 [TX_RETIME_SRC_CLK_125] = 0x0, 153 [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 154 [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 155 | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 156 }; 157 158 static void stih4xx_fix_retime_src(void *priv, u32 spd) 159 { 160 struct sti_dwmac *dwmac = priv; 161 u32 src = dwmac->tx_retime_src; 162 u32 reg = dwmac->ctrl_reg; 163 u32 freq = 0; 164 165 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 166 src = TX_RETIME_SRC_TXCLK; 167 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 168 if (dwmac->ext_phyclk) { 169 src = TX_RETIME_SRC_PHYCLK; 170 } else { 171 src = TX_RETIME_SRC_CLKGEN; 172 freq = DWMAC_50MHZ; 173 } 174 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 175 /* On GiGa clk source can be either ext or from clkgen */ 176 if (spd == SPEED_1000) { 177 freq = DWMAC_125MHZ; 178 } else { 179 /* Switch to clkgen for these speeds */ 180 src = TX_RETIME_SRC_CLKGEN; 181 if (spd == SPEED_100) 182 freq = DWMAC_25MHZ; 183 else if (spd == SPEED_10) 184 freq = DWMAC_2_5MHZ; 185 } 186 } 187 188 if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk && freq) 189 clk_set_rate(dwmac->clk, freq); 190 191 regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 192 stih4xx_tx_retime_val[src]); 193 } 194 195 static void stid127_fix_retime_src(void *priv, u32 spd) 196 { 197 struct sti_dwmac *dwmac = priv; 198 u32 reg = dwmac->ctrl_reg; 199 u32 freq = 0; 200 u32 val = 0; 201 202 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 203 val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 204 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 205 if (!dwmac->ext_phyclk) { 206 val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; 207 freq = DWMAC_50MHZ; 208 } 209 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 210 val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 211 if (spd == SPEED_1000) 212 freq = DWMAC_125MHZ; 213 else if (spd == SPEED_100) 214 freq = DWMAC_25MHZ; 215 else if (spd == SPEED_10) 216 freq = DWMAC_2_5MHZ; 217 } 218 219 if (dwmac->clk && freq) 220 clk_set_rate(dwmac->clk, freq); 221 222 regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); 223 } 224 225 static void sti_dwmac_ctrl_init(struct sti_dwmac *dwmac) 226 { 227 struct regmap *regmap = dwmac->regmap; 228 int iface = dwmac->interface; 229 struct device *dev = dwmac->dev; 230 struct device_node *np = dev->of_node; 231 u32 reg = dwmac->ctrl_reg; 232 u32 val; 233 234 if (dwmac->clk) 235 clk_prepare_enable(dwmac->clk); 236 237 if (of_property_read_bool(np, "st,gmac_en")) 238 regmap_update_bits(regmap, reg, EN_MASK, EN); 239 240 regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 241 242 val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 243 regmap_update_bits(regmap, reg, ENMII_MASK, val); 244 } 245 246 static int stix4xx_init(struct platform_device *pdev, void *priv) 247 { 248 struct sti_dwmac *dwmac = priv; 249 u32 spd = dwmac->speed; 250 251 sti_dwmac_ctrl_init(dwmac); 252 253 stih4xx_fix_retime_src(priv, spd); 254 255 return 0; 256 } 257 258 static int stid127_init(struct platform_device *pdev, void *priv) 259 { 260 struct sti_dwmac *dwmac = priv; 261 u32 spd = dwmac->speed; 262 263 sti_dwmac_ctrl_init(dwmac); 264 265 stid127_fix_retime_src(priv, spd); 266 267 return 0; 268 } 269 270 static void sti_dwmac_exit(struct platform_device *pdev, void *priv) 271 { 272 struct sti_dwmac *dwmac = priv; 273 274 if (dwmac->clk) 275 clk_disable_unprepare(dwmac->clk); 276 } 277 static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 278 struct platform_device *pdev) 279 { 280 struct resource *res; 281 struct device *dev = &pdev->dev; 282 struct device_node *np = dev->of_node; 283 struct regmap *regmap; 284 int err; 285 286 if (!np) 287 return -EINVAL; 288 289 /* clk selection from extra syscfg register */ 290 dwmac->clk_sel_reg = -ENXIO; 291 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 292 if (res) 293 dwmac->clk_sel_reg = res->start; 294 295 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 296 if (IS_ERR(regmap)) 297 return PTR_ERR(regmap); 298 299 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg); 300 if (err) { 301 dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err); 302 return err; 303 } 304 305 dwmac->dev = dev; 306 dwmac->interface = of_get_phy_mode(np); 307 dwmac->regmap = regmap; 308 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 309 dwmac->tx_retime_src = TX_RETIME_SRC_NA; 310 dwmac->speed = SPEED_100; 311 312 if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 313 const char *rs; 314 315 err = of_property_read_string(np, "st,tx-retime-src", &rs); 316 if (err < 0) { 317 dev_warn(dev, "Use internal clock source\n"); 318 dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 319 } else if (!strcasecmp(rs, "clk_125")) { 320 dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 321 } else if (!strcasecmp(rs, "txclk")) { 322 dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 323 } 324 325 dwmac->speed = SPEED_1000; 326 } 327 328 dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 329 if (IS_ERR(dwmac->clk)) { 330 dev_warn(dev, "No phy clock provided...\n"); 331 dwmac->clk = NULL; 332 } 333 334 return 0; 335 } 336 337 static void *sti_dwmac_setup(struct platform_device *pdev) 338 { 339 struct sti_dwmac *dwmac; 340 int ret; 341 342 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 343 if (!dwmac) 344 return ERR_PTR(-ENOMEM); 345 346 ret = sti_dwmac_parse_data(dwmac, pdev); 347 if (ret) { 348 dev_err(&pdev->dev, "Unable to parse OF data\n"); 349 return ERR_PTR(ret); 350 } 351 352 return dwmac; 353 } 354 355 static const struct stmmac_of_data stih4xx_dwmac_data = { 356 .fix_mac_speed = stih4xx_fix_retime_src, 357 .setup = sti_dwmac_setup, 358 .init = stix4xx_init, 359 .exit = sti_dwmac_exit, 360 }; 361 362 static const struct stmmac_of_data stid127_dwmac_data = { 363 .fix_mac_speed = stid127_fix_retime_src, 364 .setup = sti_dwmac_setup, 365 .init = stid127_init, 366 .exit = sti_dwmac_exit, 367 }; 368 369 static const struct of_device_id sti_dwmac_match[] = { 370 { .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data}, 371 { .compatible = "st,stih416-dwmac", .data = &stih4xx_dwmac_data}, 372 { .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data}, 373 { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, 374 { } 375 }; 376 MODULE_DEVICE_TABLE(of, sti_dwmac_match); 377 378 static struct platform_driver sti_dwmac_driver = { 379 .probe = stmmac_pltfr_probe, 380 .remove = stmmac_pltfr_remove, 381 .driver = { 382 .name = "sti-dwmac", 383 .pm = &stmmac_pltfr_pm_ops, 384 .of_match_table = sti_dwmac_match, 385 }, 386 }; 387 module_platform_driver(sti_dwmac_driver); 388 389 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>"); 390 MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer"); 391 MODULE_LICENSE("GPL"); 392