1 /* 2 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 3 * 4 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 5 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/platform_device.h> 17 #include <linux/stmmac.h> 18 #include <linux/phy.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/regmap.h> 22 #include <linux/clk.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_net.h> 26 27 #include "stmmac_platform.h" 28 29 #define DWMAC_125MHZ 125000000 30 #define DWMAC_50MHZ 50000000 31 #define DWMAC_25MHZ 25000000 32 #define DWMAC_2_5MHZ 2500000 33 34 #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 35 iface == PHY_INTERFACE_MODE_RGMII_ID || \ 36 iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 37 iface == PHY_INTERFACE_MODE_RGMII_TXID) 38 39 #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 40 iface == PHY_INTERFACE_MODE_GMII) 41 42 /* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families) 43 * 44 * Below table summarizes the clock requirement and clock sources for 45 * supported phy interface modes with link speeds. 46 * ________________________________________________ 47 *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 48 * ------------------------------------------------ 49 *| MII | n/a | 25Mhz | 50 *| | | txclk | 51 * ------------------------------------------------ 52 *| GMII | 125Mhz | 25Mhz | 53 *| | clk-125/txclk | txclk | 54 * ------------------------------------------------ 55 *| RGMII | 125Mhz | 25Mhz | 56 *| | clk-125/txclk | clkgen | 57 *| | clkgen | | 58 * ------------------------------------------------ 59 *| RMII | n/a | 25Mhz | 60 *| | |clkgen/phyclk-in | 61 * ------------------------------------------------ 62 * 63 * Register Configuration 64 *------------------------------- 65 * src |BIT(8)| BIT(7)| BIT(6)| 66 *------------------------------- 67 * txclk | 0 | n/a | 1 | 68 *------------------------------- 69 * ck_125| 0 | n/a | 0 | 70 *------------------------------- 71 * phyclk| 1 | 0 | n/a | 72 *------------------------------- 73 * clkgen| 1 | 1 | n/a | 74 *------------------------------- 75 */ 76 77 #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 78 #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 79 #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 80 #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 81 82 /* STiD127 register definitions 83 *----------------------- 84 * src |BIT(6)| BIT(7)| 85 *----------------------- 86 * MII | 1 | n/a | 87 *----------------------- 88 * RMII | n/a | 1 | 89 * clkgen| | | 90 *----------------------- 91 * RMII | n/a | 0 | 92 * phyclk| | | 93 *----------------------- 94 * RGMII | 1 | n/a | 95 * clkgen| | | 96 *----------------------- 97 */ 98 99 #define STID127_RETIME_SRC_MASK GENMASK(7, 6) 100 #define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 101 #define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) 102 103 #define ENMII_MASK GENMASK(5, 5) 104 #define ENMII BIT(5) 105 #define EN_MASK GENMASK(1, 1) 106 #define EN BIT(1) 107 108 /* 109 * 3 bits [4:2] 110 * 000-GMII/MII 111 * 001-RGMII 112 * 010-SGMII 113 * 100-RMII 114 */ 115 #define MII_PHY_SEL_MASK GENMASK(4, 2) 116 #define ETH_PHY_SEL_RMII BIT(4) 117 #define ETH_PHY_SEL_SGMII BIT(3) 118 #define ETH_PHY_SEL_RGMII BIT(2) 119 #define ETH_PHY_SEL_GMII 0x0 120 #define ETH_PHY_SEL_MII 0x0 121 122 struct sti_dwmac { 123 int interface; /* MII interface */ 124 bool ext_phyclk; /* Clock from external PHY */ 125 u32 tx_retime_src; /* TXCLK Retiming*/ 126 struct clk *clk; /* PHY clock */ 127 u32 ctrl_reg; /* GMAC glue-logic control register */ 128 int clk_sel_reg; /* GMAC ext clk selection register */ 129 struct device *dev; 130 struct regmap *regmap; 131 u32 speed; 132 void (*fix_retime_src)(void *priv, unsigned int speed); 133 }; 134 135 struct sti_dwmac_of_data { 136 void (*fix_retime_src)(void *priv, unsigned int speed); 137 }; 138 139 static u32 phy_intf_sels[] = { 140 [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 141 [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 142 [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 143 [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 144 [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 145 [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 146 }; 147 148 enum { 149 TX_RETIME_SRC_NA = 0, 150 TX_RETIME_SRC_TXCLK = 1, 151 TX_RETIME_SRC_CLK_125, 152 TX_RETIME_SRC_PHYCLK, 153 TX_RETIME_SRC_CLKGEN, 154 }; 155 156 static u32 stih4xx_tx_retime_val[] = { 157 [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 158 [TX_RETIME_SRC_CLK_125] = 0x0, 159 [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 160 [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 161 | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 162 }; 163 164 static void stih4xx_fix_retime_src(void *priv, u32 spd) 165 { 166 struct sti_dwmac *dwmac = priv; 167 u32 src = dwmac->tx_retime_src; 168 u32 reg = dwmac->ctrl_reg; 169 u32 freq = 0; 170 171 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 172 src = TX_RETIME_SRC_TXCLK; 173 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 174 if (dwmac->ext_phyclk) { 175 src = TX_RETIME_SRC_PHYCLK; 176 } else { 177 src = TX_RETIME_SRC_CLKGEN; 178 freq = DWMAC_50MHZ; 179 } 180 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 181 /* On GiGa clk source can be either ext or from clkgen */ 182 if (spd == SPEED_1000) { 183 freq = DWMAC_125MHZ; 184 } else { 185 /* Switch to clkgen for these speeds */ 186 src = TX_RETIME_SRC_CLKGEN; 187 if (spd == SPEED_100) 188 freq = DWMAC_25MHZ; 189 else if (spd == SPEED_10) 190 freq = DWMAC_2_5MHZ; 191 } 192 } 193 194 if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk && freq) 195 clk_set_rate(dwmac->clk, freq); 196 197 regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 198 stih4xx_tx_retime_val[src]); 199 } 200 201 static void stid127_fix_retime_src(void *priv, u32 spd) 202 { 203 struct sti_dwmac *dwmac = priv; 204 u32 reg = dwmac->ctrl_reg; 205 u32 freq = 0; 206 u32 val = 0; 207 208 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 209 val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 210 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 211 if (!dwmac->ext_phyclk) { 212 val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; 213 freq = DWMAC_50MHZ; 214 } 215 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 216 val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 217 if (spd == SPEED_1000) 218 freq = DWMAC_125MHZ; 219 else if (spd == SPEED_100) 220 freq = DWMAC_25MHZ; 221 else if (spd == SPEED_10) 222 freq = DWMAC_2_5MHZ; 223 } 224 225 if (dwmac->clk && freq) 226 clk_set_rate(dwmac->clk, freq); 227 228 regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); 229 } 230 231 static int sti_dwmac_init(struct platform_device *pdev, void *priv) 232 { 233 struct sti_dwmac *dwmac = priv; 234 struct regmap *regmap = dwmac->regmap; 235 int iface = dwmac->interface; 236 struct device *dev = dwmac->dev; 237 struct device_node *np = dev->of_node; 238 u32 reg = dwmac->ctrl_reg; 239 u32 val; 240 241 if (dwmac->clk) 242 clk_prepare_enable(dwmac->clk); 243 244 if (of_property_read_bool(np, "st,gmac_en")) 245 regmap_update_bits(regmap, reg, EN_MASK, EN); 246 247 regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 248 249 val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 250 regmap_update_bits(regmap, reg, ENMII_MASK, val); 251 252 dwmac->fix_retime_src(priv, dwmac->speed); 253 254 return 0; 255 } 256 257 static void sti_dwmac_exit(struct platform_device *pdev, void *priv) 258 { 259 struct sti_dwmac *dwmac = priv; 260 261 if (dwmac->clk) 262 clk_disable_unprepare(dwmac->clk); 263 } 264 static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 265 struct platform_device *pdev) 266 { 267 struct resource *res; 268 struct device *dev = &pdev->dev; 269 struct device_node *np = dev->of_node; 270 struct regmap *regmap; 271 int err; 272 273 if (!np) 274 return -EINVAL; 275 276 /* clk selection from extra syscfg register */ 277 dwmac->clk_sel_reg = -ENXIO; 278 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 279 if (res) 280 dwmac->clk_sel_reg = res->start; 281 282 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 283 if (IS_ERR(regmap)) 284 return PTR_ERR(regmap); 285 286 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg); 287 if (err) { 288 dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err); 289 return err; 290 } 291 292 dwmac->dev = dev; 293 dwmac->interface = of_get_phy_mode(np); 294 dwmac->regmap = regmap; 295 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 296 dwmac->tx_retime_src = TX_RETIME_SRC_NA; 297 dwmac->speed = SPEED_100; 298 299 if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 300 const char *rs; 301 302 dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 303 304 err = of_property_read_string(np, "st,tx-retime-src", &rs); 305 if (err < 0) { 306 dev_warn(dev, "Use internal clock source\n"); 307 } else { 308 if (!strcasecmp(rs, "clk_125")) 309 dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 310 else if (!strcasecmp(rs, "txclk")) 311 dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 312 } 313 dwmac->speed = SPEED_1000; 314 } 315 316 dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 317 if (IS_ERR(dwmac->clk)) { 318 dev_warn(dev, "No phy clock provided...\n"); 319 dwmac->clk = NULL; 320 } 321 322 return 0; 323 } 324 325 static int sti_dwmac_probe(struct platform_device *pdev) 326 { 327 struct plat_stmmacenet_data *plat_dat; 328 const struct sti_dwmac_of_data *data; 329 struct stmmac_resources stmmac_res; 330 struct sti_dwmac *dwmac; 331 int ret; 332 333 data = of_device_get_match_data(&pdev->dev); 334 if (!data) { 335 dev_err(&pdev->dev, "No OF match data provided\n"); 336 return -EINVAL; 337 } 338 339 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 340 if (ret) 341 return ret; 342 343 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 344 if (IS_ERR(plat_dat)) 345 return PTR_ERR(plat_dat); 346 347 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 348 if (!dwmac) 349 return -ENOMEM; 350 351 ret = sti_dwmac_parse_data(dwmac, pdev); 352 if (ret) { 353 dev_err(&pdev->dev, "Unable to parse OF data\n"); 354 return ret; 355 } 356 357 dwmac->fix_retime_src = data->fix_retime_src; 358 359 plat_dat->bsp_priv = dwmac; 360 plat_dat->init = sti_dwmac_init; 361 plat_dat->exit = sti_dwmac_exit; 362 plat_dat->fix_mac_speed = data->fix_retime_src; 363 364 ret = sti_dwmac_init(pdev, plat_dat->bsp_priv); 365 if (ret) 366 return ret; 367 368 return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 369 } 370 371 static const struct sti_dwmac_of_data stih4xx_dwmac_data = { 372 .fix_retime_src = stih4xx_fix_retime_src, 373 }; 374 375 static const struct sti_dwmac_of_data stid127_dwmac_data = { 376 .fix_retime_src = stid127_fix_retime_src, 377 }; 378 379 static const struct of_device_id sti_dwmac_match[] = { 380 { .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data}, 381 { .compatible = "st,stih416-dwmac", .data = &stih4xx_dwmac_data}, 382 { .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data}, 383 { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, 384 { } 385 }; 386 MODULE_DEVICE_TABLE(of, sti_dwmac_match); 387 388 static struct platform_driver sti_dwmac_driver = { 389 .probe = sti_dwmac_probe, 390 .remove = stmmac_pltfr_remove, 391 .driver = { 392 .name = "sti-dwmac", 393 .pm = &stmmac_pltfr_pm_ops, 394 .of_match_table = sti_dwmac_match, 395 }, 396 }; 397 module_platform_driver(sti_dwmac_driver); 398 399 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>"); 400 MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer"); 401 MODULE_LICENSE("GPL"); 402