1 /* 2 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 3 * 4 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 5 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 6 * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/platform_device.h> 17 #include <linux/stmmac.h> 18 #include <linux/phy.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/regmap.h> 22 #include <linux/clk.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_net.h> 26 27 #include "stmmac_platform.h" 28 29 #define DWMAC_125MHZ 125000000 30 #define DWMAC_50MHZ 50000000 31 #define DWMAC_25MHZ 25000000 32 #define DWMAC_2_5MHZ 2500000 33 34 #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 35 iface == PHY_INTERFACE_MODE_RGMII_ID || \ 36 iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 37 iface == PHY_INTERFACE_MODE_RGMII_TXID) 38 39 #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 40 iface == PHY_INTERFACE_MODE_GMII) 41 42 /* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families) 43 * 44 * Below table summarizes the clock requirement and clock sources for 45 * supported phy interface modes with link speeds. 46 * ________________________________________________ 47 *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 48 * ------------------------------------------------ 49 *| MII | n/a | 25Mhz | 50 *| | | txclk | 51 * ------------------------------------------------ 52 *| GMII | 125Mhz | 25Mhz | 53 *| | clk-125/txclk | txclk | 54 * ------------------------------------------------ 55 *| RGMII | 125Mhz | 25Mhz | 56 *| | clk-125/txclk | clkgen | 57 *| | clkgen | | 58 * ------------------------------------------------ 59 *| RMII | n/a | 25Mhz | 60 *| | |clkgen/phyclk-in | 61 * ------------------------------------------------ 62 * 63 * Register Configuration 64 *------------------------------- 65 * src |BIT(8)| BIT(7)| BIT(6)| 66 *------------------------------- 67 * txclk | 0 | n/a | 1 | 68 *------------------------------- 69 * ck_125| 0 | n/a | 0 | 70 *------------------------------- 71 * phyclk| 1 | 0 | n/a | 72 *------------------------------- 73 * clkgen| 1 | 1 | n/a | 74 *------------------------------- 75 */ 76 77 #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 78 #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 79 #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 80 #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 81 82 /* STiD127 register definitions 83 *----------------------- 84 * src |BIT(6)| BIT(7)| 85 *----------------------- 86 * MII | 1 | n/a | 87 *----------------------- 88 * RMII | n/a | 1 | 89 * clkgen| | | 90 *----------------------- 91 * RMII | n/a | 0 | 92 * phyclk| | | 93 *----------------------- 94 * RGMII | 1 | n/a | 95 * clkgen| | | 96 *----------------------- 97 */ 98 99 #define STID127_RETIME_SRC_MASK GENMASK(7, 6) 100 #define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 101 #define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) 102 103 #define ENMII_MASK GENMASK(5, 5) 104 #define ENMII BIT(5) 105 #define EN_MASK GENMASK(1, 1) 106 #define EN BIT(1) 107 108 /* 109 * 3 bits [4:2] 110 * 000-GMII/MII 111 * 001-RGMII 112 * 010-SGMII 113 * 100-RMII 114 */ 115 #define MII_PHY_SEL_MASK GENMASK(4, 2) 116 #define ETH_PHY_SEL_RMII BIT(4) 117 #define ETH_PHY_SEL_SGMII BIT(3) 118 #define ETH_PHY_SEL_RGMII BIT(2) 119 #define ETH_PHY_SEL_GMII 0x0 120 #define ETH_PHY_SEL_MII 0x0 121 122 struct sti_dwmac { 123 int interface; /* MII interface */ 124 bool ext_phyclk; /* Clock from external PHY */ 125 u32 tx_retime_src; /* TXCLK Retiming*/ 126 struct clk *clk; /* PHY clock */ 127 u32 ctrl_reg; /* GMAC glue-logic control register */ 128 int clk_sel_reg; /* GMAC ext clk selection register */ 129 struct device *dev; 130 struct regmap *regmap; 131 u32 speed; 132 }; 133 134 static u32 phy_intf_sels[] = { 135 [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 136 [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 137 [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 138 [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 139 [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 140 [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 141 }; 142 143 enum { 144 TX_RETIME_SRC_NA = 0, 145 TX_RETIME_SRC_TXCLK = 1, 146 TX_RETIME_SRC_CLK_125, 147 TX_RETIME_SRC_PHYCLK, 148 TX_RETIME_SRC_CLKGEN, 149 }; 150 151 static u32 stih4xx_tx_retime_val[] = { 152 [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 153 [TX_RETIME_SRC_CLK_125] = 0x0, 154 [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 155 [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 156 | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 157 }; 158 159 static void stih4xx_fix_retime_src(void *priv, u32 spd) 160 { 161 struct sti_dwmac *dwmac = priv; 162 u32 src = dwmac->tx_retime_src; 163 u32 reg = dwmac->ctrl_reg; 164 u32 freq = 0; 165 166 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 167 src = TX_RETIME_SRC_TXCLK; 168 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 169 if (dwmac->ext_phyclk) { 170 src = TX_RETIME_SRC_PHYCLK; 171 } else { 172 src = TX_RETIME_SRC_CLKGEN; 173 freq = DWMAC_50MHZ; 174 } 175 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 176 /* On GiGa clk source can be either ext or from clkgen */ 177 if (spd == SPEED_1000) { 178 freq = DWMAC_125MHZ; 179 } else { 180 /* Switch to clkgen for these speeds */ 181 src = TX_RETIME_SRC_CLKGEN; 182 if (spd == SPEED_100) 183 freq = DWMAC_25MHZ; 184 else if (spd == SPEED_10) 185 freq = DWMAC_2_5MHZ; 186 } 187 } 188 189 if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk && freq) 190 clk_set_rate(dwmac->clk, freq); 191 192 regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 193 stih4xx_tx_retime_val[src]); 194 } 195 196 static void stid127_fix_retime_src(void *priv, u32 spd) 197 { 198 struct sti_dwmac *dwmac = priv; 199 u32 reg = dwmac->ctrl_reg; 200 u32 freq = 0; 201 u32 val = 0; 202 203 if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 204 val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 205 } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 206 if (!dwmac->ext_phyclk) { 207 val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; 208 freq = DWMAC_50MHZ; 209 } 210 } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 211 val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 212 if (spd == SPEED_1000) 213 freq = DWMAC_125MHZ; 214 else if (spd == SPEED_100) 215 freq = DWMAC_25MHZ; 216 else if (spd == SPEED_10) 217 freq = DWMAC_2_5MHZ; 218 } 219 220 if (dwmac->clk && freq) 221 clk_set_rate(dwmac->clk, freq); 222 223 regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); 224 } 225 226 static void sti_dwmac_ctrl_init(struct sti_dwmac *dwmac) 227 { 228 struct regmap *regmap = dwmac->regmap; 229 int iface = dwmac->interface; 230 struct device *dev = dwmac->dev; 231 struct device_node *np = dev->of_node; 232 u32 reg = dwmac->ctrl_reg; 233 u32 val; 234 235 if (dwmac->clk) 236 clk_prepare_enable(dwmac->clk); 237 238 if (of_property_read_bool(np, "st,gmac_en")) 239 regmap_update_bits(regmap, reg, EN_MASK, EN); 240 241 regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 242 243 val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 244 regmap_update_bits(regmap, reg, ENMII_MASK, val); 245 } 246 247 static int stix4xx_init(struct platform_device *pdev, void *priv) 248 { 249 struct sti_dwmac *dwmac = priv; 250 u32 spd = dwmac->speed; 251 252 sti_dwmac_ctrl_init(dwmac); 253 254 stih4xx_fix_retime_src(priv, spd); 255 256 return 0; 257 } 258 259 static int stid127_init(struct platform_device *pdev, void *priv) 260 { 261 struct sti_dwmac *dwmac = priv; 262 u32 spd = dwmac->speed; 263 264 sti_dwmac_ctrl_init(dwmac); 265 266 stid127_fix_retime_src(priv, spd); 267 268 return 0; 269 } 270 271 static void sti_dwmac_exit(struct platform_device *pdev, void *priv) 272 { 273 struct sti_dwmac *dwmac = priv; 274 275 if (dwmac->clk) 276 clk_disable_unprepare(dwmac->clk); 277 } 278 static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 279 struct platform_device *pdev) 280 { 281 struct resource *res; 282 struct device *dev = &pdev->dev; 283 struct device_node *np = dev->of_node; 284 struct regmap *regmap; 285 int err; 286 287 if (!np) 288 return -EINVAL; 289 290 /* clk selection from extra syscfg register */ 291 dwmac->clk_sel_reg = -ENXIO; 292 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 293 if (res) 294 dwmac->clk_sel_reg = res->start; 295 296 regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 297 if (IS_ERR(regmap)) 298 return PTR_ERR(regmap); 299 300 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg); 301 if (err) { 302 dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err); 303 return err; 304 } 305 306 dwmac->dev = dev; 307 dwmac->interface = of_get_phy_mode(np); 308 dwmac->regmap = regmap; 309 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 310 dwmac->tx_retime_src = TX_RETIME_SRC_NA; 311 dwmac->speed = SPEED_100; 312 313 if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 314 const char *rs; 315 316 err = of_property_read_string(np, "st,tx-retime-src", &rs); 317 if (err < 0) { 318 dev_warn(dev, "Use internal clock source\n"); 319 dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 320 } else if (!strcasecmp(rs, "clk_125")) { 321 dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 322 } else if (!strcasecmp(rs, "txclk")) { 323 dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 324 } 325 326 dwmac->speed = SPEED_1000; 327 } 328 329 dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 330 if (IS_ERR(dwmac->clk)) { 331 dev_warn(dev, "No phy clock provided...\n"); 332 dwmac->clk = NULL; 333 } 334 335 return 0; 336 } 337 338 static int sti_dwmac_probe(struct platform_device *pdev) 339 { 340 struct plat_stmmacenet_data *plat_dat; 341 const struct stmmac_of_data *data; 342 struct stmmac_resources stmmac_res; 343 struct sti_dwmac *dwmac; 344 int ret; 345 346 data = of_device_get_match_data(&pdev->dev); 347 if (!data) { 348 dev_err(&pdev->dev, "No OF match data provided\n"); 349 return -EINVAL; 350 } 351 352 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 353 if (ret) 354 return ret; 355 356 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 357 if (IS_ERR(plat_dat)) 358 return PTR_ERR(plat_dat); 359 360 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 361 if (!dwmac) 362 return -ENOMEM; 363 364 ret = sti_dwmac_parse_data(dwmac, pdev); 365 if (ret) { 366 dev_err(&pdev->dev, "Unable to parse OF data\n"); 367 return ret; 368 } 369 370 plat_dat->bsp_priv = dwmac; 371 plat_dat->init = data->init; 372 plat_dat->exit = sti_dwmac_exit; 373 plat_dat->fix_mac_speed = data->fix_mac_speed; 374 375 ret = plat_dat->init(pdev, plat_dat->bsp_priv); 376 if (ret) 377 return ret; 378 379 return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 380 } 381 382 static const struct stmmac_of_data stih4xx_dwmac_data = { 383 .fix_mac_speed = stih4xx_fix_retime_src, 384 .init = stix4xx_init, 385 }; 386 387 static const struct stmmac_of_data stid127_dwmac_data = { 388 .fix_mac_speed = stid127_fix_retime_src, 389 .init = stid127_init, 390 }; 391 392 static const struct of_device_id sti_dwmac_match[] = { 393 { .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data}, 394 { .compatible = "st,stih416-dwmac", .data = &stih4xx_dwmac_data}, 395 { .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data}, 396 { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, 397 { } 398 }; 399 MODULE_DEVICE_TABLE(of, sti_dwmac_match); 400 401 static struct platform_driver sti_dwmac_driver = { 402 .probe = sti_dwmac_probe, 403 .remove = stmmac_pltfr_remove, 404 .driver = { 405 .name = "sti-dwmac", 406 .pm = &stmmac_pltfr_pm_ops, 407 .of_match_table = sti_dwmac_match, 408 }, 409 }; 410 module_platform_driver(sti_dwmac_driver); 411 412 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>"); 413 MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer"); 414 MODULE_LICENSE("GPL"); 415