1732fdf0eSGiuseppe CAVALLARO /* 2d15891caSSrinivas Kandagatla * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 3d15891caSSrinivas Kandagatla * 4d15891caSSrinivas Kandagatla * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 5d15891caSSrinivas Kandagatla * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 653b26b9bSGiuseppe CAVALLARO * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7d15891caSSrinivas Kandagatla * 8d15891caSSrinivas Kandagatla * This program is free software; you can redistribute it and/or modify 9d15891caSSrinivas Kandagatla * it under the terms of the GNU General Public License as published by 10d15891caSSrinivas Kandagatla * the Free Software Foundation; either version 2 of the License, or 11d15891caSSrinivas Kandagatla * (at your option) any later version. 12d15891caSSrinivas Kandagatla */ 13d15891caSSrinivas Kandagatla 14d15891caSSrinivas Kandagatla #include <linux/kernel.h> 15d15891caSSrinivas Kandagatla #include <linux/slab.h> 16d15891caSSrinivas Kandagatla #include <linux/platform_device.h> 17d15891caSSrinivas Kandagatla #include <linux/stmmac.h> 18d15891caSSrinivas Kandagatla #include <linux/phy.h> 19d15891caSSrinivas Kandagatla #include <linux/mfd/syscon.h> 20d15891caSSrinivas Kandagatla #include <linux/regmap.h> 21d15891caSSrinivas Kandagatla #include <linux/clk.h> 22d15891caSSrinivas Kandagatla #include <linux/of.h> 23d15891caSSrinivas Kandagatla #include <linux/of_net.h> 24d15891caSSrinivas Kandagatla 25f10f9fb2SAndy Shevchenko #include "stmmac_platform.h" 26f10f9fb2SAndy Shevchenko 2753b26b9bSGiuseppe CAVALLARO #define DWMAC_125MHZ 125000000 2853b26b9bSGiuseppe CAVALLARO #define DWMAC_50MHZ 50000000 2953b26b9bSGiuseppe CAVALLARO #define DWMAC_25MHZ 25000000 3053b26b9bSGiuseppe CAVALLARO #define DWMAC_2_5MHZ 2500000 3153b26b9bSGiuseppe CAVALLARO 3253b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 3353b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_ID || \ 3453b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 3553b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_TXID) 3653b26b9bSGiuseppe CAVALLARO 3753b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 3853b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_GMII) 3953b26b9bSGiuseppe CAVALLARO 40732fdf0eSGiuseppe CAVALLARO /* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families) 41732fdf0eSGiuseppe CAVALLARO * 42d15891caSSrinivas Kandagatla * Below table summarizes the clock requirement and clock sources for 43d15891caSSrinivas Kandagatla * supported phy interface modes with link speeds. 44d15891caSSrinivas Kandagatla * ________________________________________________ 45d15891caSSrinivas Kandagatla *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 46d15891caSSrinivas Kandagatla * ------------------------------------------------ 47d15891caSSrinivas Kandagatla *| MII | n/a | 25Mhz | 48d15891caSSrinivas Kandagatla *| | | txclk | 49d15891caSSrinivas Kandagatla * ------------------------------------------------ 50d15891caSSrinivas Kandagatla *| GMII | 125Mhz | 25Mhz | 51d15891caSSrinivas Kandagatla *| | clk-125/txclk | txclk | 52d15891caSSrinivas Kandagatla * ------------------------------------------------ 53d15891caSSrinivas Kandagatla *| RGMII | 125Mhz | 25Mhz | 54d15891caSSrinivas Kandagatla *| | clk-125/txclk | clkgen | 5553b26b9bSGiuseppe CAVALLARO *| | clkgen | | 56d15891caSSrinivas Kandagatla * ------------------------------------------------ 57d15891caSSrinivas Kandagatla *| RMII | n/a | 25Mhz | 58d15891caSSrinivas Kandagatla *| | |clkgen/phyclk-in | 59d15891caSSrinivas Kandagatla * ------------------------------------------------ 60d15891caSSrinivas Kandagatla * 6153b26b9bSGiuseppe CAVALLARO * Register Configuration 6253b26b9bSGiuseppe CAVALLARO *------------------------------- 6353b26b9bSGiuseppe CAVALLARO * src |BIT(8)| BIT(7)| BIT(6)| 6453b26b9bSGiuseppe CAVALLARO *------------------------------- 65d15891caSSrinivas Kandagatla * txclk | 0 | n/a | 1 | 6653b26b9bSGiuseppe CAVALLARO *------------------------------- 67d15891caSSrinivas Kandagatla * ck_125| 0 | n/a | 0 | 6853b26b9bSGiuseppe CAVALLARO *------------------------------- 69d15891caSSrinivas Kandagatla * phyclk| 1 | 0 | n/a | 7053b26b9bSGiuseppe CAVALLARO *------------------------------- 71d15891caSSrinivas Kandagatla * clkgen| 1 | 1 | n/a | 7253b26b9bSGiuseppe CAVALLARO *------------------------------- 73d15891caSSrinivas Kandagatla */ 74d15891caSSrinivas Kandagatla 7553b26b9bSGiuseppe CAVALLARO #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 7653b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 7753b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 7853b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 79d15891caSSrinivas Kandagatla 80732fdf0eSGiuseppe CAVALLARO /* STiD127 register definitions 8153b26b9bSGiuseppe CAVALLARO *----------------------- 8253b26b9bSGiuseppe CAVALLARO * src |BIT(6)| BIT(7)| 8353b26b9bSGiuseppe CAVALLARO *----------------------- 8453b26b9bSGiuseppe CAVALLARO * MII | 1 | n/a | 8553b26b9bSGiuseppe CAVALLARO *----------------------- 8653b26b9bSGiuseppe CAVALLARO * RMII | n/a | 1 | 8753b26b9bSGiuseppe CAVALLARO * clkgen| | | 8853b26b9bSGiuseppe CAVALLARO *----------------------- 8953b26b9bSGiuseppe CAVALLARO * RMII | n/a | 0 | 9053b26b9bSGiuseppe CAVALLARO * phyclk| | | 9153b26b9bSGiuseppe CAVALLARO *----------------------- 9253b26b9bSGiuseppe CAVALLARO * RGMII | 1 | n/a | 9353b26b9bSGiuseppe CAVALLARO * clkgen| | | 9453b26b9bSGiuseppe CAVALLARO *----------------------- 95d15891caSSrinivas Kandagatla */ 96d15891caSSrinivas Kandagatla 9753b26b9bSGiuseppe CAVALLARO #define STID127_RETIME_SRC_MASK GENMASK(7, 6) 9853b26b9bSGiuseppe CAVALLARO #define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 9953b26b9bSGiuseppe CAVALLARO #define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) 100d15891caSSrinivas Kandagatla 101d15891caSSrinivas Kandagatla #define ENMII_MASK GENMASK(5, 5) 102d15891caSSrinivas Kandagatla #define ENMII BIT(5) 10353b26b9bSGiuseppe CAVALLARO #define EN_MASK GENMASK(1, 1) 10453b26b9bSGiuseppe CAVALLARO #define EN BIT(1) 105d15891caSSrinivas Kandagatla 106732fdf0eSGiuseppe CAVALLARO /* 107d15891caSSrinivas Kandagatla * 3 bits [4:2] 108d15891caSSrinivas Kandagatla * 000-GMII/MII 109d15891caSSrinivas Kandagatla * 001-RGMII 110d15891caSSrinivas Kandagatla * 010-SGMII 111d15891caSSrinivas Kandagatla * 100-RMII 112d15891caSSrinivas Kandagatla */ 113d15891caSSrinivas Kandagatla #define MII_PHY_SEL_MASK GENMASK(4, 2) 114d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RMII BIT(4) 115d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_SGMII BIT(3) 116d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RGMII BIT(2) 117d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_GMII 0x0 118d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_MII 0x0 119d15891caSSrinivas Kandagatla 120d15891caSSrinivas Kandagatla struct sti_dwmac { 12153b26b9bSGiuseppe CAVALLARO int interface; /* MII interface */ 12253b26b9bSGiuseppe CAVALLARO bool ext_phyclk; /* Clock from external PHY */ 12353b26b9bSGiuseppe CAVALLARO u32 tx_retime_src; /* TXCLK Retiming*/ 12453b26b9bSGiuseppe CAVALLARO struct clk *clk; /* PHY clock */ 12553b26b9bSGiuseppe CAVALLARO int ctrl_reg; /* GMAC glue-logic control register */ 12653b26b9bSGiuseppe CAVALLARO int clk_sel_reg; /* GMAC ext clk selection register */ 127d15891caSSrinivas Kandagatla struct device *dev; 128d15891caSSrinivas Kandagatla struct regmap *regmap; 12953b26b9bSGiuseppe CAVALLARO u32 speed; 130d15891caSSrinivas Kandagatla }; 131d15891caSSrinivas Kandagatla 132d15891caSSrinivas Kandagatla static u32 phy_intf_sels[] = { 133d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 134d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 135d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 136d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 137d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 138d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 139d15891caSSrinivas Kandagatla }; 140d15891caSSrinivas Kandagatla 141d15891caSSrinivas Kandagatla enum { 142d15891caSSrinivas Kandagatla TX_RETIME_SRC_NA = 0, 143d15891caSSrinivas Kandagatla TX_RETIME_SRC_TXCLK = 1, 144d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLK_125, 145d15891caSSrinivas Kandagatla TX_RETIME_SRC_PHYCLK, 146d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLKGEN, 147d15891caSSrinivas Kandagatla }; 148d15891caSSrinivas Kandagatla 14953b26b9bSGiuseppe CAVALLARO static u32 stih4xx_tx_retime_val[] = { 15053b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 151d15891caSSrinivas Kandagatla [TX_RETIME_SRC_CLK_125] = 0x0, 15253b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 15353b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 15453b26b9bSGiuseppe CAVALLARO | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 155d15891caSSrinivas Kandagatla }; 156d15891caSSrinivas Kandagatla 15753b26b9bSGiuseppe CAVALLARO static void stih4xx_fix_retime_src(void *priv, u32 spd) 158d15891caSSrinivas Kandagatla { 15953b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 16053b26b9bSGiuseppe CAVALLARO u32 src = dwmac->tx_retime_src; 16153b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 16253b26b9bSGiuseppe CAVALLARO u32 freq = 0; 163d15891caSSrinivas Kandagatla 16453b26b9bSGiuseppe CAVALLARO if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 165d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_TXCLK; 166d15891caSSrinivas Kandagatla } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 167d15891caSSrinivas Kandagatla if (dwmac->ext_phyclk) { 168d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_PHYCLK; 169d15891caSSrinivas Kandagatla } else { 170d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN; 17153b26b9bSGiuseppe CAVALLARO freq = DWMAC_50MHZ; 172d15891caSSrinivas Kandagatla } 173d15891caSSrinivas Kandagatla } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 17453b26b9bSGiuseppe CAVALLARO /* On GiGa clk source can be either ext or from clkgen */ 17553b26b9bSGiuseppe CAVALLARO if (spd == SPEED_1000) { 17653b26b9bSGiuseppe CAVALLARO freq = DWMAC_125MHZ; 17753b26b9bSGiuseppe CAVALLARO } else { 17853b26b9bSGiuseppe CAVALLARO /* Switch to clkgen for these speeds */ 179d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN; 18053b26b9bSGiuseppe CAVALLARO if (spd == SPEED_100) 18153b26b9bSGiuseppe CAVALLARO freq = DWMAC_25MHZ; 18253b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_10) 18353b26b9bSGiuseppe CAVALLARO freq = DWMAC_2_5MHZ; 18453b26b9bSGiuseppe CAVALLARO } 185d15891caSSrinivas Kandagatla } 186d15891caSSrinivas Kandagatla 18753b26b9bSGiuseppe CAVALLARO if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk && freq) 188d15891caSSrinivas Kandagatla clk_set_rate(dwmac->clk, freq); 189d15891caSSrinivas Kandagatla 19053b26b9bSGiuseppe CAVALLARO regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 19153b26b9bSGiuseppe CAVALLARO stih4xx_tx_retime_val[src]); 192d15891caSSrinivas Kandagatla } 193d15891caSSrinivas Kandagatla 19453b26b9bSGiuseppe CAVALLARO static void stid127_fix_retime_src(void *priv, u32 spd) 19553b26b9bSGiuseppe CAVALLARO { 19653b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 19753b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 19853b26b9bSGiuseppe CAVALLARO u32 freq = 0; 19953b26b9bSGiuseppe CAVALLARO u32 val = 0; 20053b26b9bSGiuseppe CAVALLARO 20153b26b9bSGiuseppe CAVALLARO if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 20253b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 20353b26b9bSGiuseppe CAVALLARO } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 20453b26b9bSGiuseppe CAVALLARO if (!dwmac->ext_phyclk) { 20553b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; 20653b26b9bSGiuseppe CAVALLARO freq = DWMAC_50MHZ; 20753b26b9bSGiuseppe CAVALLARO } 20853b26b9bSGiuseppe CAVALLARO } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 20953b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 21053b26b9bSGiuseppe CAVALLARO if (spd == SPEED_1000) 21153b26b9bSGiuseppe CAVALLARO freq = DWMAC_125MHZ; 21253b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_100) 21353b26b9bSGiuseppe CAVALLARO freq = DWMAC_25MHZ; 21453b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_10) 21553b26b9bSGiuseppe CAVALLARO freq = DWMAC_2_5MHZ; 21653b26b9bSGiuseppe CAVALLARO } 21753b26b9bSGiuseppe CAVALLARO 21853b26b9bSGiuseppe CAVALLARO if (dwmac->clk && freq) 21953b26b9bSGiuseppe CAVALLARO clk_set_rate(dwmac->clk, freq); 22053b26b9bSGiuseppe CAVALLARO 22153b26b9bSGiuseppe CAVALLARO regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); 22253b26b9bSGiuseppe CAVALLARO } 22353b26b9bSGiuseppe CAVALLARO 22453b26b9bSGiuseppe CAVALLARO static void sti_dwmac_ctrl_init(struct sti_dwmac *dwmac) 22553b26b9bSGiuseppe CAVALLARO { 22653b26b9bSGiuseppe CAVALLARO struct regmap *regmap = dwmac->regmap; 22753b26b9bSGiuseppe CAVALLARO int iface = dwmac->interface; 22853b26b9bSGiuseppe CAVALLARO struct device *dev = dwmac->dev; 22953b26b9bSGiuseppe CAVALLARO struct device_node *np = dev->of_node; 23053b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 23153b26b9bSGiuseppe CAVALLARO u32 val; 23253b26b9bSGiuseppe CAVALLARO 23353b26b9bSGiuseppe CAVALLARO if (dwmac->clk) 23453b26b9bSGiuseppe CAVALLARO clk_prepare_enable(dwmac->clk); 23553b26b9bSGiuseppe CAVALLARO 23653b26b9bSGiuseppe CAVALLARO if (of_property_read_bool(np, "st,gmac_en")) 23753b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, EN_MASK, EN); 23853b26b9bSGiuseppe CAVALLARO 23953b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 24053b26b9bSGiuseppe CAVALLARO 24153b26b9bSGiuseppe CAVALLARO val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 24253b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, ENMII_MASK, val); 24353b26b9bSGiuseppe CAVALLARO } 24453b26b9bSGiuseppe CAVALLARO 24553b26b9bSGiuseppe CAVALLARO static int stix4xx_init(struct platform_device *pdev, void *priv) 24653b26b9bSGiuseppe CAVALLARO { 24753b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 24853b26b9bSGiuseppe CAVALLARO u32 spd = dwmac->speed; 24953b26b9bSGiuseppe CAVALLARO 25053b26b9bSGiuseppe CAVALLARO sti_dwmac_ctrl_init(dwmac); 25153b26b9bSGiuseppe CAVALLARO 25253b26b9bSGiuseppe CAVALLARO stih4xx_fix_retime_src(priv, spd); 25353b26b9bSGiuseppe CAVALLARO 25453b26b9bSGiuseppe CAVALLARO return 0; 25553b26b9bSGiuseppe CAVALLARO } 25653b26b9bSGiuseppe CAVALLARO 25753b26b9bSGiuseppe CAVALLARO static int stid127_init(struct platform_device *pdev, void *priv) 25853b26b9bSGiuseppe CAVALLARO { 25953b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 26053b26b9bSGiuseppe CAVALLARO u32 spd = dwmac->speed; 26153b26b9bSGiuseppe CAVALLARO 26253b26b9bSGiuseppe CAVALLARO sti_dwmac_ctrl_init(dwmac); 26353b26b9bSGiuseppe CAVALLARO 26453b26b9bSGiuseppe CAVALLARO stid127_fix_retime_src(priv, spd); 26553b26b9bSGiuseppe CAVALLARO 26653b26b9bSGiuseppe CAVALLARO return 0; 267d15891caSSrinivas Kandagatla } 268d15891caSSrinivas Kandagatla 269d15891caSSrinivas Kandagatla static void sti_dwmac_exit(struct platform_device *pdev, void *priv) 270d15891caSSrinivas Kandagatla { 271d15891caSSrinivas Kandagatla struct sti_dwmac *dwmac = priv; 272d15891caSSrinivas Kandagatla 273d15891caSSrinivas Kandagatla if (dwmac->clk) 274d15891caSSrinivas Kandagatla clk_disable_unprepare(dwmac->clk); 275d15891caSSrinivas Kandagatla } 276d15891caSSrinivas Kandagatla static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 277d15891caSSrinivas Kandagatla struct platform_device *pdev) 278d15891caSSrinivas Kandagatla { 279d15891caSSrinivas Kandagatla struct resource *res; 280d15891caSSrinivas Kandagatla struct device *dev = &pdev->dev; 281d15891caSSrinivas Kandagatla struct device_node *np = dev->of_node; 282d15891caSSrinivas Kandagatla struct regmap *regmap; 283d15891caSSrinivas Kandagatla int err; 284d15891caSSrinivas Kandagatla 285d15891caSSrinivas Kandagatla if (!np) 286d15891caSSrinivas Kandagatla return -EINVAL; 287d15891caSSrinivas Kandagatla 288d15891caSSrinivas Kandagatla res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-ethconf"); 289d15891caSSrinivas Kandagatla if (!res) 290d15891caSSrinivas Kandagatla return -ENODATA; 29153b26b9bSGiuseppe CAVALLARO dwmac->ctrl_reg = res->start; 29253b26b9bSGiuseppe CAVALLARO 29353b26b9bSGiuseppe CAVALLARO /* clk selection from extra syscfg register */ 29453b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = -ENXIO; 29553b26b9bSGiuseppe CAVALLARO res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 29653b26b9bSGiuseppe CAVALLARO if (res) 29753b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = res->start; 298d15891caSSrinivas Kandagatla 299d15891caSSrinivas Kandagatla regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 300d15891caSSrinivas Kandagatla if (IS_ERR(regmap)) 301d15891caSSrinivas Kandagatla return PTR_ERR(regmap); 302d15891caSSrinivas Kandagatla 303d15891caSSrinivas Kandagatla dwmac->dev = dev; 304d15891caSSrinivas Kandagatla dwmac->interface = of_get_phy_mode(np); 305d15891caSSrinivas Kandagatla dwmac->regmap = regmap; 306d15891caSSrinivas Kandagatla dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 30753b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_NA; 30853b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_100; 309d15891caSSrinivas Kandagatla 310d15891caSSrinivas Kandagatla if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 311d15891caSSrinivas Kandagatla const char *rs; 312d15891caSSrinivas Kandagatla 313d15891caSSrinivas Kandagatla err = of_property_read_string(np, "st,tx-retime-src", &rs); 31450262c85SGeert Uytterhoeven if (err < 0) { 31553b26b9bSGiuseppe CAVALLARO dev_warn(dev, "Use internal clock source\n"); 31650262c85SGeert Uytterhoeven dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 31750262c85SGeert Uytterhoeven } else if (!strcasecmp(rs, "clk_125")) { 31853b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 31950262c85SGeert Uytterhoeven } else if (!strcasecmp(rs, "txclk")) { 32053b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 32150262c85SGeert Uytterhoeven } 32253b26b9bSGiuseppe CAVALLARO 32353b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_1000; 324d15891caSSrinivas Kandagatla } 325d15891caSSrinivas Kandagatla 326d15891caSSrinivas Kandagatla dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 32753b26b9bSGiuseppe CAVALLARO if (IS_ERR(dwmac->clk)) { 32853b26b9bSGiuseppe CAVALLARO dev_warn(dev, "No phy clock provided...\n"); 329d15891caSSrinivas Kandagatla dwmac->clk = NULL; 330d15891caSSrinivas Kandagatla } 331d15891caSSrinivas Kandagatla 332d15891caSSrinivas Kandagatla return 0; 333d15891caSSrinivas Kandagatla } 334d15891caSSrinivas Kandagatla 335d15891caSSrinivas Kandagatla static void *sti_dwmac_setup(struct platform_device *pdev) 336d15891caSSrinivas Kandagatla { 337d15891caSSrinivas Kandagatla struct sti_dwmac *dwmac; 338d15891caSSrinivas Kandagatla int ret; 339d15891caSSrinivas Kandagatla 340d15891caSSrinivas Kandagatla dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 341d15891caSSrinivas Kandagatla if (!dwmac) 342d15891caSSrinivas Kandagatla return ERR_PTR(-ENOMEM); 343d15891caSSrinivas Kandagatla 344d15891caSSrinivas Kandagatla ret = sti_dwmac_parse_data(dwmac, pdev); 345d15891caSSrinivas Kandagatla if (ret) { 346d15891caSSrinivas Kandagatla dev_err(&pdev->dev, "Unable to parse OF data\n"); 347d15891caSSrinivas Kandagatla return ERR_PTR(ret); 348d15891caSSrinivas Kandagatla } 349d15891caSSrinivas Kandagatla 350d15891caSSrinivas Kandagatla return dwmac; 351d15891caSSrinivas Kandagatla } 352d15891caSSrinivas Kandagatla 35353b26b9bSGiuseppe CAVALLARO const struct stmmac_of_data stih4xx_dwmac_data = { 35453b26b9bSGiuseppe CAVALLARO .fix_mac_speed = stih4xx_fix_retime_src, 355d15891caSSrinivas Kandagatla .setup = sti_dwmac_setup, 35653b26b9bSGiuseppe CAVALLARO .init = stix4xx_init, 35753b26b9bSGiuseppe CAVALLARO .exit = sti_dwmac_exit, 35853b26b9bSGiuseppe CAVALLARO }; 35953b26b9bSGiuseppe CAVALLARO 36053b26b9bSGiuseppe CAVALLARO const struct stmmac_of_data stid127_dwmac_data = { 36153b26b9bSGiuseppe CAVALLARO .fix_mac_speed = stid127_fix_retime_src, 36253b26b9bSGiuseppe CAVALLARO .setup = sti_dwmac_setup, 36353b26b9bSGiuseppe CAVALLARO .init = stid127_init, 364d15891caSSrinivas Kandagatla .exit = sti_dwmac_exit, 365d15891caSSrinivas Kandagatla }; 366