12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2732fdf0eSGiuseppe CAVALLARO /* 3d15891caSSrinivas Kandagatla * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 4d15891caSSrinivas Kandagatla * 5d15891caSSrinivas Kandagatla * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 6d15891caSSrinivas Kandagatla * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 753b26b9bSGiuseppe CAVALLARO * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 8d15891caSSrinivas Kandagatla */ 9d15891caSSrinivas Kandagatla 10d15891caSSrinivas Kandagatla #include <linux/kernel.h> 11d15891caSSrinivas Kandagatla #include <linux/slab.h> 12d15891caSSrinivas Kandagatla #include <linux/platform_device.h> 13d15891caSSrinivas Kandagatla #include <linux/stmmac.h> 14d15891caSSrinivas Kandagatla #include <linux/phy.h> 15d15891caSSrinivas Kandagatla #include <linux/mfd/syscon.h> 162a321798SJoachim Eastwood #include <linux/module.h> 17d15891caSSrinivas Kandagatla #include <linux/regmap.h> 18d15891caSSrinivas Kandagatla #include <linux/clk.h> 19d15891caSSrinivas Kandagatla #include <linux/of.h> 20149adeddSJoachim Eastwood #include <linux/of_device.h> 21d15891caSSrinivas Kandagatla #include <linux/of_net.h> 22d15891caSSrinivas Kandagatla 23f10f9fb2SAndy Shevchenko #include "stmmac_platform.h" 24f10f9fb2SAndy Shevchenko 2553b26b9bSGiuseppe CAVALLARO #define DWMAC_125MHZ 125000000 2653b26b9bSGiuseppe CAVALLARO #define DWMAC_50MHZ 50000000 2753b26b9bSGiuseppe CAVALLARO #define DWMAC_25MHZ 25000000 2853b26b9bSGiuseppe CAVALLARO #define DWMAC_2_5MHZ 2500000 2953b26b9bSGiuseppe CAVALLARO 3053b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 3153b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_ID || \ 3253b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 3353b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_TXID) 3453b26b9bSGiuseppe CAVALLARO 3553b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 3653b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_GMII) 3753b26b9bSGiuseppe CAVALLARO 38732fdf0eSGiuseppe CAVALLARO /* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families) 39732fdf0eSGiuseppe CAVALLARO * 40d15891caSSrinivas Kandagatla * Below table summarizes the clock requirement and clock sources for 41d15891caSSrinivas Kandagatla * supported phy interface modes with link speeds. 42d15891caSSrinivas Kandagatla * ________________________________________________ 43d15891caSSrinivas Kandagatla *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 44d15891caSSrinivas Kandagatla * ------------------------------------------------ 45d15891caSSrinivas Kandagatla *| MII | n/a | 25Mhz | 46d15891caSSrinivas Kandagatla *| | | txclk | 47d15891caSSrinivas Kandagatla * ------------------------------------------------ 48d15891caSSrinivas Kandagatla *| GMII | 125Mhz | 25Mhz | 49d15891caSSrinivas Kandagatla *| | clk-125/txclk | txclk | 50d15891caSSrinivas Kandagatla * ------------------------------------------------ 51d15891caSSrinivas Kandagatla *| RGMII | 125Mhz | 25Mhz | 52d15891caSSrinivas Kandagatla *| | clk-125/txclk | clkgen | 5353b26b9bSGiuseppe CAVALLARO *| | clkgen | | 54d15891caSSrinivas Kandagatla * ------------------------------------------------ 55d15891caSSrinivas Kandagatla *| RMII | n/a | 25Mhz | 56d15891caSSrinivas Kandagatla *| | |clkgen/phyclk-in | 57d15891caSSrinivas Kandagatla * ------------------------------------------------ 58d15891caSSrinivas Kandagatla * 5953b26b9bSGiuseppe CAVALLARO * Register Configuration 6053b26b9bSGiuseppe CAVALLARO *------------------------------- 6153b26b9bSGiuseppe CAVALLARO * src |BIT(8)| BIT(7)| BIT(6)| 6253b26b9bSGiuseppe CAVALLARO *------------------------------- 63d15891caSSrinivas Kandagatla * txclk | 0 | n/a | 1 | 6453b26b9bSGiuseppe CAVALLARO *------------------------------- 65d15891caSSrinivas Kandagatla * ck_125| 0 | n/a | 0 | 6653b26b9bSGiuseppe CAVALLARO *------------------------------- 67d15891caSSrinivas Kandagatla * phyclk| 1 | 0 | n/a | 6853b26b9bSGiuseppe CAVALLARO *------------------------------- 69d15891caSSrinivas Kandagatla * clkgen| 1 | 1 | n/a | 7053b26b9bSGiuseppe CAVALLARO *------------------------------- 71d15891caSSrinivas Kandagatla */ 72d15891caSSrinivas Kandagatla 7353b26b9bSGiuseppe CAVALLARO #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 7453b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 7553b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 7653b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 77d15891caSSrinivas Kandagatla 78732fdf0eSGiuseppe CAVALLARO /* STiD127 register definitions 7953b26b9bSGiuseppe CAVALLARO *----------------------- 8053b26b9bSGiuseppe CAVALLARO * src |BIT(6)| BIT(7)| 8153b26b9bSGiuseppe CAVALLARO *----------------------- 8253b26b9bSGiuseppe CAVALLARO * MII | 1 | n/a | 8353b26b9bSGiuseppe CAVALLARO *----------------------- 8453b26b9bSGiuseppe CAVALLARO * RMII | n/a | 1 | 8553b26b9bSGiuseppe CAVALLARO * clkgen| | | 8653b26b9bSGiuseppe CAVALLARO *----------------------- 8753b26b9bSGiuseppe CAVALLARO * RMII | n/a | 0 | 8853b26b9bSGiuseppe CAVALLARO * phyclk| | | 8953b26b9bSGiuseppe CAVALLARO *----------------------- 9053b26b9bSGiuseppe CAVALLARO * RGMII | 1 | n/a | 9153b26b9bSGiuseppe CAVALLARO * clkgen| | | 9253b26b9bSGiuseppe CAVALLARO *----------------------- 93d15891caSSrinivas Kandagatla */ 94d15891caSSrinivas Kandagatla 9553b26b9bSGiuseppe CAVALLARO #define STID127_RETIME_SRC_MASK GENMASK(7, 6) 9653b26b9bSGiuseppe CAVALLARO #define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 9753b26b9bSGiuseppe CAVALLARO #define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) 98d15891caSSrinivas Kandagatla 99d15891caSSrinivas Kandagatla #define ENMII_MASK GENMASK(5, 5) 100d15891caSSrinivas Kandagatla #define ENMII BIT(5) 10153b26b9bSGiuseppe CAVALLARO #define EN_MASK GENMASK(1, 1) 10253b26b9bSGiuseppe CAVALLARO #define EN BIT(1) 103d15891caSSrinivas Kandagatla 104732fdf0eSGiuseppe CAVALLARO /* 105d15891caSSrinivas Kandagatla * 3 bits [4:2] 106d15891caSSrinivas Kandagatla * 000-GMII/MII 107d15891caSSrinivas Kandagatla * 001-RGMII 108d15891caSSrinivas Kandagatla * 010-SGMII 109d15891caSSrinivas Kandagatla * 100-RMII 110d15891caSSrinivas Kandagatla */ 111d15891caSSrinivas Kandagatla #define MII_PHY_SEL_MASK GENMASK(4, 2) 112d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RMII BIT(4) 113d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_SGMII BIT(3) 114d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RGMII BIT(2) 115d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_GMII 0x0 116d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_MII 0x0 117d15891caSSrinivas Kandagatla 118d15891caSSrinivas Kandagatla struct sti_dwmac { 11953b26b9bSGiuseppe CAVALLARO int interface; /* MII interface */ 12053b26b9bSGiuseppe CAVALLARO bool ext_phyclk; /* Clock from external PHY */ 12153b26b9bSGiuseppe CAVALLARO u32 tx_retime_src; /* TXCLK Retiming*/ 12253b26b9bSGiuseppe CAVALLARO struct clk *clk; /* PHY clock */ 1239b1a6d36SPeter Griffin u32 ctrl_reg; /* GMAC glue-logic control register */ 12453b26b9bSGiuseppe CAVALLARO int clk_sel_reg; /* GMAC ext clk selection register */ 125d15891caSSrinivas Kandagatla struct regmap *regmap; 12606a6e829SJoachim Eastwood bool gmac_en; 12753b26b9bSGiuseppe CAVALLARO u32 speed; 12816b1adbbSJoachim Eastwood void (*fix_retime_src)(void *priv, unsigned int speed); 129d15891caSSrinivas Kandagatla }; 130d15891caSSrinivas Kandagatla 13107ca3749SJoachim Eastwood struct sti_dwmac_of_data { 13216b1adbbSJoachim Eastwood void (*fix_retime_src)(void *priv, unsigned int speed); 13307ca3749SJoachim Eastwood }; 13407ca3749SJoachim Eastwood 135d15891caSSrinivas Kandagatla static u32 phy_intf_sels[] = { 136d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 137d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 138d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 139d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 140d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 141d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 142d15891caSSrinivas Kandagatla }; 143d15891caSSrinivas Kandagatla 144d15891caSSrinivas Kandagatla enum { 145d15891caSSrinivas Kandagatla TX_RETIME_SRC_NA = 0, 146d15891caSSrinivas Kandagatla TX_RETIME_SRC_TXCLK = 1, 147d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLK_125, 148d15891caSSrinivas Kandagatla TX_RETIME_SRC_PHYCLK, 149d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLKGEN, 150d15891caSSrinivas Kandagatla }; 151d15891caSSrinivas Kandagatla 15253b26b9bSGiuseppe CAVALLARO static u32 stih4xx_tx_retime_val[] = { 15353b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 154d15891caSSrinivas Kandagatla [TX_RETIME_SRC_CLK_125] = 0x0, 15553b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 15653b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 15753b26b9bSGiuseppe CAVALLARO | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 158d15891caSSrinivas Kandagatla }; 159d15891caSSrinivas Kandagatla 16053b26b9bSGiuseppe CAVALLARO static void stih4xx_fix_retime_src(void *priv, u32 spd) 161d15891caSSrinivas Kandagatla { 16253b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 16353b26b9bSGiuseppe CAVALLARO u32 src = dwmac->tx_retime_src; 16453b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 16553b26b9bSGiuseppe CAVALLARO u32 freq = 0; 166d15891caSSrinivas Kandagatla 16753b26b9bSGiuseppe CAVALLARO if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 168d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_TXCLK; 169d15891caSSrinivas Kandagatla } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 170d15891caSSrinivas Kandagatla if (dwmac->ext_phyclk) { 171d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_PHYCLK; 172d15891caSSrinivas Kandagatla } else { 173d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN; 17453b26b9bSGiuseppe CAVALLARO freq = DWMAC_50MHZ; 175d15891caSSrinivas Kandagatla } 176d15891caSSrinivas Kandagatla } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 17753b26b9bSGiuseppe CAVALLARO /* On GiGa clk source can be either ext or from clkgen */ 17853b26b9bSGiuseppe CAVALLARO if (spd == SPEED_1000) { 17953b26b9bSGiuseppe CAVALLARO freq = DWMAC_125MHZ; 18053b26b9bSGiuseppe CAVALLARO } else { 18153b26b9bSGiuseppe CAVALLARO /* Switch to clkgen for these speeds */ 182d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN; 18353b26b9bSGiuseppe CAVALLARO if (spd == SPEED_100) 18453b26b9bSGiuseppe CAVALLARO freq = DWMAC_25MHZ; 18553b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_10) 18653b26b9bSGiuseppe CAVALLARO freq = DWMAC_2_5MHZ; 18753b26b9bSGiuseppe CAVALLARO } 188d15891caSSrinivas Kandagatla } 189d15891caSSrinivas Kandagatla 190b211aa65SJoachim Eastwood if (src == TX_RETIME_SRC_CLKGEN && freq) 191d15891caSSrinivas Kandagatla clk_set_rate(dwmac->clk, freq); 192d15891caSSrinivas Kandagatla 19353b26b9bSGiuseppe CAVALLARO regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 19453b26b9bSGiuseppe CAVALLARO stih4xx_tx_retime_val[src]); 195d15891caSSrinivas Kandagatla } 196d15891caSSrinivas Kandagatla 19753b26b9bSGiuseppe CAVALLARO static void stid127_fix_retime_src(void *priv, u32 spd) 19853b26b9bSGiuseppe CAVALLARO { 19953b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 20053b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 20153b26b9bSGiuseppe CAVALLARO u32 freq = 0; 20253b26b9bSGiuseppe CAVALLARO u32 val = 0; 20353b26b9bSGiuseppe CAVALLARO 20453b26b9bSGiuseppe CAVALLARO if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 20553b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 20653b26b9bSGiuseppe CAVALLARO } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 20753b26b9bSGiuseppe CAVALLARO if (!dwmac->ext_phyclk) { 20853b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; 20953b26b9bSGiuseppe CAVALLARO freq = DWMAC_50MHZ; 21053b26b9bSGiuseppe CAVALLARO } 21153b26b9bSGiuseppe CAVALLARO } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 21253b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 21353b26b9bSGiuseppe CAVALLARO if (spd == SPEED_1000) 21453b26b9bSGiuseppe CAVALLARO freq = DWMAC_125MHZ; 21553b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_100) 21653b26b9bSGiuseppe CAVALLARO freq = DWMAC_25MHZ; 21753b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_10) 21853b26b9bSGiuseppe CAVALLARO freq = DWMAC_2_5MHZ; 21953b26b9bSGiuseppe CAVALLARO } 22053b26b9bSGiuseppe CAVALLARO 221b211aa65SJoachim Eastwood if (freq) 22253b26b9bSGiuseppe CAVALLARO clk_set_rate(dwmac->clk, freq); 22353b26b9bSGiuseppe CAVALLARO 22453b26b9bSGiuseppe CAVALLARO regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); 22553b26b9bSGiuseppe CAVALLARO } 22653b26b9bSGiuseppe CAVALLARO 2270eebedc2SJoachim Eastwood static int sti_dwmac_set_mode(struct sti_dwmac *dwmac) 22853b26b9bSGiuseppe CAVALLARO { 22953b26b9bSGiuseppe CAVALLARO struct regmap *regmap = dwmac->regmap; 23053b26b9bSGiuseppe CAVALLARO int iface = dwmac->interface; 23153b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 23253b26b9bSGiuseppe CAVALLARO u32 val; 23353b26b9bSGiuseppe CAVALLARO 23406a6e829SJoachim Eastwood if (dwmac->gmac_en) 23553b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, EN_MASK, EN); 23653b26b9bSGiuseppe CAVALLARO 23753b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 23853b26b9bSGiuseppe CAVALLARO 23953b26b9bSGiuseppe CAVALLARO val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 24053b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, ENMII_MASK, val); 24153b26b9bSGiuseppe CAVALLARO 2420eebedc2SJoachim Eastwood dwmac->fix_retime_src(dwmac, dwmac->speed); 24353b26b9bSGiuseppe CAVALLARO 24453b26b9bSGiuseppe CAVALLARO return 0; 245d15891caSSrinivas Kandagatla } 246d15891caSSrinivas Kandagatla 247d15891caSSrinivas Kandagatla static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 248d15891caSSrinivas Kandagatla struct platform_device *pdev) 249d15891caSSrinivas Kandagatla { 250d15891caSSrinivas Kandagatla struct resource *res; 251d15891caSSrinivas Kandagatla struct device *dev = &pdev->dev; 252d15891caSSrinivas Kandagatla struct device_node *np = dev->of_node; 253d15891caSSrinivas Kandagatla struct regmap *regmap; 254d15891caSSrinivas Kandagatla int err; 255d15891caSSrinivas Kandagatla 25653b26b9bSGiuseppe CAVALLARO /* clk selection from extra syscfg register */ 25753b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = -ENXIO; 25853b26b9bSGiuseppe CAVALLARO res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 25953b26b9bSGiuseppe CAVALLARO if (res) 26053b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = res->start; 261d15891caSSrinivas Kandagatla 262d15891caSSrinivas Kandagatla regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 263d15891caSSrinivas Kandagatla if (IS_ERR(regmap)) 264d15891caSSrinivas Kandagatla return PTR_ERR(regmap); 265d15891caSSrinivas Kandagatla 2669b1a6d36SPeter Griffin err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg); 2679b1a6d36SPeter Griffin if (err) { 2689b1a6d36SPeter Griffin dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err); 2699b1a6d36SPeter Griffin return err; 2709b1a6d36SPeter Griffin } 2719b1a6d36SPeter Griffin 272d15891caSSrinivas Kandagatla dwmac->interface = of_get_phy_mode(np); 273d15891caSSrinivas Kandagatla dwmac->regmap = regmap; 27406a6e829SJoachim Eastwood dwmac->gmac_en = of_property_read_bool(np, "st,gmac_en"); 275d15891caSSrinivas Kandagatla dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 27653b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_NA; 27753b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_100; 278d15891caSSrinivas Kandagatla 279d15891caSSrinivas Kandagatla if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 280d15891caSSrinivas Kandagatla const char *rs; 281d15891caSSrinivas Kandagatla 28222407e13SGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 28322407e13SGiuseppe CAVALLARO 284d15891caSSrinivas Kandagatla err = of_property_read_string(np, "st,tx-retime-src", &rs); 28550262c85SGeert Uytterhoeven if (err < 0) { 28653b26b9bSGiuseppe CAVALLARO dev_warn(dev, "Use internal clock source\n"); 28722407e13SGiuseppe CAVALLARO } else { 28822407e13SGiuseppe CAVALLARO if (!strcasecmp(rs, "clk_125")) 28953b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 29022407e13SGiuseppe CAVALLARO else if (!strcasecmp(rs, "txclk")) 29153b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 29250262c85SGeert Uytterhoeven } 29353b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_1000; 294d15891caSSrinivas Kandagatla } 295d15891caSSrinivas Kandagatla 296d15891caSSrinivas Kandagatla dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 29753b26b9bSGiuseppe CAVALLARO if (IS_ERR(dwmac->clk)) { 29853b26b9bSGiuseppe CAVALLARO dev_warn(dev, "No phy clock provided...\n"); 299d15891caSSrinivas Kandagatla dwmac->clk = NULL; 300d15891caSSrinivas Kandagatla } 301d15891caSSrinivas Kandagatla 302d15891caSSrinivas Kandagatla return 0; 303d15891caSSrinivas Kandagatla } 304d15891caSSrinivas Kandagatla 3058387ee21SJoachim Eastwood static int sti_dwmac_probe(struct platform_device *pdev) 306d15891caSSrinivas Kandagatla { 3078387ee21SJoachim Eastwood struct plat_stmmacenet_data *plat_dat; 30807ca3749SJoachim Eastwood const struct sti_dwmac_of_data *data; 3098387ee21SJoachim Eastwood struct stmmac_resources stmmac_res; 310d15891caSSrinivas Kandagatla struct sti_dwmac *dwmac; 311d15891caSSrinivas Kandagatla int ret; 312d15891caSSrinivas Kandagatla 313149adeddSJoachim Eastwood data = of_device_get_match_data(&pdev->dev); 314149adeddSJoachim Eastwood if (!data) { 315149adeddSJoachim Eastwood dev_err(&pdev->dev, "No OF match data provided\n"); 316149adeddSJoachim Eastwood return -EINVAL; 317149adeddSJoachim Eastwood } 318149adeddSJoachim Eastwood 3198387ee21SJoachim Eastwood ret = stmmac_get_platform_resources(pdev, &stmmac_res); 3208387ee21SJoachim Eastwood if (ret) 3218387ee21SJoachim Eastwood return ret; 3228387ee21SJoachim Eastwood 3238387ee21SJoachim Eastwood plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 3248387ee21SJoachim Eastwood if (IS_ERR(plat_dat)) 3258387ee21SJoachim Eastwood return PTR_ERR(plat_dat); 3268387ee21SJoachim Eastwood 327d15891caSSrinivas Kandagatla dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 328d2ed0a77SJohan Hovold if (!dwmac) { 329d2ed0a77SJohan Hovold ret = -ENOMEM; 330d2ed0a77SJohan Hovold goto err_remove_config_dt; 331d2ed0a77SJohan Hovold } 332d15891caSSrinivas Kandagatla 333d15891caSSrinivas Kandagatla ret = sti_dwmac_parse_data(dwmac, pdev); 334d15891caSSrinivas Kandagatla if (ret) { 335d15891caSSrinivas Kandagatla dev_err(&pdev->dev, "Unable to parse OF data\n"); 336d2ed0a77SJohan Hovold goto err_remove_config_dt; 337d15891caSSrinivas Kandagatla } 338d15891caSSrinivas Kandagatla 33916b1adbbSJoachim Eastwood dwmac->fix_retime_src = data->fix_retime_src; 3408387ee21SJoachim Eastwood 34116b1adbbSJoachim Eastwood plat_dat->bsp_priv = dwmac; 34216b1adbbSJoachim Eastwood plat_dat->fix_mac_speed = data->fix_retime_src; 34316b1adbbSJoachim Eastwood 344b89cbfb0SJoachim Eastwood ret = clk_prepare_enable(dwmac->clk); 3458387ee21SJoachim Eastwood if (ret) 346d2ed0a77SJohan Hovold goto err_remove_config_dt; 3478387ee21SJoachim Eastwood 3480eebedc2SJoachim Eastwood ret = sti_dwmac_set_mode(dwmac); 349b89cbfb0SJoachim Eastwood if (ret) 350b89cbfb0SJoachim Eastwood goto disable_clk; 351b89cbfb0SJoachim Eastwood 352b89cbfb0SJoachim Eastwood ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 353b89cbfb0SJoachim Eastwood if (ret) 354b89cbfb0SJoachim Eastwood goto disable_clk; 355b89cbfb0SJoachim Eastwood 356b89cbfb0SJoachim Eastwood return 0; 357b89cbfb0SJoachim Eastwood 358b89cbfb0SJoachim Eastwood disable_clk: 359b89cbfb0SJoachim Eastwood clk_disable_unprepare(dwmac->clk); 360d2ed0a77SJohan Hovold err_remove_config_dt: 361d2ed0a77SJohan Hovold stmmac_remove_config_dt(pdev, plat_dat); 3620a9e2271SJohan Hovold 363b89cbfb0SJoachim Eastwood return ret; 364d15891caSSrinivas Kandagatla } 365d15891caSSrinivas Kandagatla 3662517cfd4SJoachim Eastwood static int sti_dwmac_remove(struct platform_device *pdev) 3672517cfd4SJoachim Eastwood { 3682517cfd4SJoachim Eastwood struct sti_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev); 3692517cfd4SJoachim Eastwood int ret = stmmac_dvr_remove(&pdev->dev); 3702517cfd4SJoachim Eastwood 3712517cfd4SJoachim Eastwood clk_disable_unprepare(dwmac->clk); 3722517cfd4SJoachim Eastwood 3732517cfd4SJoachim Eastwood return ret; 3742517cfd4SJoachim Eastwood } 3752517cfd4SJoachim Eastwood 3762517cfd4SJoachim Eastwood #ifdef CONFIG_PM_SLEEP 3772517cfd4SJoachim Eastwood static int sti_dwmac_suspend(struct device *dev) 3782517cfd4SJoachim Eastwood { 3792517cfd4SJoachim Eastwood struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev); 3802517cfd4SJoachim Eastwood int ret = stmmac_suspend(dev); 3812517cfd4SJoachim Eastwood 3822517cfd4SJoachim Eastwood clk_disable_unprepare(dwmac->clk); 3832517cfd4SJoachim Eastwood 3842517cfd4SJoachim Eastwood return ret; 3852517cfd4SJoachim Eastwood } 3862517cfd4SJoachim Eastwood 3872517cfd4SJoachim Eastwood static int sti_dwmac_resume(struct device *dev) 3882517cfd4SJoachim Eastwood { 3892517cfd4SJoachim Eastwood struct sti_dwmac *dwmac = get_stmmac_bsp_priv(dev); 3902517cfd4SJoachim Eastwood 391b89cbfb0SJoachim Eastwood clk_prepare_enable(dwmac->clk); 3920eebedc2SJoachim Eastwood sti_dwmac_set_mode(dwmac); 3932517cfd4SJoachim Eastwood 3942517cfd4SJoachim Eastwood return stmmac_resume(dev); 3952517cfd4SJoachim Eastwood } 3962517cfd4SJoachim Eastwood #endif /* CONFIG_PM_SLEEP */ 3972517cfd4SJoachim Eastwood 3982517cfd4SJoachim Eastwood static SIMPLE_DEV_PM_OPS(sti_dwmac_pm_ops, sti_dwmac_suspend, 3992517cfd4SJoachim Eastwood sti_dwmac_resume); 4002517cfd4SJoachim Eastwood 40107ca3749SJoachim Eastwood static const struct sti_dwmac_of_data stih4xx_dwmac_data = { 40216b1adbbSJoachim Eastwood .fix_retime_src = stih4xx_fix_retime_src, 40353b26b9bSGiuseppe CAVALLARO }; 40453b26b9bSGiuseppe CAVALLARO 40507ca3749SJoachim Eastwood static const struct sti_dwmac_of_data stid127_dwmac_data = { 40616b1adbbSJoachim Eastwood .fix_retime_src = stid127_fix_retime_src, 407d15891caSSrinivas Kandagatla }; 4082a321798SJoachim Eastwood 4092a321798SJoachim Eastwood static const struct of_device_id sti_dwmac_match[] = { 4102a321798SJoachim Eastwood { .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data}, 4112a321798SJoachim Eastwood { .compatible = "st,stih416-dwmac", .data = &stih4xx_dwmac_data}, 4122a321798SJoachim Eastwood { .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data}, 4132a321798SJoachim Eastwood { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, 4142a321798SJoachim Eastwood { } 4152a321798SJoachim Eastwood }; 4162a321798SJoachim Eastwood MODULE_DEVICE_TABLE(of, sti_dwmac_match); 4172a321798SJoachim Eastwood 4182a321798SJoachim Eastwood static struct platform_driver sti_dwmac_driver = { 4198387ee21SJoachim Eastwood .probe = sti_dwmac_probe, 4202517cfd4SJoachim Eastwood .remove = sti_dwmac_remove, 4212a321798SJoachim Eastwood .driver = { 4222a321798SJoachim Eastwood .name = "sti-dwmac", 4232517cfd4SJoachim Eastwood .pm = &sti_dwmac_pm_ops, 4242a321798SJoachim Eastwood .of_match_table = sti_dwmac_match, 4252a321798SJoachim Eastwood }, 4262a321798SJoachim Eastwood }; 4272a321798SJoachim Eastwood module_platform_driver(sti_dwmac_driver); 4282a321798SJoachim Eastwood 4292a321798SJoachim Eastwood MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>"); 4302a321798SJoachim Eastwood MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer"); 4312a321798SJoachim Eastwood MODULE_LICENSE("GPL"); 432