1732fdf0eSGiuseppe CAVALLARO /* 2d15891caSSrinivas Kandagatla * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer 3d15891caSSrinivas Kandagatla * 4d15891caSSrinivas Kandagatla * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited 5d15891caSSrinivas Kandagatla * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 653b26b9bSGiuseppe CAVALLARO * Contributors: Giuseppe Cavallaro <peppe.cavallaro@st.com> 7d15891caSSrinivas Kandagatla * 8d15891caSSrinivas Kandagatla * This program is free software; you can redistribute it and/or modify 9d15891caSSrinivas Kandagatla * it under the terms of the GNU General Public License as published by 10d15891caSSrinivas Kandagatla * the Free Software Foundation; either version 2 of the License, or 11d15891caSSrinivas Kandagatla * (at your option) any later version. 12d15891caSSrinivas Kandagatla */ 13d15891caSSrinivas Kandagatla 14d15891caSSrinivas Kandagatla #include <linux/kernel.h> 15d15891caSSrinivas Kandagatla #include <linux/slab.h> 16d15891caSSrinivas Kandagatla #include <linux/platform_device.h> 17d15891caSSrinivas Kandagatla #include <linux/stmmac.h> 18d15891caSSrinivas Kandagatla #include <linux/phy.h> 19d15891caSSrinivas Kandagatla #include <linux/mfd/syscon.h> 202a321798SJoachim Eastwood #include <linux/module.h> 21d15891caSSrinivas Kandagatla #include <linux/regmap.h> 22d15891caSSrinivas Kandagatla #include <linux/clk.h> 23d15891caSSrinivas Kandagatla #include <linux/of.h> 24149adeddSJoachim Eastwood #include <linux/of_device.h> 25d15891caSSrinivas Kandagatla #include <linux/of_net.h> 26d15891caSSrinivas Kandagatla 27f10f9fb2SAndy Shevchenko #include "stmmac_platform.h" 28f10f9fb2SAndy Shevchenko 2953b26b9bSGiuseppe CAVALLARO #define DWMAC_125MHZ 125000000 3053b26b9bSGiuseppe CAVALLARO #define DWMAC_50MHZ 50000000 3153b26b9bSGiuseppe CAVALLARO #define DWMAC_25MHZ 25000000 3253b26b9bSGiuseppe CAVALLARO #define DWMAC_2_5MHZ 2500000 3353b26b9bSGiuseppe CAVALLARO 3453b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_RGMII(iface) (iface == PHY_INTERFACE_MODE_RGMII || \ 3553b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_ID || \ 3653b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_RXID || \ 3753b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_RGMII_TXID) 3853b26b9bSGiuseppe CAVALLARO 3953b26b9bSGiuseppe CAVALLARO #define IS_PHY_IF_MODE_GBIT(iface) (IS_PHY_IF_MODE_RGMII(iface) || \ 4053b26b9bSGiuseppe CAVALLARO iface == PHY_INTERFACE_MODE_GMII) 4153b26b9bSGiuseppe CAVALLARO 42732fdf0eSGiuseppe CAVALLARO /* STiH4xx register definitions (STiH415/STiH416/STiH407/STiH410 families) 43732fdf0eSGiuseppe CAVALLARO * 44d15891caSSrinivas Kandagatla * Below table summarizes the clock requirement and clock sources for 45d15891caSSrinivas Kandagatla * supported phy interface modes with link speeds. 46d15891caSSrinivas Kandagatla * ________________________________________________ 47d15891caSSrinivas Kandagatla *| PHY_MODE | 1000 Mbit Link | 100 Mbit Link | 48d15891caSSrinivas Kandagatla * ------------------------------------------------ 49d15891caSSrinivas Kandagatla *| MII | n/a | 25Mhz | 50d15891caSSrinivas Kandagatla *| | | txclk | 51d15891caSSrinivas Kandagatla * ------------------------------------------------ 52d15891caSSrinivas Kandagatla *| GMII | 125Mhz | 25Mhz | 53d15891caSSrinivas Kandagatla *| | clk-125/txclk | txclk | 54d15891caSSrinivas Kandagatla * ------------------------------------------------ 55d15891caSSrinivas Kandagatla *| RGMII | 125Mhz | 25Mhz | 56d15891caSSrinivas Kandagatla *| | clk-125/txclk | clkgen | 5753b26b9bSGiuseppe CAVALLARO *| | clkgen | | 58d15891caSSrinivas Kandagatla * ------------------------------------------------ 59d15891caSSrinivas Kandagatla *| RMII | n/a | 25Mhz | 60d15891caSSrinivas Kandagatla *| | |clkgen/phyclk-in | 61d15891caSSrinivas Kandagatla * ------------------------------------------------ 62d15891caSSrinivas Kandagatla * 6353b26b9bSGiuseppe CAVALLARO * Register Configuration 6453b26b9bSGiuseppe CAVALLARO *------------------------------- 6553b26b9bSGiuseppe CAVALLARO * src |BIT(8)| BIT(7)| BIT(6)| 6653b26b9bSGiuseppe CAVALLARO *------------------------------- 67d15891caSSrinivas Kandagatla * txclk | 0 | n/a | 1 | 6853b26b9bSGiuseppe CAVALLARO *------------------------------- 69d15891caSSrinivas Kandagatla * ck_125| 0 | n/a | 0 | 7053b26b9bSGiuseppe CAVALLARO *------------------------------- 71d15891caSSrinivas Kandagatla * phyclk| 1 | 0 | n/a | 7253b26b9bSGiuseppe CAVALLARO *------------------------------- 73d15891caSSrinivas Kandagatla * clkgen| 1 | 1 | n/a | 7453b26b9bSGiuseppe CAVALLARO *------------------------------- 75d15891caSSrinivas Kandagatla */ 76d15891caSSrinivas Kandagatla 7753b26b9bSGiuseppe CAVALLARO #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6) 7853b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TX_RETIME_CLK BIT(8) 7953b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 8053b26b9bSGiuseppe CAVALLARO #define STIH4XX_ETH_SEL_TXCLK_NOT_CLK125 BIT(6) 81d15891caSSrinivas Kandagatla 82732fdf0eSGiuseppe CAVALLARO /* STiD127 register definitions 8353b26b9bSGiuseppe CAVALLARO *----------------------- 8453b26b9bSGiuseppe CAVALLARO * src |BIT(6)| BIT(7)| 8553b26b9bSGiuseppe CAVALLARO *----------------------- 8653b26b9bSGiuseppe CAVALLARO * MII | 1 | n/a | 8753b26b9bSGiuseppe CAVALLARO *----------------------- 8853b26b9bSGiuseppe CAVALLARO * RMII | n/a | 1 | 8953b26b9bSGiuseppe CAVALLARO * clkgen| | | 9053b26b9bSGiuseppe CAVALLARO *----------------------- 9153b26b9bSGiuseppe CAVALLARO * RMII | n/a | 0 | 9253b26b9bSGiuseppe CAVALLARO * phyclk| | | 9353b26b9bSGiuseppe CAVALLARO *----------------------- 9453b26b9bSGiuseppe CAVALLARO * RGMII | 1 | n/a | 9553b26b9bSGiuseppe CAVALLARO * clkgen| | | 9653b26b9bSGiuseppe CAVALLARO *----------------------- 97d15891caSSrinivas Kandagatla */ 98d15891caSSrinivas Kandagatla 9953b26b9bSGiuseppe CAVALLARO #define STID127_RETIME_SRC_MASK GENMASK(7, 6) 10053b26b9bSGiuseppe CAVALLARO #define STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK BIT(7) 10153b26b9bSGiuseppe CAVALLARO #define STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK BIT(6) 102d15891caSSrinivas Kandagatla 103d15891caSSrinivas Kandagatla #define ENMII_MASK GENMASK(5, 5) 104d15891caSSrinivas Kandagatla #define ENMII BIT(5) 10553b26b9bSGiuseppe CAVALLARO #define EN_MASK GENMASK(1, 1) 10653b26b9bSGiuseppe CAVALLARO #define EN BIT(1) 107d15891caSSrinivas Kandagatla 108732fdf0eSGiuseppe CAVALLARO /* 109d15891caSSrinivas Kandagatla * 3 bits [4:2] 110d15891caSSrinivas Kandagatla * 000-GMII/MII 111d15891caSSrinivas Kandagatla * 001-RGMII 112d15891caSSrinivas Kandagatla * 010-SGMII 113d15891caSSrinivas Kandagatla * 100-RMII 114d15891caSSrinivas Kandagatla */ 115d15891caSSrinivas Kandagatla #define MII_PHY_SEL_MASK GENMASK(4, 2) 116d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RMII BIT(4) 117d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_SGMII BIT(3) 118d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_RGMII BIT(2) 119d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_GMII 0x0 120d15891caSSrinivas Kandagatla #define ETH_PHY_SEL_MII 0x0 121d15891caSSrinivas Kandagatla 122d15891caSSrinivas Kandagatla struct sti_dwmac { 12353b26b9bSGiuseppe CAVALLARO int interface; /* MII interface */ 12453b26b9bSGiuseppe CAVALLARO bool ext_phyclk; /* Clock from external PHY */ 12553b26b9bSGiuseppe CAVALLARO u32 tx_retime_src; /* TXCLK Retiming*/ 12653b26b9bSGiuseppe CAVALLARO struct clk *clk; /* PHY clock */ 1279b1a6d36SPeter Griffin u32 ctrl_reg; /* GMAC glue-logic control register */ 12853b26b9bSGiuseppe CAVALLARO int clk_sel_reg; /* GMAC ext clk selection register */ 129d15891caSSrinivas Kandagatla struct device *dev; 130d15891caSSrinivas Kandagatla struct regmap *regmap; 13153b26b9bSGiuseppe CAVALLARO u32 speed; 132d15891caSSrinivas Kandagatla }; 133d15891caSSrinivas Kandagatla 134d15891caSSrinivas Kandagatla static u32 phy_intf_sels[] = { 135d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_MII] = ETH_PHY_SEL_MII, 136d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_GMII] = ETH_PHY_SEL_GMII, 137d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII] = ETH_PHY_SEL_RGMII, 138d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RGMII_ID] = ETH_PHY_SEL_RGMII, 139d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_SGMII] = ETH_PHY_SEL_SGMII, 140d15891caSSrinivas Kandagatla [PHY_INTERFACE_MODE_RMII] = ETH_PHY_SEL_RMII, 141d15891caSSrinivas Kandagatla }; 142d15891caSSrinivas Kandagatla 143d15891caSSrinivas Kandagatla enum { 144d15891caSSrinivas Kandagatla TX_RETIME_SRC_NA = 0, 145d15891caSSrinivas Kandagatla TX_RETIME_SRC_TXCLK = 1, 146d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLK_125, 147d15891caSSrinivas Kandagatla TX_RETIME_SRC_PHYCLK, 148d15891caSSrinivas Kandagatla TX_RETIME_SRC_CLKGEN, 149d15891caSSrinivas Kandagatla }; 150d15891caSSrinivas Kandagatla 15153b26b9bSGiuseppe CAVALLARO static u32 stih4xx_tx_retime_val[] = { 15253b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_TXCLK] = STIH4XX_ETH_SEL_TXCLK_NOT_CLK125, 153d15891caSSrinivas Kandagatla [TX_RETIME_SRC_CLK_125] = 0x0, 15453b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_PHYCLK] = STIH4XX_ETH_SEL_TX_RETIME_CLK, 15553b26b9bSGiuseppe CAVALLARO [TX_RETIME_SRC_CLKGEN] = STIH4XX_ETH_SEL_TX_RETIME_CLK 15653b26b9bSGiuseppe CAVALLARO | STIH4XX_ETH_SEL_INTERNAL_NOTEXT_PHYCLK, 157d15891caSSrinivas Kandagatla }; 158d15891caSSrinivas Kandagatla 15953b26b9bSGiuseppe CAVALLARO static void stih4xx_fix_retime_src(void *priv, u32 spd) 160d15891caSSrinivas Kandagatla { 16153b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 16253b26b9bSGiuseppe CAVALLARO u32 src = dwmac->tx_retime_src; 16353b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 16453b26b9bSGiuseppe CAVALLARO u32 freq = 0; 165d15891caSSrinivas Kandagatla 16653b26b9bSGiuseppe CAVALLARO if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 167d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_TXCLK; 168d15891caSSrinivas Kandagatla } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 169d15891caSSrinivas Kandagatla if (dwmac->ext_phyclk) { 170d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_PHYCLK; 171d15891caSSrinivas Kandagatla } else { 172d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN; 17353b26b9bSGiuseppe CAVALLARO freq = DWMAC_50MHZ; 174d15891caSSrinivas Kandagatla } 175d15891caSSrinivas Kandagatla } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 17653b26b9bSGiuseppe CAVALLARO /* On GiGa clk source can be either ext or from clkgen */ 17753b26b9bSGiuseppe CAVALLARO if (spd == SPEED_1000) { 17853b26b9bSGiuseppe CAVALLARO freq = DWMAC_125MHZ; 17953b26b9bSGiuseppe CAVALLARO } else { 18053b26b9bSGiuseppe CAVALLARO /* Switch to clkgen for these speeds */ 181d15891caSSrinivas Kandagatla src = TX_RETIME_SRC_CLKGEN; 18253b26b9bSGiuseppe CAVALLARO if (spd == SPEED_100) 18353b26b9bSGiuseppe CAVALLARO freq = DWMAC_25MHZ; 18453b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_10) 18553b26b9bSGiuseppe CAVALLARO freq = DWMAC_2_5MHZ; 18653b26b9bSGiuseppe CAVALLARO } 187d15891caSSrinivas Kandagatla } 188d15891caSSrinivas Kandagatla 18953b26b9bSGiuseppe CAVALLARO if (src == TX_RETIME_SRC_CLKGEN && dwmac->clk && freq) 190d15891caSSrinivas Kandagatla clk_set_rate(dwmac->clk, freq); 191d15891caSSrinivas Kandagatla 19253b26b9bSGiuseppe CAVALLARO regmap_update_bits(dwmac->regmap, reg, STIH4XX_RETIME_SRC_MASK, 19353b26b9bSGiuseppe CAVALLARO stih4xx_tx_retime_val[src]); 194d15891caSSrinivas Kandagatla } 195d15891caSSrinivas Kandagatla 19653b26b9bSGiuseppe CAVALLARO static void stid127_fix_retime_src(void *priv, u32 spd) 19753b26b9bSGiuseppe CAVALLARO { 19853b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 19953b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 20053b26b9bSGiuseppe CAVALLARO u32 freq = 0; 20153b26b9bSGiuseppe CAVALLARO u32 val = 0; 20253b26b9bSGiuseppe CAVALLARO 20353b26b9bSGiuseppe CAVALLARO if (dwmac->interface == PHY_INTERFACE_MODE_MII) { 20453b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 20553b26b9bSGiuseppe CAVALLARO } else if (dwmac->interface == PHY_INTERFACE_MODE_RMII) { 20653b26b9bSGiuseppe CAVALLARO if (!dwmac->ext_phyclk) { 20753b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_PHYCLK; 20853b26b9bSGiuseppe CAVALLARO freq = DWMAC_50MHZ; 20953b26b9bSGiuseppe CAVALLARO } 21053b26b9bSGiuseppe CAVALLARO } else if (IS_PHY_IF_MODE_RGMII(dwmac->interface)) { 21153b26b9bSGiuseppe CAVALLARO val = STID127_ETH_SEL_INTERNAL_NOTEXT_TXCLK; 21253b26b9bSGiuseppe CAVALLARO if (spd == SPEED_1000) 21353b26b9bSGiuseppe CAVALLARO freq = DWMAC_125MHZ; 21453b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_100) 21553b26b9bSGiuseppe CAVALLARO freq = DWMAC_25MHZ; 21653b26b9bSGiuseppe CAVALLARO else if (spd == SPEED_10) 21753b26b9bSGiuseppe CAVALLARO freq = DWMAC_2_5MHZ; 21853b26b9bSGiuseppe CAVALLARO } 21953b26b9bSGiuseppe CAVALLARO 22053b26b9bSGiuseppe CAVALLARO if (dwmac->clk && freq) 22153b26b9bSGiuseppe CAVALLARO clk_set_rate(dwmac->clk, freq); 22253b26b9bSGiuseppe CAVALLARO 22353b26b9bSGiuseppe CAVALLARO regmap_update_bits(dwmac->regmap, reg, STID127_RETIME_SRC_MASK, val); 22453b26b9bSGiuseppe CAVALLARO } 22553b26b9bSGiuseppe CAVALLARO 22653b26b9bSGiuseppe CAVALLARO static void sti_dwmac_ctrl_init(struct sti_dwmac *dwmac) 22753b26b9bSGiuseppe CAVALLARO { 22853b26b9bSGiuseppe CAVALLARO struct regmap *regmap = dwmac->regmap; 22953b26b9bSGiuseppe CAVALLARO int iface = dwmac->interface; 23053b26b9bSGiuseppe CAVALLARO struct device *dev = dwmac->dev; 23153b26b9bSGiuseppe CAVALLARO struct device_node *np = dev->of_node; 23253b26b9bSGiuseppe CAVALLARO u32 reg = dwmac->ctrl_reg; 23353b26b9bSGiuseppe CAVALLARO u32 val; 23453b26b9bSGiuseppe CAVALLARO 23553b26b9bSGiuseppe CAVALLARO if (dwmac->clk) 23653b26b9bSGiuseppe CAVALLARO clk_prepare_enable(dwmac->clk); 23753b26b9bSGiuseppe CAVALLARO 23853b26b9bSGiuseppe CAVALLARO if (of_property_read_bool(np, "st,gmac_en")) 23953b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, EN_MASK, EN); 24053b26b9bSGiuseppe CAVALLARO 24153b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, MII_PHY_SEL_MASK, phy_intf_sels[iface]); 24253b26b9bSGiuseppe CAVALLARO 24353b26b9bSGiuseppe CAVALLARO val = (iface == PHY_INTERFACE_MODE_REVMII) ? 0 : ENMII; 24453b26b9bSGiuseppe CAVALLARO regmap_update_bits(regmap, reg, ENMII_MASK, val); 24553b26b9bSGiuseppe CAVALLARO } 24653b26b9bSGiuseppe CAVALLARO 24753b26b9bSGiuseppe CAVALLARO static int stix4xx_init(struct platform_device *pdev, void *priv) 24853b26b9bSGiuseppe CAVALLARO { 24953b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 25053b26b9bSGiuseppe CAVALLARO u32 spd = dwmac->speed; 25153b26b9bSGiuseppe CAVALLARO 25253b26b9bSGiuseppe CAVALLARO sti_dwmac_ctrl_init(dwmac); 25353b26b9bSGiuseppe CAVALLARO 25453b26b9bSGiuseppe CAVALLARO stih4xx_fix_retime_src(priv, spd); 25553b26b9bSGiuseppe CAVALLARO 25653b26b9bSGiuseppe CAVALLARO return 0; 25753b26b9bSGiuseppe CAVALLARO } 25853b26b9bSGiuseppe CAVALLARO 25953b26b9bSGiuseppe CAVALLARO static int stid127_init(struct platform_device *pdev, void *priv) 26053b26b9bSGiuseppe CAVALLARO { 26153b26b9bSGiuseppe CAVALLARO struct sti_dwmac *dwmac = priv; 26253b26b9bSGiuseppe CAVALLARO u32 spd = dwmac->speed; 26353b26b9bSGiuseppe CAVALLARO 26453b26b9bSGiuseppe CAVALLARO sti_dwmac_ctrl_init(dwmac); 26553b26b9bSGiuseppe CAVALLARO 26653b26b9bSGiuseppe CAVALLARO stid127_fix_retime_src(priv, spd); 26753b26b9bSGiuseppe CAVALLARO 26853b26b9bSGiuseppe CAVALLARO return 0; 269d15891caSSrinivas Kandagatla } 270d15891caSSrinivas Kandagatla 271d15891caSSrinivas Kandagatla static void sti_dwmac_exit(struct platform_device *pdev, void *priv) 272d15891caSSrinivas Kandagatla { 273d15891caSSrinivas Kandagatla struct sti_dwmac *dwmac = priv; 274d15891caSSrinivas Kandagatla 275d15891caSSrinivas Kandagatla if (dwmac->clk) 276d15891caSSrinivas Kandagatla clk_disable_unprepare(dwmac->clk); 277d15891caSSrinivas Kandagatla } 278d15891caSSrinivas Kandagatla static int sti_dwmac_parse_data(struct sti_dwmac *dwmac, 279d15891caSSrinivas Kandagatla struct platform_device *pdev) 280d15891caSSrinivas Kandagatla { 281d15891caSSrinivas Kandagatla struct resource *res; 282d15891caSSrinivas Kandagatla struct device *dev = &pdev->dev; 283d15891caSSrinivas Kandagatla struct device_node *np = dev->of_node; 284d15891caSSrinivas Kandagatla struct regmap *regmap; 285d15891caSSrinivas Kandagatla int err; 286d15891caSSrinivas Kandagatla 287d15891caSSrinivas Kandagatla if (!np) 288d15891caSSrinivas Kandagatla return -EINVAL; 289d15891caSSrinivas Kandagatla 29053b26b9bSGiuseppe CAVALLARO /* clk selection from extra syscfg register */ 29153b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = -ENXIO; 29253b26b9bSGiuseppe CAVALLARO res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf"); 29353b26b9bSGiuseppe CAVALLARO if (res) 29453b26b9bSGiuseppe CAVALLARO dwmac->clk_sel_reg = res->start; 295d15891caSSrinivas Kandagatla 296d15891caSSrinivas Kandagatla regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); 297d15891caSSrinivas Kandagatla if (IS_ERR(regmap)) 298d15891caSSrinivas Kandagatla return PTR_ERR(regmap); 299d15891caSSrinivas Kandagatla 3009b1a6d36SPeter Griffin err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg); 3019b1a6d36SPeter Griffin if (err) { 3029b1a6d36SPeter Griffin dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err); 3039b1a6d36SPeter Griffin return err; 3049b1a6d36SPeter Griffin } 3059b1a6d36SPeter Griffin 306d15891caSSrinivas Kandagatla dwmac->dev = dev; 307d15891caSSrinivas Kandagatla dwmac->interface = of_get_phy_mode(np); 308d15891caSSrinivas Kandagatla dwmac->regmap = regmap; 309d15891caSSrinivas Kandagatla dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); 31053b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_NA; 31153b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_100; 312d15891caSSrinivas Kandagatla 313d15891caSSrinivas Kandagatla if (IS_PHY_IF_MODE_GBIT(dwmac->interface)) { 314d15891caSSrinivas Kandagatla const char *rs; 315d15891caSSrinivas Kandagatla 316d15891caSSrinivas Kandagatla err = of_property_read_string(np, "st,tx-retime-src", &rs); 31750262c85SGeert Uytterhoeven if (err < 0) { 31853b26b9bSGiuseppe CAVALLARO dev_warn(dev, "Use internal clock source\n"); 31950262c85SGeert Uytterhoeven dwmac->tx_retime_src = TX_RETIME_SRC_CLKGEN; 32050262c85SGeert Uytterhoeven } else if (!strcasecmp(rs, "clk_125")) { 32153b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_CLK_125; 32250262c85SGeert Uytterhoeven } else if (!strcasecmp(rs, "txclk")) { 32353b26b9bSGiuseppe CAVALLARO dwmac->tx_retime_src = TX_RETIME_SRC_TXCLK; 32450262c85SGeert Uytterhoeven } 32553b26b9bSGiuseppe CAVALLARO 32653b26b9bSGiuseppe CAVALLARO dwmac->speed = SPEED_1000; 327d15891caSSrinivas Kandagatla } 328d15891caSSrinivas Kandagatla 329d15891caSSrinivas Kandagatla dwmac->clk = devm_clk_get(dev, "sti-ethclk"); 33053b26b9bSGiuseppe CAVALLARO if (IS_ERR(dwmac->clk)) { 33153b26b9bSGiuseppe CAVALLARO dev_warn(dev, "No phy clock provided...\n"); 332d15891caSSrinivas Kandagatla dwmac->clk = NULL; 333d15891caSSrinivas Kandagatla } 334d15891caSSrinivas Kandagatla 335d15891caSSrinivas Kandagatla return 0; 336d15891caSSrinivas Kandagatla } 337d15891caSSrinivas Kandagatla 3388387ee21SJoachim Eastwood static int sti_dwmac_probe(struct platform_device *pdev) 339d15891caSSrinivas Kandagatla { 3408387ee21SJoachim Eastwood struct plat_stmmacenet_data *plat_dat; 341149adeddSJoachim Eastwood const struct stmmac_of_data *data; 3428387ee21SJoachim Eastwood struct stmmac_resources stmmac_res; 343d15891caSSrinivas Kandagatla struct sti_dwmac *dwmac; 344d15891caSSrinivas Kandagatla int ret; 345d15891caSSrinivas Kandagatla 346149adeddSJoachim Eastwood data = of_device_get_match_data(&pdev->dev); 347149adeddSJoachim Eastwood if (!data) { 348149adeddSJoachim Eastwood dev_err(&pdev->dev, "No OF match data provided\n"); 349149adeddSJoachim Eastwood return -EINVAL; 350149adeddSJoachim Eastwood } 351149adeddSJoachim Eastwood 3528387ee21SJoachim Eastwood ret = stmmac_get_platform_resources(pdev, &stmmac_res); 3538387ee21SJoachim Eastwood if (ret) 3548387ee21SJoachim Eastwood return ret; 3558387ee21SJoachim Eastwood 3568387ee21SJoachim Eastwood plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 3578387ee21SJoachim Eastwood if (IS_ERR(plat_dat)) 3588387ee21SJoachim Eastwood return PTR_ERR(plat_dat); 3598387ee21SJoachim Eastwood 360d15891caSSrinivas Kandagatla dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); 361d15891caSSrinivas Kandagatla if (!dwmac) 3628387ee21SJoachim Eastwood return -ENOMEM; 363d15891caSSrinivas Kandagatla 364d15891caSSrinivas Kandagatla ret = sti_dwmac_parse_data(dwmac, pdev); 365d15891caSSrinivas Kandagatla if (ret) { 366d15891caSSrinivas Kandagatla dev_err(&pdev->dev, "Unable to parse OF data\n"); 3678387ee21SJoachim Eastwood return ret; 368d15891caSSrinivas Kandagatla } 369d15891caSSrinivas Kandagatla 3708387ee21SJoachim Eastwood plat_dat->bsp_priv = dwmac; 371149adeddSJoachim Eastwood plat_dat->init = data->init; 3728387ee21SJoachim Eastwood plat_dat->exit = sti_dwmac_exit; 373149adeddSJoachim Eastwood plat_dat->fix_mac_speed = data->fix_mac_speed; 3748387ee21SJoachim Eastwood 3758387ee21SJoachim Eastwood ret = plat_dat->init(pdev, plat_dat->bsp_priv); 3768387ee21SJoachim Eastwood if (ret) 3778387ee21SJoachim Eastwood return ret; 3788387ee21SJoachim Eastwood 3798387ee21SJoachim Eastwood return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 380d15891caSSrinivas Kandagatla } 381d15891caSSrinivas Kandagatla 3822a321798SJoachim Eastwood static const struct stmmac_of_data stih4xx_dwmac_data = { 38353b26b9bSGiuseppe CAVALLARO .fix_mac_speed = stih4xx_fix_retime_src, 38453b26b9bSGiuseppe CAVALLARO .init = stix4xx_init, 38553b26b9bSGiuseppe CAVALLARO }; 38653b26b9bSGiuseppe CAVALLARO 3872a321798SJoachim Eastwood static const struct stmmac_of_data stid127_dwmac_data = { 38853b26b9bSGiuseppe CAVALLARO .fix_mac_speed = stid127_fix_retime_src, 38953b26b9bSGiuseppe CAVALLARO .init = stid127_init, 390d15891caSSrinivas Kandagatla }; 3912a321798SJoachim Eastwood 3922a321798SJoachim Eastwood static const struct of_device_id sti_dwmac_match[] = { 3932a321798SJoachim Eastwood { .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data}, 3942a321798SJoachim Eastwood { .compatible = "st,stih416-dwmac", .data = &stih4xx_dwmac_data}, 3952a321798SJoachim Eastwood { .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data}, 3962a321798SJoachim Eastwood { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, 3972a321798SJoachim Eastwood { } 3982a321798SJoachim Eastwood }; 3992a321798SJoachim Eastwood MODULE_DEVICE_TABLE(of, sti_dwmac_match); 4002a321798SJoachim Eastwood 4012a321798SJoachim Eastwood static struct platform_driver sti_dwmac_driver = { 4028387ee21SJoachim Eastwood .probe = sti_dwmac_probe, 4032a321798SJoachim Eastwood .remove = stmmac_pltfr_remove, 4042a321798SJoachim Eastwood .driver = { 4052a321798SJoachim Eastwood .name = "sti-dwmac", 4062a321798SJoachim Eastwood .pm = &stmmac_pltfr_pm_ops, 4072a321798SJoachim Eastwood .of_match_table = sti_dwmac_match, 4082a321798SJoachim Eastwood }, 4092a321798SJoachim Eastwood }; 4102a321798SJoachim Eastwood module_platform_driver(sti_dwmac_driver); 4112a321798SJoachim Eastwood 4122a321798SJoachim Eastwood MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@st.com>"); 4132a321798SJoachim Eastwood MODULE_DESCRIPTION("STMicroelectronics DWMAC Specific Glue layer"); 4142a321798SJoachim Eastwood MODULE_LICENSE("GPL"); 415