1 /* Copyright Altera Corporation (C) 2014. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License, version 2, 5 * as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * 15 * Adopted from dwmac-sti.c 16 */ 17 18 #include <linux/mfd/syscon.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/phy.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/stmmac.h> 26 27 #include "stmmac.h" 28 #include "stmmac_platform.h" 29 30 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 33 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 34 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 35 36 #define EMAC_SPLITTER_CTRL_REG 0x0 37 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3 38 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2 39 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3 40 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0 41 42 struct socfpga_dwmac { 43 int interface; 44 u32 reg_offset; 45 u32 reg_shift; 46 struct device *dev; 47 struct regmap *sys_mgr_base_addr; 48 struct reset_control *stmmac_rst; 49 void __iomem *splitter_base; 50 }; 51 52 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed) 53 { 54 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv; 55 void __iomem *splitter_base = dwmac->splitter_base; 56 u32 val; 57 58 if (!splitter_base) 59 return; 60 61 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG); 62 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK; 63 64 switch (speed) { 65 case 1000: 66 val |= EMAC_SPLITTER_CTRL_SPEED_1000; 67 break; 68 case 100: 69 val |= EMAC_SPLITTER_CTRL_SPEED_100; 70 break; 71 case 10: 72 val |= EMAC_SPLITTER_CTRL_SPEED_10; 73 break; 74 default: 75 return; 76 } 77 78 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG); 79 } 80 81 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) 82 { 83 struct device_node *np = dev->of_node; 84 struct regmap *sys_mgr_base_addr; 85 u32 reg_offset, reg_shift; 86 int ret; 87 struct device_node *np_splitter; 88 struct resource res_splitter; 89 90 dwmac->stmmac_rst = devm_reset_control_get(dev, 91 STMMAC_RESOURCE_NAME); 92 if (IS_ERR(dwmac->stmmac_rst)) { 93 dev_info(dev, "Could not get reset control!\n"); 94 return -EINVAL; 95 } 96 97 dwmac->interface = of_get_phy_mode(np); 98 99 sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); 100 if (IS_ERR(sys_mgr_base_addr)) { 101 dev_info(dev, "No sysmgr-syscon node found\n"); 102 return PTR_ERR(sys_mgr_base_addr); 103 } 104 105 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); 106 if (ret) { 107 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); 108 return -EINVAL; 109 } 110 111 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); 112 if (ret) { 113 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); 114 return -EINVAL; 115 } 116 117 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); 118 if (np_splitter) { 119 if (of_address_to_resource(np_splitter, 0, &res_splitter)) { 120 dev_info(dev, "Missing emac splitter address\n"); 121 return -EINVAL; 122 } 123 124 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); 125 if (IS_ERR(dwmac->splitter_base)) { 126 dev_info(dev, "Failed to mapping emac splitter\n"); 127 return PTR_ERR(dwmac->splitter_base); 128 } 129 } 130 131 dwmac->reg_offset = reg_offset; 132 dwmac->reg_shift = reg_shift; 133 dwmac->sys_mgr_base_addr = sys_mgr_base_addr; 134 dwmac->dev = dev; 135 136 return 0; 137 } 138 139 static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac) 140 { 141 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 142 int phymode = dwmac->interface; 143 u32 reg_offset = dwmac->reg_offset; 144 u32 reg_shift = dwmac->reg_shift; 145 u32 ctrl, val; 146 147 switch (phymode) { 148 case PHY_INTERFACE_MODE_RGMII: 149 case PHY_INTERFACE_MODE_RGMII_ID: 150 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 151 break; 152 case PHY_INTERFACE_MODE_MII: 153 case PHY_INTERFACE_MODE_GMII: 154 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 155 break; 156 default: 157 dev_err(dwmac->dev, "bad phy mode %d\n", phymode); 158 return -EINVAL; 159 } 160 161 /* Overwrite val to GMII if splitter core is enabled. The phymode here 162 * is the actual phy mode on phy hardware, but phy interface from 163 * EMAC core is GMII. 164 */ 165 if (dwmac->splitter_base) 166 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 167 168 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 169 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); 170 ctrl |= val << reg_shift; 171 172 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 173 return 0; 174 } 175 176 static void *socfpga_dwmac_probe(struct platform_device *pdev) 177 { 178 struct device *dev = &pdev->dev; 179 int ret; 180 struct socfpga_dwmac *dwmac; 181 182 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL); 183 if (!dwmac) 184 return ERR_PTR(-ENOMEM); 185 186 ret = socfpga_dwmac_parse_data(dwmac, dev); 187 if (ret) { 188 dev_err(dev, "Unable to parse OF data\n"); 189 return ERR_PTR(ret); 190 } 191 192 ret = socfpga_dwmac_setup(dwmac); 193 if (ret) { 194 dev_err(dev, "couldn't setup SoC glue (%d)\n", ret); 195 return ERR_PTR(ret); 196 } 197 198 return dwmac; 199 } 200 201 static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv) 202 { 203 struct socfpga_dwmac *dwmac = priv; 204 205 /* On socfpga platform exit, assert and hold reset to the 206 * enet controller - the default state after a hard reset. 207 */ 208 if (dwmac->stmmac_rst) 209 reset_control_assert(dwmac->stmmac_rst); 210 } 211 212 static int socfpga_dwmac_init(struct platform_device *pdev, void *priv) 213 { 214 struct socfpga_dwmac *dwmac = priv; 215 struct net_device *ndev = platform_get_drvdata(pdev); 216 struct stmmac_priv *stpriv = NULL; 217 int ret = 0; 218 219 if (ndev) 220 stpriv = netdev_priv(ndev); 221 222 /* Assert reset to the enet controller before changing the phy mode */ 223 if (dwmac->stmmac_rst) 224 reset_control_assert(dwmac->stmmac_rst); 225 226 /* Setup the phy mode in the system manager registers according to 227 * devicetree configuration 228 */ 229 ret = socfpga_dwmac_setup(dwmac); 230 231 /* Deassert reset for the phy configuration to be sampled by 232 * the enet controller, and operation to start in requested mode 233 */ 234 if (dwmac->stmmac_rst) 235 reset_control_deassert(dwmac->stmmac_rst); 236 237 /* Before the enet controller is suspended, the phy is suspended. 238 * This causes the phy clock to be gated. The enet controller is 239 * resumed before the phy, so the clock is still gated "off" when 240 * the enet controller is resumed. This code makes sure the phy 241 * is "resumed" before reinitializing the enet controller since 242 * the enet controller depends on an active phy clock to complete 243 * a DMA reset. A DMA reset will "time out" if executed 244 * with no phy clock input on the Synopsys enet controller. 245 * Verified through Synopsys Case #8000711656. 246 * 247 * Note that the phy clock is also gated when the phy is isolated. 248 * Phy "suspend" and "isolate" controls are located in phy basic 249 * control register 0, and can be modified by the phy driver 250 * framework. 251 */ 252 if (stpriv && stpriv->phydev) 253 phy_resume(stpriv->phydev); 254 255 return ret; 256 } 257 258 const struct stmmac_of_data socfpga_gmac_data = { 259 .setup = socfpga_dwmac_probe, 260 .init = socfpga_dwmac_init, 261 .exit = socfpga_dwmac_exit, 262 .fix_mac_speed = socfpga_dwmac_fix_mac_speed, 263 }; 264