1 /* Copyright Altera Corporation (C) 2014. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License, version 2, 5 * as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * 15 * Adopted from dwmac-sti.c 16 */ 17 18 #include <linux/mfd/syscon.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/phy.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/stmmac.h> 26 27 #include "stmmac.h" 28 #include "stmmac_platform.h" 29 30 #include "altr_tse_pcs.h" 31 32 #define SGMII_ADAPTER_CTRL_REG 0x00 33 #define SGMII_ADAPTER_DISABLE 0x0001 34 35 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 36 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 37 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 38 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 39 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 40 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010 41 42 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028 43 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004 44 45 #define EMAC_SPLITTER_CTRL_REG 0x0 46 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3 47 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2 48 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3 49 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0 50 51 struct socfpga_dwmac { 52 int interface; 53 u32 reg_offset; 54 u32 reg_shift; 55 struct device *dev; 56 struct regmap *sys_mgr_base_addr; 57 struct reset_control *stmmac_rst; 58 void __iomem *splitter_base; 59 bool f2h_ptp_ref_clk; 60 struct tse_pcs pcs; 61 }; 62 63 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed) 64 { 65 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv; 66 void __iomem *splitter_base = dwmac->splitter_base; 67 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; 68 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; 69 struct device *dev = dwmac->dev; 70 struct net_device *ndev = dev_get_drvdata(dev); 71 struct phy_device *phy_dev = ndev->phydev; 72 u32 val; 73 74 if ((tse_pcs_base) && (sgmii_adapter_base)) 75 writew(SGMII_ADAPTER_DISABLE, 76 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); 77 78 if (splitter_base) { 79 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG); 80 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK; 81 82 switch (speed) { 83 case 1000: 84 val |= EMAC_SPLITTER_CTRL_SPEED_1000; 85 break; 86 case 100: 87 val |= EMAC_SPLITTER_CTRL_SPEED_100; 88 break; 89 case 10: 90 val |= EMAC_SPLITTER_CTRL_SPEED_10; 91 break; 92 default: 93 return; 94 } 95 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG); 96 } 97 98 if (tse_pcs_base && sgmii_adapter_base) 99 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); 100 } 101 102 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) 103 { 104 struct device_node *np = dev->of_node; 105 struct regmap *sys_mgr_base_addr; 106 u32 reg_offset, reg_shift; 107 int ret, index; 108 struct device_node *np_splitter = NULL; 109 struct device_node *np_sgmii_adapter = NULL; 110 struct resource res_splitter; 111 struct resource res_tse_pcs; 112 struct resource res_sgmii_adapter; 113 114 dwmac->interface = of_get_phy_mode(np); 115 116 sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); 117 if (IS_ERR(sys_mgr_base_addr)) { 118 dev_info(dev, "No sysmgr-syscon node found\n"); 119 return PTR_ERR(sys_mgr_base_addr); 120 } 121 122 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); 123 if (ret) { 124 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); 125 return -EINVAL; 126 } 127 128 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); 129 if (ret) { 130 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); 131 return -EINVAL; 132 } 133 134 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk"); 135 136 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); 137 if (np_splitter) { 138 ret = of_address_to_resource(np_splitter, 0, &res_splitter); 139 of_node_put(np_splitter); 140 if (ret) { 141 dev_info(dev, "Missing emac splitter address\n"); 142 return -EINVAL; 143 } 144 145 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); 146 if (IS_ERR(dwmac->splitter_base)) { 147 dev_info(dev, "Failed to mapping emac splitter\n"); 148 return PTR_ERR(dwmac->splitter_base); 149 } 150 } 151 152 np_sgmii_adapter = of_parse_phandle(np, 153 "altr,gmii-to-sgmii-converter", 0); 154 if (np_sgmii_adapter) { 155 index = of_property_match_string(np_sgmii_adapter, "reg-names", 156 "hps_emac_interface_splitter_avalon_slave"); 157 158 if (index >= 0) { 159 if (of_address_to_resource(np_sgmii_adapter, index, 160 &res_splitter)) { 161 dev_err(dev, 162 "%s: ERROR: missing emac splitter address\n", 163 __func__); 164 ret = -EINVAL; 165 goto err_node_put; 166 } 167 168 dwmac->splitter_base = 169 devm_ioremap_resource(dev, &res_splitter); 170 171 if (IS_ERR(dwmac->splitter_base)) { 172 ret = PTR_ERR(dwmac->splitter_base); 173 goto err_node_put; 174 } 175 } 176 177 index = of_property_match_string(np_sgmii_adapter, "reg-names", 178 "gmii_to_sgmii_adapter_avalon_slave"); 179 180 if (index >= 0) { 181 if (of_address_to_resource(np_sgmii_adapter, index, 182 &res_sgmii_adapter)) { 183 dev_err(dev, 184 "%s: ERROR: failed mapping adapter\n", 185 __func__); 186 ret = -EINVAL; 187 goto err_node_put; 188 } 189 190 dwmac->pcs.sgmii_adapter_base = 191 devm_ioremap_resource(dev, &res_sgmii_adapter); 192 193 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) { 194 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base); 195 goto err_node_put; 196 } 197 } 198 199 index = of_property_match_string(np_sgmii_adapter, "reg-names", 200 "eth_tse_control_port"); 201 202 if (index >= 0) { 203 if (of_address_to_resource(np_sgmii_adapter, index, 204 &res_tse_pcs)) { 205 dev_err(dev, 206 "%s: ERROR: failed mapping tse control port\n", 207 __func__); 208 ret = -EINVAL; 209 goto err_node_put; 210 } 211 212 dwmac->pcs.tse_pcs_base = 213 devm_ioremap_resource(dev, &res_tse_pcs); 214 215 if (IS_ERR(dwmac->pcs.tse_pcs_base)) { 216 ret = PTR_ERR(dwmac->pcs.tse_pcs_base); 217 goto err_node_put; 218 } 219 } 220 } 221 dwmac->reg_offset = reg_offset; 222 dwmac->reg_shift = reg_shift; 223 dwmac->sys_mgr_base_addr = sys_mgr_base_addr; 224 dwmac->dev = dev; 225 of_node_put(np_sgmii_adapter); 226 227 return 0; 228 229 err_node_put: 230 of_node_put(np_sgmii_adapter); 231 return ret; 232 } 233 234 static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) 235 { 236 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 237 int phymode = dwmac->interface; 238 u32 reg_offset = dwmac->reg_offset; 239 u32 reg_shift = dwmac->reg_shift; 240 u32 ctrl, val, module; 241 242 switch (phymode) { 243 case PHY_INTERFACE_MODE_RGMII: 244 case PHY_INTERFACE_MODE_RGMII_ID: 245 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 246 break; 247 case PHY_INTERFACE_MODE_MII: 248 case PHY_INTERFACE_MODE_GMII: 249 case PHY_INTERFACE_MODE_SGMII: 250 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 251 break; 252 default: 253 dev_err(dwmac->dev, "bad phy mode %d\n", phymode); 254 return -EINVAL; 255 } 256 257 /* Overwrite val to GMII if splitter core is enabled. The phymode here 258 * is the actual phy mode on phy hardware, but phy interface from 259 * EMAC core is GMII. 260 */ 261 if (dwmac->splitter_base) 262 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 263 264 /* Assert reset to the enet controller before changing the phy mode */ 265 if (dwmac->stmmac_rst) 266 reset_control_assert(dwmac->stmmac_rst); 267 268 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 269 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); 270 ctrl |= val << reg_shift; 271 272 if (dwmac->f2h_ptp_ref_clk) { 273 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); 274 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 275 &module); 276 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); 277 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 278 module); 279 } else { 280 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); 281 } 282 283 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 284 285 /* Deassert reset for the phy configuration to be sampled by 286 * the enet controller, and operation to start in requested mode 287 */ 288 if (dwmac->stmmac_rst) 289 reset_control_deassert(dwmac->stmmac_rst); 290 if (phymode == PHY_INTERFACE_MODE_SGMII) { 291 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { 292 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); 293 return -EINVAL; 294 } 295 } 296 297 return 0; 298 } 299 300 static int socfpga_dwmac_probe(struct platform_device *pdev) 301 { 302 struct plat_stmmacenet_data *plat_dat; 303 struct stmmac_resources stmmac_res; 304 struct device *dev = &pdev->dev; 305 int ret; 306 struct socfpga_dwmac *dwmac; 307 308 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 309 if (ret) 310 return ret; 311 312 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 313 if (IS_ERR(plat_dat)) 314 return PTR_ERR(plat_dat); 315 316 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL); 317 if (!dwmac) 318 return -ENOMEM; 319 320 ret = socfpga_dwmac_parse_data(dwmac, dev); 321 if (ret) { 322 dev_err(dev, "Unable to parse OF data\n"); 323 return ret; 324 } 325 326 plat_dat->bsp_priv = dwmac; 327 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed; 328 329 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 330 331 if (!ret) { 332 struct net_device *ndev = platform_get_drvdata(pdev); 333 struct stmmac_priv *stpriv = netdev_priv(ndev); 334 335 /* The socfpga driver needs to control the stmmac reset to 336 * set the phy mode. Create a copy of the core reset handel 337 * so it can be used by the driver later. 338 */ 339 dwmac->stmmac_rst = stpriv->stmmac_rst; 340 341 ret = socfpga_dwmac_set_phy_mode(dwmac); 342 } 343 344 return ret; 345 } 346 347 #ifdef CONFIG_PM_SLEEP 348 static int socfpga_dwmac_resume(struct device *dev) 349 { 350 struct net_device *ndev = dev_get_drvdata(dev); 351 struct stmmac_priv *priv = netdev_priv(ndev); 352 353 socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv); 354 355 /* Before the enet controller is suspended, the phy is suspended. 356 * This causes the phy clock to be gated. The enet controller is 357 * resumed before the phy, so the clock is still gated "off" when 358 * the enet controller is resumed. This code makes sure the phy 359 * is "resumed" before reinitializing the enet controller since 360 * the enet controller depends on an active phy clock to complete 361 * a DMA reset. A DMA reset will "time out" if executed 362 * with no phy clock input on the Synopsys enet controller. 363 * Verified through Synopsys Case #8000711656. 364 * 365 * Note that the phy clock is also gated when the phy is isolated. 366 * Phy "suspend" and "isolate" controls are located in phy basic 367 * control register 0, and can be modified by the phy driver 368 * framework. 369 */ 370 if (ndev->phydev) 371 phy_resume(ndev->phydev); 372 373 return stmmac_resume(dev); 374 } 375 #endif /* CONFIG_PM_SLEEP */ 376 377 static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend, 378 socfpga_dwmac_resume); 379 380 static const struct of_device_id socfpga_dwmac_match[] = { 381 { .compatible = "altr,socfpga-stmmac" }, 382 { } 383 }; 384 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); 385 386 static struct platform_driver socfpga_dwmac_driver = { 387 .probe = socfpga_dwmac_probe, 388 .remove = stmmac_pltfr_remove, 389 .driver = { 390 .name = "socfpga-dwmac", 391 .pm = &socfpga_dwmac_pm_ops, 392 .of_match_table = socfpga_dwmac_match, 393 }, 394 }; 395 module_platform_driver(socfpga_dwmac_driver); 396 397 MODULE_LICENSE("GPL v2"); 398