1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright Altera Corporation (C) 2014. All rights reserved. 3 * 4 * Adopted from dwmac-sti.c 5 */ 6 7 #include <linux/mfd/altera-sysmgr.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 #include <linux/of_net.h> 11 #include <linux/phy.h> 12 #include <linux/regmap.h> 13 #include <linux/reset.h> 14 #include <linux/stmmac.h> 15 16 #include "stmmac.h" 17 #include "stmmac_platform.h" 18 19 #include "altr_tse_pcs.h" 20 21 #define SGMII_ADAPTER_CTRL_REG 0x00 22 #define SGMII_ADAPTER_DISABLE 0x0001 23 24 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 25 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 26 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 27 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 28 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 29 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010 30 #define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000100 31 32 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028 33 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004 34 #define SYSMGR_FPGAINTF_EMAC_REG 0x00000070 35 #define SYSMGR_FPGAINTF_EMAC_BIT 0x1 36 37 #define EMAC_SPLITTER_CTRL_REG 0x0 38 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3 39 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2 40 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3 41 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0 42 43 struct socfpga_dwmac; 44 struct socfpga_dwmac_ops { 45 int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv); 46 }; 47 48 struct socfpga_dwmac { 49 int interface; 50 u32 reg_offset; 51 u32 reg_shift; 52 struct device *dev; 53 struct regmap *sys_mgr_base_addr; 54 struct reset_control *stmmac_rst; 55 struct reset_control *stmmac_ocp_rst; 56 void __iomem *splitter_base; 57 bool f2h_ptp_ref_clk; 58 struct tse_pcs pcs; 59 const struct socfpga_dwmac_ops *ops; 60 }; 61 62 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed) 63 { 64 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv; 65 void __iomem *splitter_base = dwmac->splitter_base; 66 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; 67 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; 68 struct device *dev = dwmac->dev; 69 struct net_device *ndev = dev_get_drvdata(dev); 70 struct phy_device *phy_dev = ndev->phydev; 71 u32 val; 72 73 if ((tse_pcs_base) && (sgmii_adapter_base)) 74 writew(SGMII_ADAPTER_DISABLE, 75 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); 76 77 if (splitter_base) { 78 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG); 79 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK; 80 81 switch (speed) { 82 case 1000: 83 val |= EMAC_SPLITTER_CTRL_SPEED_1000; 84 break; 85 case 100: 86 val |= EMAC_SPLITTER_CTRL_SPEED_100; 87 break; 88 case 10: 89 val |= EMAC_SPLITTER_CTRL_SPEED_10; 90 break; 91 default: 92 return; 93 } 94 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG); 95 } 96 97 if (tse_pcs_base && sgmii_adapter_base) 98 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); 99 } 100 101 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) 102 { 103 struct device_node *np = dev->of_node; 104 struct regmap *sys_mgr_base_addr; 105 u32 reg_offset, reg_shift; 106 int ret, index; 107 struct device_node *np_splitter = NULL; 108 struct device_node *np_sgmii_adapter = NULL; 109 struct resource res_splitter; 110 struct resource res_tse_pcs; 111 struct resource res_sgmii_adapter; 112 113 dwmac->interface = of_get_phy_mode(np); 114 115 sys_mgr_base_addr = 116 altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); 117 if (IS_ERR(sys_mgr_base_addr)) { 118 dev_info(dev, "No sysmgr-syscon node found\n"); 119 return PTR_ERR(sys_mgr_base_addr); 120 } 121 122 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); 123 if (ret) { 124 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); 125 return -EINVAL; 126 } 127 128 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); 129 if (ret) { 130 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); 131 return -EINVAL; 132 } 133 134 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk"); 135 136 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); 137 if (np_splitter) { 138 ret = of_address_to_resource(np_splitter, 0, &res_splitter); 139 of_node_put(np_splitter); 140 if (ret) { 141 dev_info(dev, "Missing emac splitter address\n"); 142 return -EINVAL; 143 } 144 145 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); 146 if (IS_ERR(dwmac->splitter_base)) { 147 dev_info(dev, "Failed to mapping emac splitter\n"); 148 return PTR_ERR(dwmac->splitter_base); 149 } 150 } 151 152 np_sgmii_adapter = of_parse_phandle(np, 153 "altr,gmii-to-sgmii-converter", 0); 154 if (np_sgmii_adapter) { 155 index = of_property_match_string(np_sgmii_adapter, "reg-names", 156 "hps_emac_interface_splitter_avalon_slave"); 157 158 if (index >= 0) { 159 if (of_address_to_resource(np_sgmii_adapter, index, 160 &res_splitter)) { 161 dev_err(dev, 162 "%s: ERROR: missing emac splitter address\n", 163 __func__); 164 ret = -EINVAL; 165 goto err_node_put; 166 } 167 168 dwmac->splitter_base = 169 devm_ioremap_resource(dev, &res_splitter); 170 171 if (IS_ERR(dwmac->splitter_base)) { 172 ret = PTR_ERR(dwmac->splitter_base); 173 goto err_node_put; 174 } 175 } 176 177 index = of_property_match_string(np_sgmii_adapter, "reg-names", 178 "gmii_to_sgmii_adapter_avalon_slave"); 179 180 if (index >= 0) { 181 if (of_address_to_resource(np_sgmii_adapter, index, 182 &res_sgmii_adapter)) { 183 dev_err(dev, 184 "%s: ERROR: failed mapping adapter\n", 185 __func__); 186 ret = -EINVAL; 187 goto err_node_put; 188 } 189 190 dwmac->pcs.sgmii_adapter_base = 191 devm_ioremap_resource(dev, &res_sgmii_adapter); 192 193 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) { 194 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base); 195 goto err_node_put; 196 } 197 } 198 199 index = of_property_match_string(np_sgmii_adapter, "reg-names", 200 "eth_tse_control_port"); 201 202 if (index >= 0) { 203 if (of_address_to_resource(np_sgmii_adapter, index, 204 &res_tse_pcs)) { 205 dev_err(dev, 206 "%s: ERROR: failed mapping tse control port\n", 207 __func__); 208 ret = -EINVAL; 209 goto err_node_put; 210 } 211 212 dwmac->pcs.tse_pcs_base = 213 devm_ioremap_resource(dev, &res_tse_pcs); 214 215 if (IS_ERR(dwmac->pcs.tse_pcs_base)) { 216 ret = PTR_ERR(dwmac->pcs.tse_pcs_base); 217 goto err_node_put; 218 } 219 } 220 } 221 dwmac->reg_offset = reg_offset; 222 dwmac->reg_shift = reg_shift; 223 dwmac->sys_mgr_base_addr = sys_mgr_base_addr; 224 dwmac->dev = dev; 225 of_node_put(np_sgmii_adapter); 226 227 return 0; 228 229 err_node_put: 230 of_node_put(np_sgmii_adapter); 231 return ret; 232 } 233 234 static int socfpga_set_phy_mode_common(int phymode, u32 *val) 235 { 236 switch (phymode) { 237 case PHY_INTERFACE_MODE_RGMII: 238 case PHY_INTERFACE_MODE_RGMII_ID: 239 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 240 break; 241 case PHY_INTERFACE_MODE_MII: 242 case PHY_INTERFACE_MODE_GMII: 243 case PHY_INTERFACE_MODE_SGMII: 244 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 245 break; 246 case PHY_INTERFACE_MODE_RMII: 247 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; 248 break; 249 default: 250 return -EINVAL; 251 } 252 return 0; 253 } 254 255 static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac) 256 { 257 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 258 int phymode = dwmac->interface; 259 u32 reg_offset = dwmac->reg_offset; 260 u32 reg_shift = dwmac->reg_shift; 261 u32 ctrl, val, module; 262 263 if (socfpga_set_phy_mode_common(phymode, &val)) { 264 dev_err(dwmac->dev, "bad phy mode %d\n", phymode); 265 return -EINVAL; 266 } 267 268 /* Overwrite val to GMII if splitter core is enabled. The phymode here 269 * is the actual phy mode on phy hardware, but phy interface from 270 * EMAC core is GMII. 271 */ 272 if (dwmac->splitter_base) 273 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 274 275 /* Assert reset to the enet controller before changing the phy mode */ 276 reset_control_assert(dwmac->stmmac_ocp_rst); 277 reset_control_assert(dwmac->stmmac_rst); 278 279 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 280 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); 281 ctrl |= val << reg_shift; 282 283 if (dwmac->f2h_ptp_ref_clk || 284 phymode == PHY_INTERFACE_MODE_MII || 285 phymode == PHY_INTERFACE_MODE_GMII || 286 phymode == PHY_INTERFACE_MODE_SGMII) { 287 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); 288 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 289 &module); 290 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); 291 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 292 module); 293 } else { 294 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); 295 } 296 297 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 298 299 /* Deassert reset for the phy configuration to be sampled by 300 * the enet controller, and operation to start in requested mode 301 */ 302 reset_control_deassert(dwmac->stmmac_ocp_rst); 303 reset_control_deassert(dwmac->stmmac_rst); 304 if (phymode == PHY_INTERFACE_MODE_SGMII) { 305 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { 306 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); 307 return -EINVAL; 308 } 309 } 310 311 return 0; 312 } 313 314 static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac) 315 { 316 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 317 int phymode = dwmac->interface; 318 u32 reg_offset = dwmac->reg_offset; 319 u32 reg_shift = dwmac->reg_shift; 320 u32 ctrl, val, module; 321 322 if (socfpga_set_phy_mode_common(phymode, &val)) 323 return -EINVAL; 324 325 /* Overwrite val to GMII if splitter core is enabled. The phymode here 326 * is the actual phy mode on phy hardware, but phy interface from 327 * EMAC core is GMII. 328 */ 329 if (dwmac->splitter_base) 330 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 331 332 /* Assert reset to the enet controller before changing the phy mode */ 333 reset_control_assert(dwmac->stmmac_ocp_rst); 334 reset_control_assert(dwmac->stmmac_rst); 335 336 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 337 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK); 338 ctrl |= val; 339 340 if (dwmac->f2h_ptp_ref_clk || 341 phymode == PHY_INTERFACE_MODE_MII || 342 phymode == PHY_INTERFACE_MODE_GMII || 343 phymode == PHY_INTERFACE_MODE_SGMII) { 344 ctrl |= SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK; 345 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG, 346 &module); 347 module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift); 348 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG, 349 module); 350 } else { 351 ctrl &= ~SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK; 352 } 353 354 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 355 356 /* Deassert reset for the phy configuration to be sampled by 357 * the enet controller, and operation to start in requested mode 358 */ 359 reset_control_deassert(dwmac->stmmac_ocp_rst); 360 reset_control_deassert(dwmac->stmmac_rst); 361 if (phymode == PHY_INTERFACE_MODE_SGMII) { 362 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { 363 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); 364 return -EINVAL; 365 } 366 } 367 return 0; 368 } 369 370 static int socfpga_dwmac_probe(struct platform_device *pdev) 371 { 372 struct plat_stmmacenet_data *plat_dat; 373 struct stmmac_resources stmmac_res; 374 struct device *dev = &pdev->dev; 375 int ret; 376 struct socfpga_dwmac *dwmac; 377 struct net_device *ndev; 378 struct stmmac_priv *stpriv; 379 const struct socfpga_dwmac_ops *ops; 380 381 ops = device_get_match_data(&pdev->dev); 382 if (!ops) { 383 dev_err(&pdev->dev, "no of match data provided\n"); 384 return -EINVAL; 385 } 386 387 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 388 if (ret) 389 return ret; 390 391 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 392 if (IS_ERR(plat_dat)) 393 return PTR_ERR(plat_dat); 394 395 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL); 396 if (!dwmac) { 397 ret = -ENOMEM; 398 goto err_remove_config_dt; 399 } 400 401 dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp"); 402 if (IS_ERR(dwmac->stmmac_ocp_rst)) { 403 ret = PTR_ERR(dwmac->stmmac_ocp_rst); 404 dev_err(dev, "error getting reset control of ocp %d\n", ret); 405 goto err_remove_config_dt; 406 } 407 408 reset_control_deassert(dwmac->stmmac_ocp_rst); 409 410 ret = socfpga_dwmac_parse_data(dwmac, dev); 411 if (ret) { 412 dev_err(dev, "Unable to parse OF data\n"); 413 goto err_remove_config_dt; 414 } 415 416 dwmac->ops = ops; 417 plat_dat->bsp_priv = dwmac; 418 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed; 419 420 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 421 if (ret) 422 goto err_remove_config_dt; 423 424 ndev = platform_get_drvdata(pdev); 425 stpriv = netdev_priv(ndev); 426 427 /* The socfpga driver needs to control the stmmac reset to set the phy 428 * mode. Create a copy of the core reset handle so it can be used by 429 * the driver later. 430 */ 431 dwmac->stmmac_rst = stpriv->plat->stmmac_rst; 432 433 ret = ops->set_phy_mode(dwmac); 434 if (ret) 435 goto err_dvr_remove; 436 437 return 0; 438 439 err_dvr_remove: 440 stmmac_dvr_remove(&pdev->dev); 441 err_remove_config_dt: 442 stmmac_remove_config_dt(pdev, plat_dat); 443 444 return ret; 445 } 446 447 #ifdef CONFIG_PM_SLEEP 448 static int socfpga_dwmac_resume(struct device *dev) 449 { 450 struct net_device *ndev = dev_get_drvdata(dev); 451 struct stmmac_priv *priv = netdev_priv(ndev); 452 struct socfpga_dwmac *dwmac_priv = get_stmmac_bsp_priv(dev); 453 454 dwmac_priv->ops->set_phy_mode(priv->plat->bsp_priv); 455 456 /* Before the enet controller is suspended, the phy is suspended. 457 * This causes the phy clock to be gated. The enet controller is 458 * resumed before the phy, so the clock is still gated "off" when 459 * the enet controller is resumed. This code makes sure the phy 460 * is "resumed" before reinitializing the enet controller since 461 * the enet controller depends on an active phy clock to complete 462 * a DMA reset. A DMA reset will "time out" if executed 463 * with no phy clock input on the Synopsys enet controller. 464 * Verified through Synopsys Case #8000711656. 465 * 466 * Note that the phy clock is also gated when the phy is isolated. 467 * Phy "suspend" and "isolate" controls are located in phy basic 468 * control register 0, and can be modified by the phy driver 469 * framework. 470 */ 471 if (ndev->phydev) 472 phy_resume(ndev->phydev); 473 474 return stmmac_resume(dev); 475 } 476 #endif /* CONFIG_PM_SLEEP */ 477 478 static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend, 479 socfpga_dwmac_resume); 480 481 static const struct socfpga_dwmac_ops socfpga_gen5_ops = { 482 .set_phy_mode = socfpga_gen5_set_phy_mode, 483 }; 484 485 static const struct socfpga_dwmac_ops socfpga_gen10_ops = { 486 .set_phy_mode = socfpga_gen10_set_phy_mode, 487 }; 488 489 static const struct of_device_id socfpga_dwmac_match[] = { 490 { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops }, 491 { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops }, 492 { } 493 }; 494 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); 495 496 static struct platform_driver socfpga_dwmac_driver = { 497 .probe = socfpga_dwmac_probe, 498 .remove = stmmac_pltfr_remove, 499 .driver = { 500 .name = "socfpga-dwmac", 501 .pm = &socfpga_dwmac_pm_ops, 502 .of_match_table = socfpga_dwmac_match, 503 }, 504 }; 505 module_platform_driver(socfpga_dwmac_driver); 506 507 MODULE_LICENSE("GPL v2"); 508