1 /* Copyright Altera Corporation (C) 2014. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License, version 2, 5 * as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * 15 * Adopted from dwmac-sti.c 16 */ 17 18 #include <linux/mfd/syscon.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/phy.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/stmmac.h> 26 27 #include "stmmac.h" 28 #include "stmmac_platform.h" 29 30 #include "altr_tse_pcs.h" 31 32 #define SGMII_ADAPTER_CTRL_REG 0x00 33 #define SGMII_ADAPTER_DISABLE 0x0001 34 35 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 36 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 37 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 38 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 39 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 40 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010 41 42 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028 43 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004 44 45 #define EMAC_SPLITTER_CTRL_REG 0x0 46 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3 47 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2 48 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3 49 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0 50 51 struct socfpga_dwmac { 52 int interface; 53 u32 reg_offset; 54 u32 reg_shift; 55 struct device *dev; 56 struct regmap *sys_mgr_base_addr; 57 struct reset_control *stmmac_rst; 58 void __iomem *splitter_base; 59 bool f2h_ptp_ref_clk; 60 struct tse_pcs pcs; 61 }; 62 63 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed) 64 { 65 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv; 66 void __iomem *splitter_base = dwmac->splitter_base; 67 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base; 68 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; 69 struct device *dev = dwmac->dev; 70 struct net_device *ndev = dev_get_drvdata(dev); 71 struct phy_device *phy_dev = ndev->phydev; 72 u32 val; 73 74 if ((tse_pcs_base) && (sgmii_adapter_base)) 75 writew(SGMII_ADAPTER_DISABLE, 76 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); 77 78 if (splitter_base) { 79 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG); 80 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK; 81 82 switch (speed) { 83 case 1000: 84 val |= EMAC_SPLITTER_CTRL_SPEED_1000; 85 break; 86 case 100: 87 val |= EMAC_SPLITTER_CTRL_SPEED_100; 88 break; 89 case 10: 90 val |= EMAC_SPLITTER_CTRL_SPEED_10; 91 break; 92 default: 93 return; 94 } 95 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG); 96 } 97 98 if (tse_pcs_base && sgmii_adapter_base) 99 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); 100 } 101 102 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) 103 { 104 struct device_node *np = dev->of_node; 105 struct regmap *sys_mgr_base_addr; 106 u32 reg_offset, reg_shift; 107 int ret, index; 108 struct device_node *np_splitter = NULL; 109 struct device_node *np_sgmii_adapter = NULL; 110 struct resource res_splitter; 111 struct resource res_tse_pcs; 112 struct resource res_sgmii_adapter; 113 114 dwmac->interface = of_get_phy_mode(np); 115 116 sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); 117 if (IS_ERR(sys_mgr_base_addr)) { 118 dev_info(dev, "No sysmgr-syscon node found\n"); 119 return PTR_ERR(sys_mgr_base_addr); 120 } 121 122 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); 123 if (ret) { 124 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); 125 return -EINVAL; 126 } 127 128 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); 129 if (ret) { 130 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); 131 return -EINVAL; 132 } 133 134 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk"); 135 136 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); 137 if (np_splitter) { 138 if (of_address_to_resource(np_splitter, 0, &res_splitter)) { 139 dev_info(dev, "Missing emac splitter address\n"); 140 return -EINVAL; 141 } 142 143 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); 144 if (IS_ERR(dwmac->splitter_base)) { 145 dev_info(dev, "Failed to mapping emac splitter\n"); 146 return PTR_ERR(dwmac->splitter_base); 147 } 148 } 149 150 np_sgmii_adapter = of_parse_phandle(np, 151 "altr,gmii-to-sgmii-converter", 0); 152 if (np_sgmii_adapter) { 153 index = of_property_match_string(np_sgmii_adapter, "reg-names", 154 "hps_emac_interface_splitter_avalon_slave"); 155 156 if (index >= 0) { 157 if (of_address_to_resource(np_sgmii_adapter, index, 158 &res_splitter)) { 159 dev_err(dev, 160 "%s: ERROR: missing emac splitter address\n", 161 __func__); 162 return -EINVAL; 163 } 164 165 dwmac->splitter_base = 166 devm_ioremap_resource(dev, &res_splitter); 167 168 if (IS_ERR(dwmac->splitter_base)) 169 return PTR_ERR(dwmac->splitter_base); 170 } 171 172 index = of_property_match_string(np_sgmii_adapter, "reg-names", 173 "gmii_to_sgmii_adapter_avalon_slave"); 174 175 if (index >= 0) { 176 if (of_address_to_resource(np_sgmii_adapter, index, 177 &res_sgmii_adapter)) { 178 dev_err(dev, 179 "%s: ERROR: failed mapping adapter\n", 180 __func__); 181 return -EINVAL; 182 } 183 184 dwmac->pcs.sgmii_adapter_base = 185 devm_ioremap_resource(dev, &res_sgmii_adapter); 186 187 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) 188 return PTR_ERR(dwmac->pcs.sgmii_adapter_base); 189 } 190 191 index = of_property_match_string(np_sgmii_adapter, "reg-names", 192 "eth_tse_control_port"); 193 194 if (index >= 0) { 195 if (of_address_to_resource(np_sgmii_adapter, index, 196 &res_tse_pcs)) { 197 dev_err(dev, 198 "%s: ERROR: failed mapping tse control port\n", 199 __func__); 200 return -EINVAL; 201 } 202 203 dwmac->pcs.tse_pcs_base = 204 devm_ioremap_resource(dev, &res_tse_pcs); 205 206 if (IS_ERR(dwmac->pcs.tse_pcs_base)) 207 return PTR_ERR(dwmac->pcs.tse_pcs_base); 208 } 209 } 210 dwmac->reg_offset = reg_offset; 211 dwmac->reg_shift = reg_shift; 212 dwmac->sys_mgr_base_addr = sys_mgr_base_addr; 213 dwmac->dev = dev; 214 215 return 0; 216 } 217 218 static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) 219 { 220 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 221 int phymode = dwmac->interface; 222 u32 reg_offset = dwmac->reg_offset; 223 u32 reg_shift = dwmac->reg_shift; 224 u32 ctrl, val, module; 225 226 switch (phymode) { 227 case PHY_INTERFACE_MODE_RGMII: 228 case PHY_INTERFACE_MODE_RGMII_ID: 229 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 230 break; 231 case PHY_INTERFACE_MODE_MII: 232 case PHY_INTERFACE_MODE_GMII: 233 case PHY_INTERFACE_MODE_SGMII: 234 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 235 break; 236 default: 237 dev_err(dwmac->dev, "bad phy mode %d\n", phymode); 238 return -EINVAL; 239 } 240 241 /* Overwrite val to GMII if splitter core is enabled. The phymode here 242 * is the actual phy mode on phy hardware, but phy interface from 243 * EMAC core is GMII. 244 */ 245 if (dwmac->splitter_base) 246 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 247 248 /* Assert reset to the enet controller before changing the phy mode */ 249 if (dwmac->stmmac_rst) 250 reset_control_assert(dwmac->stmmac_rst); 251 252 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 253 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); 254 ctrl |= val << reg_shift; 255 256 if (dwmac->f2h_ptp_ref_clk) { 257 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); 258 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 259 &module); 260 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); 261 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 262 module); 263 } else { 264 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); 265 } 266 267 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 268 269 /* Deassert reset for the phy configuration to be sampled by 270 * the enet controller, and operation to start in requested mode 271 */ 272 if (dwmac->stmmac_rst) 273 reset_control_deassert(dwmac->stmmac_rst); 274 if (phymode == PHY_INTERFACE_MODE_SGMII) { 275 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) { 276 dev_err(dwmac->dev, "Unable to initialize TSE PCS"); 277 return -EINVAL; 278 } 279 } 280 281 return 0; 282 } 283 284 static int socfpga_dwmac_probe(struct platform_device *pdev) 285 { 286 struct plat_stmmacenet_data *plat_dat; 287 struct stmmac_resources stmmac_res; 288 struct device *dev = &pdev->dev; 289 int ret; 290 struct socfpga_dwmac *dwmac; 291 292 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 293 if (ret) 294 return ret; 295 296 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 297 if (IS_ERR(plat_dat)) 298 return PTR_ERR(plat_dat); 299 300 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL); 301 if (!dwmac) 302 return -ENOMEM; 303 304 ret = socfpga_dwmac_parse_data(dwmac, dev); 305 if (ret) { 306 dev_err(dev, "Unable to parse OF data\n"); 307 return ret; 308 } 309 310 plat_dat->bsp_priv = dwmac; 311 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed; 312 313 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 314 315 if (!ret) { 316 struct net_device *ndev = platform_get_drvdata(pdev); 317 struct stmmac_priv *stpriv = netdev_priv(ndev); 318 319 /* The socfpga driver needs to control the stmmac reset to 320 * set the phy mode. Create a copy of the core reset handel 321 * so it can be used by the driver later. 322 */ 323 dwmac->stmmac_rst = stpriv->stmmac_rst; 324 325 ret = socfpga_dwmac_set_phy_mode(dwmac); 326 } 327 328 return ret; 329 } 330 331 #ifdef CONFIG_PM_SLEEP 332 static int socfpga_dwmac_resume(struct device *dev) 333 { 334 struct net_device *ndev = dev_get_drvdata(dev); 335 struct stmmac_priv *priv = netdev_priv(ndev); 336 337 socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv); 338 339 /* Before the enet controller is suspended, the phy is suspended. 340 * This causes the phy clock to be gated. The enet controller is 341 * resumed before the phy, so the clock is still gated "off" when 342 * the enet controller is resumed. This code makes sure the phy 343 * is "resumed" before reinitializing the enet controller since 344 * the enet controller depends on an active phy clock to complete 345 * a DMA reset. A DMA reset will "time out" if executed 346 * with no phy clock input on the Synopsys enet controller. 347 * Verified through Synopsys Case #8000711656. 348 * 349 * Note that the phy clock is also gated when the phy is isolated. 350 * Phy "suspend" and "isolate" controls are located in phy basic 351 * control register 0, and can be modified by the phy driver 352 * framework. 353 */ 354 if (priv->phydev) 355 phy_resume(priv->phydev); 356 357 return stmmac_resume(dev); 358 } 359 #endif /* CONFIG_PM_SLEEP */ 360 361 static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend, 362 socfpga_dwmac_resume); 363 364 static const struct of_device_id socfpga_dwmac_match[] = { 365 { .compatible = "altr,socfpga-stmmac" }, 366 { } 367 }; 368 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); 369 370 static struct platform_driver socfpga_dwmac_driver = { 371 .probe = socfpga_dwmac_probe, 372 .remove = stmmac_pltfr_remove, 373 .driver = { 374 .name = "socfpga-dwmac", 375 .pm = &socfpga_dwmac_pm_ops, 376 .of_match_table = socfpga_dwmac_match, 377 }, 378 }; 379 module_platform_driver(socfpga_dwmac_driver); 380 381 MODULE_LICENSE("GPL v2"); 382