1 /* Copyright Altera Corporation (C) 2014. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License, version 2, 5 * as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * 15 * Adopted from dwmac-sti.c 16 */ 17 18 #include <linux/mfd/syscon.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_net.h> 22 #include <linux/phy.h> 23 #include <linux/regmap.h> 24 #include <linux/reset.h> 25 #include <linux/stmmac.h> 26 27 #include "stmmac.h" 28 #include "stmmac_platform.h" 29 30 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 33 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2 34 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003 35 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010 36 37 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028 38 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004 39 40 #define EMAC_SPLITTER_CTRL_REG 0x0 41 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3 42 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2 43 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3 44 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0 45 46 struct socfpga_dwmac { 47 int interface; 48 u32 reg_offset; 49 u32 reg_shift; 50 struct device *dev; 51 struct regmap *sys_mgr_base_addr; 52 struct reset_control *stmmac_rst; 53 void __iomem *splitter_base; 54 bool f2h_ptp_ref_clk; 55 }; 56 57 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed) 58 { 59 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv; 60 void __iomem *splitter_base = dwmac->splitter_base; 61 u32 val; 62 63 if (!splitter_base) 64 return; 65 66 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG); 67 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK; 68 69 switch (speed) { 70 case 1000: 71 val |= EMAC_SPLITTER_CTRL_SPEED_1000; 72 break; 73 case 100: 74 val |= EMAC_SPLITTER_CTRL_SPEED_100; 75 break; 76 case 10: 77 val |= EMAC_SPLITTER_CTRL_SPEED_10; 78 break; 79 default: 80 return; 81 } 82 83 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG); 84 } 85 86 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev) 87 { 88 struct device_node *np = dev->of_node; 89 struct regmap *sys_mgr_base_addr; 90 u32 reg_offset, reg_shift; 91 int ret; 92 struct device_node *np_splitter; 93 struct resource res_splitter; 94 95 dwmac->interface = of_get_phy_mode(np); 96 97 sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); 98 if (IS_ERR(sys_mgr_base_addr)) { 99 dev_info(dev, "No sysmgr-syscon node found\n"); 100 return PTR_ERR(sys_mgr_base_addr); 101 } 102 103 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); 104 if (ret) { 105 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n"); 106 return -EINVAL; 107 } 108 109 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); 110 if (ret) { 111 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n"); 112 return -EINVAL; 113 } 114 115 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk"); 116 117 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0); 118 if (np_splitter) { 119 if (of_address_to_resource(np_splitter, 0, &res_splitter)) { 120 dev_info(dev, "Missing emac splitter address\n"); 121 return -EINVAL; 122 } 123 124 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter); 125 if (IS_ERR(dwmac->splitter_base)) { 126 dev_info(dev, "Failed to mapping emac splitter\n"); 127 return PTR_ERR(dwmac->splitter_base); 128 } 129 } 130 131 dwmac->reg_offset = reg_offset; 132 dwmac->reg_shift = reg_shift; 133 dwmac->sys_mgr_base_addr = sys_mgr_base_addr; 134 dwmac->dev = dev; 135 136 return 0; 137 } 138 139 static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac) 140 { 141 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; 142 int phymode = dwmac->interface; 143 u32 reg_offset = dwmac->reg_offset; 144 u32 reg_shift = dwmac->reg_shift; 145 u32 ctrl, val, module; 146 147 switch (phymode) { 148 case PHY_INTERFACE_MODE_RGMII: 149 case PHY_INTERFACE_MODE_RGMII_ID: 150 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; 151 break; 152 case PHY_INTERFACE_MODE_MII: 153 case PHY_INTERFACE_MODE_GMII: 154 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 155 break; 156 default: 157 dev_err(dwmac->dev, "bad phy mode %d\n", phymode); 158 return -EINVAL; 159 } 160 161 /* Overwrite val to GMII if splitter core is enabled. The phymode here 162 * is the actual phy mode on phy hardware, but phy interface from 163 * EMAC core is GMII. 164 */ 165 if (dwmac->splitter_base) 166 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; 167 168 /* Assert reset to the enet controller before changing the phy mode */ 169 if (dwmac->stmmac_rst) 170 reset_control_assert(dwmac->stmmac_rst); 171 172 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); 173 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); 174 ctrl |= val << reg_shift; 175 176 if (dwmac->f2h_ptp_ref_clk) { 177 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); 178 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 179 &module); 180 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); 181 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, 182 module); 183 } else { 184 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); 185 } 186 187 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); 188 189 /* Deassert reset for the phy configuration to be sampled by 190 * the enet controller, and operation to start in requested mode 191 */ 192 if (dwmac->stmmac_rst) 193 reset_control_deassert(dwmac->stmmac_rst); 194 195 return 0; 196 } 197 198 static int socfpga_dwmac_init(struct platform_device *pdev, void *priv) 199 { 200 struct socfpga_dwmac *dwmac = priv; 201 202 /* Setup the phy mode in the system manager registers according to 203 * devicetree configuration 204 */ 205 return socfpga_dwmac_setup(dwmac); 206 } 207 208 static int socfpga_dwmac_probe(struct platform_device *pdev) 209 { 210 struct plat_stmmacenet_data *plat_dat; 211 struct stmmac_resources stmmac_res; 212 struct device *dev = &pdev->dev; 213 int ret; 214 struct socfpga_dwmac *dwmac; 215 216 ret = stmmac_get_platform_resources(pdev, &stmmac_res); 217 if (ret) 218 return ret; 219 220 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); 221 if (IS_ERR(plat_dat)) 222 return PTR_ERR(plat_dat); 223 224 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL); 225 if (!dwmac) 226 return -ENOMEM; 227 228 ret = socfpga_dwmac_parse_data(dwmac, dev); 229 if (ret) { 230 dev_err(dev, "Unable to parse OF data\n"); 231 return ret; 232 } 233 234 plat_dat->bsp_priv = dwmac; 235 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed; 236 237 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); 238 if (!ret) { 239 struct net_device *ndev = platform_get_drvdata(pdev); 240 struct stmmac_priv *stpriv = netdev_priv(ndev); 241 242 /* The socfpga driver needs to control the stmmac reset to 243 * set the phy mode. Create a copy of the core reset handel 244 * so it can be used by the driver later. 245 */ 246 dwmac->stmmac_rst = stpriv->stmmac_rst; 247 248 ret = socfpga_dwmac_init(pdev, dwmac); 249 } 250 251 return ret; 252 } 253 254 #ifdef CONFIG_PM_SLEEP 255 static int socfpga_dwmac_resume(struct device *dev) 256 { 257 struct platform_device *pdev = to_platform_device(dev); 258 struct net_device *ndev = dev_get_drvdata(dev); 259 struct stmmac_priv *priv = netdev_priv(ndev); 260 261 socfpga_dwmac_init(pdev, priv->plat->bsp_priv); 262 263 /* Before the enet controller is suspended, the phy is suspended. 264 * This causes the phy clock to be gated. The enet controller is 265 * resumed before the phy, so the clock is still gated "off" when 266 * the enet controller is resumed. This code makes sure the phy 267 * is "resumed" before reinitializing the enet controller since 268 * the enet controller depends on an active phy clock to complete 269 * a DMA reset. A DMA reset will "time out" if executed 270 * with no phy clock input on the Synopsys enet controller. 271 * Verified through Synopsys Case #8000711656. 272 * 273 * Note that the phy clock is also gated when the phy is isolated. 274 * Phy "suspend" and "isolate" controls are located in phy basic 275 * control register 0, and can be modified by the phy driver 276 * framework. 277 */ 278 if (priv->phydev) 279 phy_resume(priv->phydev); 280 281 return stmmac_resume(dev); 282 } 283 #endif /* CONFIG_PM_SLEEP */ 284 285 SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend, socfpga_dwmac_resume); 286 287 static const struct of_device_id socfpga_dwmac_match[] = { 288 { .compatible = "altr,socfpga-stmmac" }, 289 { } 290 }; 291 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match); 292 293 static struct platform_driver socfpga_dwmac_driver = { 294 .probe = socfpga_dwmac_probe, 295 .remove = stmmac_pltfr_remove, 296 .driver = { 297 .name = "socfpga-dwmac", 298 .pm = &socfpga_dwmac_pm_ops, 299 .of_match_table = socfpga_dwmac_match, 300 }, 301 }; 302 module_platform_driver(socfpga_dwmac_driver); 303 304 MODULE_LICENSE("GPL v2"); 305