1 /**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2013 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/delay.h> 16 #include <linux/notifier.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/in.h> 20 #include <linux/ethtool.h> 21 #include <linux/topology.h> 22 #include <linux/gfp.h> 23 #include <linux/aer.h> 24 #include <linux/interrupt.h> 25 #include "net_driver.h" 26 #include "efx.h" 27 #include "nic.h" 28 #include "selftest.h" 29 30 #include "mcdi.h" 31 #include "workarounds.h" 32 33 /************************************************************************** 34 * 35 * Type name strings 36 * 37 ************************************************************************** 38 */ 39 40 /* Loopback mode names (see LOOPBACK_MODE()) */ 41 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; 42 const char *const efx_loopback_mode_names[] = { 43 [LOOPBACK_NONE] = "NONE", 44 [LOOPBACK_DATA] = "DATAPATH", 45 [LOOPBACK_GMAC] = "GMAC", 46 [LOOPBACK_XGMII] = "XGMII", 47 [LOOPBACK_XGXS] = "XGXS", 48 [LOOPBACK_XAUI] = "XAUI", 49 [LOOPBACK_GMII] = "GMII", 50 [LOOPBACK_SGMII] = "SGMII", 51 [LOOPBACK_XGBR] = "XGBR", 52 [LOOPBACK_XFI] = "XFI", 53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR", 54 [LOOPBACK_GMII_FAR] = "GMII_FAR", 55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR", 56 [LOOPBACK_XFI_FAR] = "XFI_FAR", 57 [LOOPBACK_GPHY] = "GPHY", 58 [LOOPBACK_PHYXS] = "PHYXS", 59 [LOOPBACK_PCS] = "PCS", 60 [LOOPBACK_PMAPMD] = "PMA/PMD", 61 [LOOPBACK_XPORT] = "XPORT", 62 [LOOPBACK_XGMII_WS] = "XGMII_WS", 63 [LOOPBACK_XAUI_WS] = "XAUI_WS", 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", 65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", 66 [LOOPBACK_GMII_WS] = "GMII_WS", 67 [LOOPBACK_XFI_WS] = "XFI_WS", 68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS", 70 }; 71 72 const unsigned int efx_reset_type_max = RESET_TYPE_MAX; 73 const char *const efx_reset_type_names[] = { 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE", 75 [RESET_TYPE_ALL] = "ALL", 76 [RESET_TYPE_RECOVER_OR_ALL] = "RECOVER_OR_ALL", 77 [RESET_TYPE_WORLD] = "WORLD", 78 [RESET_TYPE_RECOVER_OR_DISABLE] = "RECOVER_OR_DISABLE", 79 [RESET_TYPE_DISABLE] = "DISABLE", 80 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", 81 [RESET_TYPE_INT_ERROR] = "INT_ERROR", 82 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", 83 [RESET_TYPE_DMA_ERROR] = "DMA_ERROR", 84 [RESET_TYPE_TX_SKIP] = "TX_SKIP", 85 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", 86 }; 87 88 /* Reset workqueue. If any NIC has a hardware failure then a reset will be 89 * queued onto this work queue. This is not a per-nic work queue, because 90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. 91 */ 92 static struct workqueue_struct *reset_workqueue; 93 94 /************************************************************************** 95 * 96 * Configurable values 97 * 98 *************************************************************************/ 99 100 /* 101 * Use separate channels for TX and RX events 102 * 103 * Set this to 1 to use separate channels for TX and RX. It allows us 104 * to control interrupt affinity separately for TX and RX. 105 * 106 * This is only used in MSI-X interrupt mode 107 */ 108 static bool separate_tx_channels; 109 module_param(separate_tx_channels, bool, 0444); 110 MODULE_PARM_DESC(separate_tx_channels, 111 "Use separate channels for TX and RX"); 112 113 /* This is the weight assigned to each of the (per-channel) virtual 114 * NAPI devices. 115 */ 116 static int napi_weight = 64; 117 118 /* This is the time (in jiffies) between invocations of the hardware 119 * monitor. 120 * On Falcon-based NICs, this will: 121 * - Check the on-board hardware monitor; 122 * - Poll the link state and reconfigure the hardware as necessary. 123 * On Siena-based NICs for power systems with EEH support, this will give EEH a 124 * chance to start. 125 */ 126 static unsigned int efx_monitor_interval = 1 * HZ; 127 128 /* Initial interrupt moderation settings. They can be modified after 129 * module load with ethtool. 130 * 131 * The default for RX should strike a balance between increasing the 132 * round-trip latency and reducing overhead. 133 */ 134 static unsigned int rx_irq_mod_usec = 60; 135 136 /* Initial interrupt moderation settings. They can be modified after 137 * module load with ethtool. 138 * 139 * This default is chosen to ensure that a 10G link does not go idle 140 * while a TX queue is stopped after it has become full. A queue is 141 * restarted when it drops below half full. The time this takes (assuming 142 * worst case 3 descriptors per packet and 1024 descriptors) is 143 * 512 / 3 * 1.2 = 205 usec. 144 */ 145 static unsigned int tx_irq_mod_usec = 150; 146 147 /* This is the first interrupt mode to try out of: 148 * 0 => MSI-X 149 * 1 => MSI 150 * 2 => legacy 151 */ 152 static unsigned int interrupt_mode; 153 154 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 155 * i.e. the number of CPUs among which we may distribute simultaneous 156 * interrupt handling. 157 * 158 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 159 * The default (0) means to assign an interrupt to each core. 160 */ 161 static unsigned int rss_cpus; 162 module_param(rss_cpus, uint, 0444); 163 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 164 165 static bool phy_flash_cfg; 166 module_param(phy_flash_cfg, bool, 0644); 167 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); 168 169 static unsigned irq_adapt_low_thresh = 8000; 170 module_param(irq_adapt_low_thresh, uint, 0644); 171 MODULE_PARM_DESC(irq_adapt_low_thresh, 172 "Threshold score for reducing IRQ moderation"); 173 174 static unsigned irq_adapt_high_thresh = 16000; 175 module_param(irq_adapt_high_thresh, uint, 0644); 176 MODULE_PARM_DESC(irq_adapt_high_thresh, 177 "Threshold score for increasing IRQ moderation"); 178 179 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 180 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 181 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | 182 NETIF_MSG_TX_ERR | NETIF_MSG_HW); 183 module_param(debug, uint, 0); 184 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); 185 186 /************************************************************************** 187 * 188 * Utility functions and prototypes 189 * 190 *************************************************************************/ 191 192 static int efx_soft_enable_interrupts(struct efx_nic *efx); 193 static void efx_soft_disable_interrupts(struct efx_nic *efx); 194 static void efx_remove_channel(struct efx_channel *channel); 195 static void efx_remove_channels(struct efx_nic *efx); 196 static const struct efx_channel_type efx_default_channel_type; 197 static void efx_remove_port(struct efx_nic *efx); 198 static void efx_init_napi_channel(struct efx_channel *channel); 199 static void efx_fini_napi(struct efx_nic *efx); 200 static void efx_fini_napi_channel(struct efx_channel *channel); 201 static void efx_fini_struct(struct efx_nic *efx); 202 static void efx_start_all(struct efx_nic *efx); 203 static void efx_stop_all(struct efx_nic *efx); 204 205 #define EFX_ASSERT_RESET_SERIALISED(efx) \ 206 do { \ 207 if ((efx->state == STATE_READY) || \ 208 (efx->state == STATE_RECOVERY) || \ 209 (efx->state == STATE_DISABLED)) \ 210 ASSERT_RTNL(); \ 211 } while (0) 212 213 static int efx_check_disabled(struct efx_nic *efx) 214 { 215 if (efx->state == STATE_DISABLED || efx->state == STATE_RECOVERY) { 216 netif_err(efx, drv, efx->net_dev, 217 "device is disabled due to earlier errors\n"); 218 return -EIO; 219 } 220 return 0; 221 } 222 223 /************************************************************************** 224 * 225 * Event queue processing 226 * 227 *************************************************************************/ 228 229 /* Process channel's event queue 230 * 231 * This function is responsible for processing the event queue of a 232 * single channel. The caller must guarantee that this function will 233 * never be concurrently called more than once on the same channel, 234 * though different channels may be being processed concurrently. 235 */ 236 static int efx_process_channel(struct efx_channel *channel, int budget) 237 { 238 int spent; 239 240 if (unlikely(!channel->enabled)) 241 return 0; 242 243 spent = efx_nic_process_eventq(channel, budget); 244 if (spent && efx_channel_has_rx_queue(channel)) { 245 struct efx_rx_queue *rx_queue = 246 efx_channel_get_rx_queue(channel); 247 248 efx_rx_flush_packet(channel); 249 efx_fast_push_rx_descriptors(rx_queue); 250 } 251 252 return spent; 253 } 254 255 /* NAPI poll handler 256 * 257 * NAPI guarantees serialisation of polls of the same device, which 258 * provides the guarantee required by efx_process_channel(). 259 */ 260 static int efx_poll(struct napi_struct *napi, int budget) 261 { 262 struct efx_channel *channel = 263 container_of(napi, struct efx_channel, napi_str); 264 struct efx_nic *efx = channel->efx; 265 int spent; 266 267 netif_vdbg(efx, intr, efx->net_dev, 268 "channel %d NAPI poll executing on CPU %d\n", 269 channel->channel, raw_smp_processor_id()); 270 271 spent = efx_process_channel(channel, budget); 272 273 if (spent < budget) { 274 if (efx_channel_has_rx_queue(channel) && 275 efx->irq_rx_adaptive && 276 unlikely(++channel->irq_count == 1000)) { 277 if (unlikely(channel->irq_mod_score < 278 irq_adapt_low_thresh)) { 279 if (channel->irq_moderation > 1) { 280 channel->irq_moderation -= 1; 281 efx->type->push_irq_moderation(channel); 282 } 283 } else if (unlikely(channel->irq_mod_score > 284 irq_adapt_high_thresh)) { 285 if (channel->irq_moderation < 286 efx->irq_rx_moderation) { 287 channel->irq_moderation += 1; 288 efx->type->push_irq_moderation(channel); 289 } 290 } 291 channel->irq_count = 0; 292 channel->irq_mod_score = 0; 293 } 294 295 efx_filter_rfs_expire(channel); 296 297 /* There is no race here; although napi_disable() will 298 * only wait for napi_complete(), this isn't a problem 299 * since efx_nic_eventq_read_ack() will have no effect if 300 * interrupts have already been disabled. 301 */ 302 napi_complete(napi); 303 efx_nic_eventq_read_ack(channel); 304 } 305 306 return spent; 307 } 308 309 /* Create event queue 310 * Event queue memory allocations are done only once. If the channel 311 * is reset, the memory buffer will be reused; this guards against 312 * errors during channel reset and also simplifies interrupt handling. 313 */ 314 static int efx_probe_eventq(struct efx_channel *channel) 315 { 316 struct efx_nic *efx = channel->efx; 317 unsigned long entries; 318 319 netif_dbg(efx, probe, efx->net_dev, 320 "chan %d create event queue\n", channel->channel); 321 322 /* Build an event queue with room for one event per tx and rx buffer, 323 * plus some extra for link state events and MCDI completions. */ 324 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 325 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 326 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 327 328 return efx_nic_probe_eventq(channel); 329 } 330 331 /* Prepare channel's event queue */ 332 static int efx_init_eventq(struct efx_channel *channel) 333 { 334 struct efx_nic *efx = channel->efx; 335 int rc; 336 337 EFX_WARN_ON_PARANOID(channel->eventq_init); 338 339 netif_dbg(efx, drv, efx->net_dev, 340 "chan %d init event queue\n", channel->channel); 341 342 rc = efx_nic_init_eventq(channel); 343 if (rc == 0) { 344 efx->type->push_irq_moderation(channel); 345 channel->eventq_read_ptr = 0; 346 channel->eventq_init = true; 347 } 348 return rc; 349 } 350 351 /* Enable event queue processing and NAPI */ 352 static void efx_start_eventq(struct efx_channel *channel) 353 { 354 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 355 "chan %d start event queue\n", channel->channel); 356 357 /* Make sure the NAPI handler sees the enabled flag set */ 358 channel->enabled = true; 359 smp_wmb(); 360 361 napi_enable(&channel->napi_str); 362 efx_nic_eventq_read_ack(channel); 363 } 364 365 /* Disable event queue processing and NAPI */ 366 static void efx_stop_eventq(struct efx_channel *channel) 367 { 368 if (!channel->enabled) 369 return; 370 371 napi_disable(&channel->napi_str); 372 channel->enabled = false; 373 } 374 375 static void efx_fini_eventq(struct efx_channel *channel) 376 { 377 if (!channel->eventq_init) 378 return; 379 380 netif_dbg(channel->efx, drv, channel->efx->net_dev, 381 "chan %d fini event queue\n", channel->channel); 382 383 efx_nic_fini_eventq(channel); 384 channel->eventq_init = false; 385 } 386 387 static void efx_remove_eventq(struct efx_channel *channel) 388 { 389 netif_dbg(channel->efx, drv, channel->efx->net_dev, 390 "chan %d remove event queue\n", channel->channel); 391 392 efx_nic_remove_eventq(channel); 393 } 394 395 /************************************************************************** 396 * 397 * Channel handling 398 * 399 *************************************************************************/ 400 401 /* Allocate and initialise a channel structure. */ 402 static struct efx_channel * 403 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 404 { 405 struct efx_channel *channel; 406 struct efx_rx_queue *rx_queue; 407 struct efx_tx_queue *tx_queue; 408 int j; 409 410 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 411 if (!channel) 412 return NULL; 413 414 channel->efx = efx; 415 channel->channel = i; 416 channel->type = &efx_default_channel_type; 417 418 for (j = 0; j < EFX_TXQ_TYPES; j++) { 419 tx_queue = &channel->tx_queue[j]; 420 tx_queue->efx = efx; 421 tx_queue->queue = i * EFX_TXQ_TYPES + j; 422 tx_queue->channel = channel; 423 } 424 425 rx_queue = &channel->rx_queue; 426 rx_queue->efx = efx; 427 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 428 (unsigned long)rx_queue); 429 430 return channel; 431 } 432 433 /* Allocate and initialise a channel structure, copying parameters 434 * (but not resources) from an old channel structure. 435 */ 436 static struct efx_channel * 437 efx_copy_channel(const struct efx_channel *old_channel) 438 { 439 struct efx_channel *channel; 440 struct efx_rx_queue *rx_queue; 441 struct efx_tx_queue *tx_queue; 442 int j; 443 444 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 445 if (!channel) 446 return NULL; 447 448 *channel = *old_channel; 449 450 channel->napi_dev = NULL; 451 memset(&channel->eventq, 0, sizeof(channel->eventq)); 452 453 for (j = 0; j < EFX_TXQ_TYPES; j++) { 454 tx_queue = &channel->tx_queue[j]; 455 if (tx_queue->channel) 456 tx_queue->channel = channel; 457 tx_queue->buffer = NULL; 458 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 459 } 460 461 rx_queue = &channel->rx_queue; 462 rx_queue->buffer = NULL; 463 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 464 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 465 (unsigned long)rx_queue); 466 467 return channel; 468 } 469 470 static int efx_probe_channel(struct efx_channel *channel) 471 { 472 struct efx_tx_queue *tx_queue; 473 struct efx_rx_queue *rx_queue; 474 int rc; 475 476 netif_dbg(channel->efx, probe, channel->efx->net_dev, 477 "creating channel %d\n", channel->channel); 478 479 rc = channel->type->pre_probe(channel); 480 if (rc) 481 goto fail; 482 483 rc = efx_probe_eventq(channel); 484 if (rc) 485 goto fail; 486 487 efx_for_each_channel_tx_queue(tx_queue, channel) { 488 rc = efx_probe_tx_queue(tx_queue); 489 if (rc) 490 goto fail; 491 } 492 493 efx_for_each_channel_rx_queue(rx_queue, channel) { 494 rc = efx_probe_rx_queue(rx_queue); 495 if (rc) 496 goto fail; 497 } 498 499 channel->n_rx_frm_trunc = 0; 500 501 return 0; 502 503 fail: 504 efx_remove_channel(channel); 505 return rc; 506 } 507 508 static void 509 efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 510 { 511 struct efx_nic *efx = channel->efx; 512 const char *type; 513 int number; 514 515 number = channel->channel; 516 if (efx->tx_channel_offset == 0) { 517 type = ""; 518 } else if (channel->channel < efx->tx_channel_offset) { 519 type = "-rx"; 520 } else { 521 type = "-tx"; 522 number -= efx->tx_channel_offset; 523 } 524 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 525 } 526 527 static void efx_set_channel_names(struct efx_nic *efx) 528 { 529 struct efx_channel *channel; 530 531 efx_for_each_channel(channel, efx) 532 channel->type->get_name(channel, 533 efx->msi_context[channel->channel].name, 534 sizeof(efx->msi_context[0].name)); 535 } 536 537 static int efx_probe_channels(struct efx_nic *efx) 538 { 539 struct efx_channel *channel; 540 int rc; 541 542 /* Restart special buffer allocation */ 543 efx->next_buffer_table = 0; 544 545 /* Probe channels in reverse, so that any 'extra' channels 546 * use the start of the buffer table. This allows the traffic 547 * channels to be resized without moving them or wasting the 548 * entries before them. 549 */ 550 efx_for_each_channel_rev(channel, efx) { 551 rc = efx_probe_channel(channel); 552 if (rc) { 553 netif_err(efx, probe, efx->net_dev, 554 "failed to create channel %d\n", 555 channel->channel); 556 goto fail; 557 } 558 } 559 efx_set_channel_names(efx); 560 561 return 0; 562 563 fail: 564 efx_remove_channels(efx); 565 return rc; 566 } 567 568 /* Channels are shutdown and reinitialised whilst the NIC is running 569 * to propagate configuration changes (mtu, checksum offload), or 570 * to clear hardware error conditions 571 */ 572 static void efx_start_datapath(struct efx_nic *efx) 573 { 574 bool old_rx_scatter = efx->rx_scatter; 575 struct efx_tx_queue *tx_queue; 576 struct efx_rx_queue *rx_queue; 577 struct efx_channel *channel; 578 size_t rx_buf_len; 579 580 /* Calculate the rx buffer allocation parameters required to 581 * support the current MTU, including padding for header 582 * alignment and overruns. 583 */ 584 efx->rx_dma_len = (efx->rx_prefix_size + 585 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + 586 efx->type->rx_buffer_padding); 587 rx_buf_len = (sizeof(struct efx_rx_page_state) + 588 NET_IP_ALIGN + efx->rx_dma_len); 589 if (rx_buf_len <= PAGE_SIZE) { 590 efx->rx_scatter = efx->type->always_rx_scatter; 591 efx->rx_buffer_order = 0; 592 } else if (efx->type->can_rx_scatter) { 593 BUILD_BUG_ON(EFX_RX_USR_BUF_SIZE % L1_CACHE_BYTES); 594 BUILD_BUG_ON(sizeof(struct efx_rx_page_state) + 595 2 * ALIGN(NET_IP_ALIGN + EFX_RX_USR_BUF_SIZE, 596 EFX_RX_BUF_ALIGNMENT) > 597 PAGE_SIZE); 598 efx->rx_scatter = true; 599 efx->rx_dma_len = EFX_RX_USR_BUF_SIZE; 600 efx->rx_buffer_order = 0; 601 } else { 602 efx->rx_scatter = false; 603 efx->rx_buffer_order = get_order(rx_buf_len); 604 } 605 606 efx_rx_config_page_split(efx); 607 if (efx->rx_buffer_order) 608 netif_dbg(efx, drv, efx->net_dev, 609 "RX buf len=%u; page order=%u batch=%u\n", 610 efx->rx_dma_len, efx->rx_buffer_order, 611 efx->rx_pages_per_batch); 612 else 613 netif_dbg(efx, drv, efx->net_dev, 614 "RX buf len=%u step=%u bpp=%u; page batch=%u\n", 615 efx->rx_dma_len, efx->rx_page_buf_step, 616 efx->rx_bufs_per_page, efx->rx_pages_per_batch); 617 618 /* RX filters may also have scatter-enabled flags */ 619 if (efx->rx_scatter != old_rx_scatter) 620 efx->type->filter_update_rx_scatter(efx); 621 622 /* We must keep at least one descriptor in a TX ring empty. 623 * We could avoid this when the queue size does not exactly 624 * match the hardware ring size, but it's not that important. 625 * Therefore we stop the queue when one more skb might fill 626 * the ring completely. We wake it when half way back to 627 * empty. 628 */ 629 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); 630 efx->txq_wake_thresh = efx->txq_stop_thresh / 2; 631 632 /* Initialise the channels */ 633 efx_for_each_channel(channel, efx) { 634 efx_for_each_channel_tx_queue(tx_queue, channel) { 635 efx_init_tx_queue(tx_queue); 636 atomic_inc(&efx->active_queues); 637 } 638 639 efx_for_each_channel_rx_queue(rx_queue, channel) { 640 efx_init_rx_queue(rx_queue); 641 atomic_inc(&efx->active_queues); 642 efx_nic_generate_fill_event(rx_queue); 643 } 644 645 WARN_ON(channel->rx_pkt_n_frags); 646 } 647 648 if (netif_device_present(efx->net_dev)) 649 netif_tx_wake_all_queues(efx->net_dev); 650 } 651 652 static void efx_stop_datapath(struct efx_nic *efx) 653 { 654 struct efx_channel *channel; 655 struct efx_tx_queue *tx_queue; 656 struct efx_rx_queue *rx_queue; 657 int rc; 658 659 EFX_ASSERT_RESET_SERIALISED(efx); 660 BUG_ON(efx->port_enabled); 661 662 /* Stop RX refill */ 663 efx_for_each_channel(channel, efx) { 664 efx_for_each_channel_rx_queue(rx_queue, channel) 665 rx_queue->refill_enabled = false; 666 } 667 668 efx_for_each_channel(channel, efx) { 669 /* RX packet processing is pipelined, so wait for the 670 * NAPI handler to complete. At least event queue 0 671 * might be kept active by non-data events, so don't 672 * use napi_synchronize() but actually disable NAPI 673 * temporarily. 674 */ 675 if (efx_channel_has_rx_queue(channel)) { 676 efx_stop_eventq(channel); 677 efx_start_eventq(channel); 678 } 679 } 680 681 rc = efx->type->fini_dmaq(efx); 682 if (rc && EFX_WORKAROUND_7803(efx)) { 683 /* Schedule a reset to recover from the flush failure. The 684 * descriptor caches reference memory we're about to free, 685 * but falcon_reconfigure_mac_wrapper() won't reconnect 686 * the MACs because of the pending reset. 687 */ 688 netif_err(efx, drv, efx->net_dev, 689 "Resetting to recover from flush failure\n"); 690 efx_schedule_reset(efx, RESET_TYPE_ALL); 691 } else if (rc) { 692 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 693 } else { 694 netif_dbg(efx, drv, efx->net_dev, 695 "successfully flushed all queues\n"); 696 } 697 698 efx_for_each_channel(channel, efx) { 699 efx_for_each_channel_rx_queue(rx_queue, channel) 700 efx_fini_rx_queue(rx_queue); 701 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 702 efx_fini_tx_queue(tx_queue); 703 } 704 } 705 706 static void efx_remove_channel(struct efx_channel *channel) 707 { 708 struct efx_tx_queue *tx_queue; 709 struct efx_rx_queue *rx_queue; 710 711 netif_dbg(channel->efx, drv, channel->efx->net_dev, 712 "destroy chan %d\n", channel->channel); 713 714 efx_for_each_channel_rx_queue(rx_queue, channel) 715 efx_remove_rx_queue(rx_queue); 716 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 717 efx_remove_tx_queue(tx_queue); 718 efx_remove_eventq(channel); 719 channel->type->post_remove(channel); 720 } 721 722 static void efx_remove_channels(struct efx_nic *efx) 723 { 724 struct efx_channel *channel; 725 726 efx_for_each_channel(channel, efx) 727 efx_remove_channel(channel); 728 } 729 730 int 731 efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 732 { 733 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 734 u32 old_rxq_entries, old_txq_entries; 735 unsigned i, next_buffer_table = 0; 736 int rc, rc2; 737 738 rc = efx_check_disabled(efx); 739 if (rc) 740 return rc; 741 742 /* Not all channels should be reallocated. We must avoid 743 * reallocating their buffer table entries. 744 */ 745 efx_for_each_channel(channel, efx) { 746 struct efx_rx_queue *rx_queue; 747 struct efx_tx_queue *tx_queue; 748 749 if (channel->type->copy) 750 continue; 751 next_buffer_table = max(next_buffer_table, 752 channel->eventq.index + 753 channel->eventq.entries); 754 efx_for_each_channel_rx_queue(rx_queue, channel) 755 next_buffer_table = max(next_buffer_table, 756 rx_queue->rxd.index + 757 rx_queue->rxd.entries); 758 efx_for_each_channel_tx_queue(tx_queue, channel) 759 next_buffer_table = max(next_buffer_table, 760 tx_queue->txd.index + 761 tx_queue->txd.entries); 762 } 763 764 efx_device_detach_sync(efx); 765 efx_stop_all(efx); 766 efx_soft_disable_interrupts(efx); 767 768 /* Clone channels (where possible) */ 769 memset(other_channel, 0, sizeof(other_channel)); 770 for (i = 0; i < efx->n_channels; i++) { 771 channel = efx->channel[i]; 772 if (channel->type->copy) 773 channel = channel->type->copy(channel); 774 if (!channel) { 775 rc = -ENOMEM; 776 goto out; 777 } 778 other_channel[i] = channel; 779 } 780 781 /* Swap entry counts and channel pointers */ 782 old_rxq_entries = efx->rxq_entries; 783 old_txq_entries = efx->txq_entries; 784 efx->rxq_entries = rxq_entries; 785 efx->txq_entries = txq_entries; 786 for (i = 0; i < efx->n_channels; i++) { 787 channel = efx->channel[i]; 788 efx->channel[i] = other_channel[i]; 789 other_channel[i] = channel; 790 } 791 792 /* Restart buffer table allocation */ 793 efx->next_buffer_table = next_buffer_table; 794 795 for (i = 0; i < efx->n_channels; i++) { 796 channel = efx->channel[i]; 797 if (!channel->type->copy) 798 continue; 799 rc = efx_probe_channel(channel); 800 if (rc) 801 goto rollback; 802 efx_init_napi_channel(efx->channel[i]); 803 } 804 805 out: 806 /* Destroy unused channel structures */ 807 for (i = 0; i < efx->n_channels; i++) { 808 channel = other_channel[i]; 809 if (channel && channel->type->copy) { 810 efx_fini_napi_channel(channel); 811 efx_remove_channel(channel); 812 kfree(channel); 813 } 814 } 815 816 rc2 = efx_soft_enable_interrupts(efx); 817 if (rc2) { 818 rc = rc ? rc : rc2; 819 netif_err(efx, drv, efx->net_dev, 820 "unable to restart interrupts on channel reallocation\n"); 821 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 822 } else { 823 efx_start_all(efx); 824 netif_device_attach(efx->net_dev); 825 } 826 return rc; 827 828 rollback: 829 /* Swap back */ 830 efx->rxq_entries = old_rxq_entries; 831 efx->txq_entries = old_txq_entries; 832 for (i = 0; i < efx->n_channels; i++) { 833 channel = efx->channel[i]; 834 efx->channel[i] = other_channel[i]; 835 other_channel[i] = channel; 836 } 837 goto out; 838 } 839 840 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) 841 { 842 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); 843 } 844 845 static const struct efx_channel_type efx_default_channel_type = { 846 .pre_probe = efx_channel_dummy_op_int, 847 .post_remove = efx_channel_dummy_op_void, 848 .get_name = efx_get_channel_name, 849 .copy = efx_copy_channel, 850 .keep_eventq = false, 851 }; 852 853 int efx_channel_dummy_op_int(struct efx_channel *channel) 854 { 855 return 0; 856 } 857 858 void efx_channel_dummy_op_void(struct efx_channel *channel) 859 { 860 } 861 862 /************************************************************************** 863 * 864 * Port handling 865 * 866 **************************************************************************/ 867 868 /* This ensures that the kernel is kept informed (via 869 * netif_carrier_on/off) of the link status, and also maintains the 870 * link status's stop on the port's TX queue. 871 */ 872 void efx_link_status_changed(struct efx_nic *efx) 873 { 874 struct efx_link_state *link_state = &efx->link_state; 875 876 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure 877 * that no events are triggered between unregister_netdev() and the 878 * driver unloading. A more general condition is that NETDEV_CHANGE 879 * can only be generated between NETDEV_UP and NETDEV_DOWN */ 880 if (!netif_running(efx->net_dev)) 881 return; 882 883 if (link_state->up != netif_carrier_ok(efx->net_dev)) { 884 efx->n_link_state_changes++; 885 886 if (link_state->up) 887 netif_carrier_on(efx->net_dev); 888 else 889 netif_carrier_off(efx->net_dev); 890 } 891 892 /* Status message for kernel log */ 893 if (link_state->up) 894 netif_info(efx, link, efx->net_dev, 895 "link up at %uMbps %s-duplex (MTU %d)\n", 896 link_state->speed, link_state->fd ? "full" : "half", 897 efx->net_dev->mtu); 898 else 899 netif_info(efx, link, efx->net_dev, "link down\n"); 900 } 901 902 void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) 903 { 904 efx->link_advertising = advertising; 905 if (advertising) { 906 if (advertising & ADVERTISED_Pause) 907 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); 908 else 909 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); 910 if (advertising & ADVERTISED_Asym_Pause) 911 efx->wanted_fc ^= EFX_FC_TX; 912 } 913 } 914 915 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) 916 { 917 efx->wanted_fc = wanted_fc; 918 if (efx->link_advertising) { 919 if (wanted_fc & EFX_FC_RX) 920 efx->link_advertising |= (ADVERTISED_Pause | 921 ADVERTISED_Asym_Pause); 922 else 923 efx->link_advertising &= ~(ADVERTISED_Pause | 924 ADVERTISED_Asym_Pause); 925 if (wanted_fc & EFX_FC_TX) 926 efx->link_advertising ^= ADVERTISED_Asym_Pause; 927 } 928 } 929 930 static void efx_fini_port(struct efx_nic *efx); 931 932 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure 933 * the MAC appropriately. All other PHY configuration changes are pushed 934 * through phy_op->set_settings(), and pushed asynchronously to the MAC 935 * through efx_monitor(). 936 * 937 * Callers must hold the mac_lock 938 */ 939 int __efx_reconfigure_port(struct efx_nic *efx) 940 { 941 enum efx_phy_mode phy_mode; 942 int rc; 943 944 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 945 946 /* Disable PHY transmit in mac level loopbacks */ 947 phy_mode = efx->phy_mode; 948 if (LOOPBACK_INTERNAL(efx)) 949 efx->phy_mode |= PHY_MODE_TX_DISABLED; 950 else 951 efx->phy_mode &= ~PHY_MODE_TX_DISABLED; 952 953 rc = efx->type->reconfigure_port(efx); 954 955 if (rc) 956 efx->phy_mode = phy_mode; 957 958 return rc; 959 } 960 961 /* Reinitialise the MAC to pick up new PHY settings, even if the port is 962 * disabled. */ 963 int efx_reconfigure_port(struct efx_nic *efx) 964 { 965 int rc; 966 967 EFX_ASSERT_RESET_SERIALISED(efx); 968 969 mutex_lock(&efx->mac_lock); 970 rc = __efx_reconfigure_port(efx); 971 mutex_unlock(&efx->mac_lock); 972 973 return rc; 974 } 975 976 /* Asynchronous work item for changing MAC promiscuity and multicast 977 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current 978 * MAC directly. */ 979 static void efx_mac_work(struct work_struct *data) 980 { 981 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); 982 983 mutex_lock(&efx->mac_lock); 984 if (efx->port_enabled) 985 efx->type->reconfigure_mac(efx); 986 mutex_unlock(&efx->mac_lock); 987 } 988 989 static int efx_probe_port(struct efx_nic *efx) 990 { 991 int rc; 992 993 netif_dbg(efx, probe, efx->net_dev, "create port\n"); 994 995 if (phy_flash_cfg) 996 efx->phy_mode = PHY_MODE_SPECIAL; 997 998 /* Connect up MAC/PHY operations table */ 999 rc = efx->type->probe_port(efx); 1000 if (rc) 1001 return rc; 1002 1003 /* Initialise MAC address to permanent address */ 1004 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); 1005 1006 return 0; 1007 } 1008 1009 static int efx_init_port(struct efx_nic *efx) 1010 { 1011 int rc; 1012 1013 netif_dbg(efx, drv, efx->net_dev, "init port\n"); 1014 1015 mutex_lock(&efx->mac_lock); 1016 1017 rc = efx->phy_op->init(efx); 1018 if (rc) 1019 goto fail1; 1020 1021 efx->port_initialized = true; 1022 1023 /* Reconfigure the MAC before creating dma queues (required for 1024 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ 1025 efx->type->reconfigure_mac(efx); 1026 1027 /* Ensure the PHY advertises the correct flow control settings */ 1028 rc = efx->phy_op->reconfigure(efx); 1029 if (rc) 1030 goto fail2; 1031 1032 mutex_unlock(&efx->mac_lock); 1033 return 0; 1034 1035 fail2: 1036 efx->phy_op->fini(efx); 1037 fail1: 1038 mutex_unlock(&efx->mac_lock); 1039 return rc; 1040 } 1041 1042 static void efx_start_port(struct efx_nic *efx) 1043 { 1044 netif_dbg(efx, ifup, efx->net_dev, "start port\n"); 1045 BUG_ON(efx->port_enabled); 1046 1047 mutex_lock(&efx->mac_lock); 1048 efx->port_enabled = true; 1049 1050 /* efx_mac_work() might have been scheduled after efx_stop_port(), 1051 * and then cancelled by efx_flush_all() */ 1052 efx->type->reconfigure_mac(efx); 1053 1054 mutex_unlock(&efx->mac_lock); 1055 } 1056 1057 /* Prevent efx_mac_work() and efx_monitor() from working */ 1058 static void efx_stop_port(struct efx_nic *efx) 1059 { 1060 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); 1061 1062 mutex_lock(&efx->mac_lock); 1063 efx->port_enabled = false; 1064 mutex_unlock(&efx->mac_lock); 1065 1066 /* Serialise against efx_set_multicast_list() */ 1067 netif_addr_lock_bh(efx->net_dev); 1068 netif_addr_unlock_bh(efx->net_dev); 1069 } 1070 1071 static void efx_fini_port(struct efx_nic *efx) 1072 { 1073 netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); 1074 1075 if (!efx->port_initialized) 1076 return; 1077 1078 efx->phy_op->fini(efx); 1079 efx->port_initialized = false; 1080 1081 efx->link_state.up = false; 1082 efx_link_status_changed(efx); 1083 } 1084 1085 static void efx_remove_port(struct efx_nic *efx) 1086 { 1087 netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); 1088 1089 efx->type->remove_port(efx); 1090 } 1091 1092 /************************************************************************** 1093 * 1094 * NIC handling 1095 * 1096 **************************************************************************/ 1097 1098 /* This configures the PCI device to enable I/O and DMA. */ 1099 static int efx_init_io(struct efx_nic *efx) 1100 { 1101 struct pci_dev *pci_dev = efx->pci_dev; 1102 dma_addr_t dma_mask = efx->type->max_dma_mask; 1103 unsigned int mem_map_size = efx->type->mem_map_size(efx); 1104 int rc; 1105 1106 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); 1107 1108 rc = pci_enable_device(pci_dev); 1109 if (rc) { 1110 netif_err(efx, probe, efx->net_dev, 1111 "failed to enable PCI device\n"); 1112 goto fail1; 1113 } 1114 1115 pci_set_master(pci_dev); 1116 1117 /* Set the PCI DMA mask. Try all possibilities from our 1118 * genuine mask down to 32 bits, because some architectures 1119 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit 1120 * masks event though they reject 46 bit masks. 1121 */ 1122 while (dma_mask > 0x7fffffffUL) { 1123 if (dma_supported(&pci_dev->dev, dma_mask)) { 1124 rc = dma_set_mask(&pci_dev->dev, dma_mask); 1125 if (rc == 0) 1126 break; 1127 } 1128 dma_mask >>= 1; 1129 } 1130 if (rc) { 1131 netif_err(efx, probe, efx->net_dev, 1132 "could not find a suitable DMA mask\n"); 1133 goto fail2; 1134 } 1135 netif_dbg(efx, probe, efx->net_dev, 1136 "using DMA mask %llx\n", (unsigned long long) dma_mask); 1137 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask); 1138 if (rc) { 1139 /* dma_set_coherent_mask() is not *allowed* to 1140 * fail with a mask that dma_set_mask() accepted, 1141 * but just in case... 1142 */ 1143 netif_err(efx, probe, efx->net_dev, 1144 "failed to set consistent DMA mask\n"); 1145 goto fail2; 1146 } 1147 1148 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); 1149 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); 1150 if (rc) { 1151 netif_err(efx, probe, efx->net_dev, 1152 "request for memory BAR failed\n"); 1153 rc = -EIO; 1154 goto fail3; 1155 } 1156 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); 1157 if (!efx->membase) { 1158 netif_err(efx, probe, efx->net_dev, 1159 "could not map memory BAR at %llx+%x\n", 1160 (unsigned long long)efx->membase_phys, mem_map_size); 1161 rc = -ENOMEM; 1162 goto fail4; 1163 } 1164 netif_dbg(efx, probe, efx->net_dev, 1165 "memory BAR at %llx+%x (virtual %p)\n", 1166 (unsigned long long)efx->membase_phys, mem_map_size, 1167 efx->membase); 1168 1169 return 0; 1170 1171 fail4: 1172 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1173 fail3: 1174 efx->membase_phys = 0; 1175 fail2: 1176 pci_disable_device(efx->pci_dev); 1177 fail1: 1178 return rc; 1179 } 1180 1181 static void efx_fini_io(struct efx_nic *efx) 1182 { 1183 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); 1184 1185 if (efx->membase) { 1186 iounmap(efx->membase); 1187 efx->membase = NULL; 1188 } 1189 1190 if (efx->membase_phys) { 1191 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1192 efx->membase_phys = 0; 1193 } 1194 1195 pci_disable_device(efx->pci_dev); 1196 } 1197 1198 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 1199 { 1200 cpumask_var_t thread_mask; 1201 unsigned int count; 1202 int cpu; 1203 1204 if (rss_cpus) { 1205 count = rss_cpus; 1206 } else { 1207 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 1208 netif_warn(efx, probe, efx->net_dev, 1209 "RSS disabled due to allocation failure\n"); 1210 return 1; 1211 } 1212 1213 count = 0; 1214 for_each_online_cpu(cpu) { 1215 if (!cpumask_test_cpu(cpu, thread_mask)) { 1216 ++count; 1217 cpumask_or(thread_mask, thread_mask, 1218 topology_thread_cpumask(cpu)); 1219 } 1220 } 1221 1222 free_cpumask_var(thread_mask); 1223 } 1224 1225 /* If RSS is requested for the PF *and* VFs then we can't write RSS 1226 * table entries that are inaccessible to VFs 1227 */ 1228 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && 1229 count > efx_vf_size(efx)) { 1230 netif_warn(efx, probe, efx->net_dev, 1231 "Reducing number of RSS channels from %u to %u for " 1232 "VF support. Increase vf-msix-limit to use more " 1233 "channels on the PF.\n", 1234 count, efx_vf_size(efx)); 1235 count = efx_vf_size(efx); 1236 } 1237 1238 return count; 1239 } 1240 1241 /* Probe the number and type of interrupts we are able to obtain, and 1242 * the resulting numbers of channels and RX queues. 1243 */ 1244 static int efx_probe_interrupts(struct efx_nic *efx) 1245 { 1246 unsigned int extra_channels = 0; 1247 unsigned int i, j; 1248 int rc; 1249 1250 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 1251 if (efx->extra_channel_type[i]) 1252 ++extra_channels; 1253 1254 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 1255 struct msix_entry xentries[EFX_MAX_CHANNELS]; 1256 unsigned int n_channels; 1257 1258 n_channels = efx_wanted_parallelism(efx); 1259 if (separate_tx_channels) 1260 n_channels *= 2; 1261 n_channels += extra_channels; 1262 n_channels = min(n_channels, efx->max_channels); 1263 1264 for (i = 0; i < n_channels; i++) 1265 xentries[i].entry = i; 1266 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); 1267 if (rc > 0) { 1268 netif_err(efx, drv, efx->net_dev, 1269 "WARNING: Insufficient MSI-X vectors" 1270 " available (%d < %u).\n", rc, n_channels); 1271 netif_err(efx, drv, efx->net_dev, 1272 "WARNING: Performance may be reduced.\n"); 1273 EFX_BUG_ON_PARANOID(rc >= n_channels); 1274 n_channels = rc; 1275 rc = pci_enable_msix(efx->pci_dev, xentries, 1276 n_channels); 1277 } 1278 1279 if (rc == 0) { 1280 efx->n_channels = n_channels; 1281 if (n_channels > extra_channels) 1282 n_channels -= extra_channels; 1283 if (separate_tx_channels) { 1284 efx->n_tx_channels = max(n_channels / 2, 1U); 1285 efx->n_rx_channels = max(n_channels - 1286 efx->n_tx_channels, 1287 1U); 1288 } else { 1289 efx->n_tx_channels = n_channels; 1290 efx->n_rx_channels = n_channels; 1291 } 1292 for (i = 0; i < efx->n_channels; i++) 1293 efx_get_channel(efx, i)->irq = 1294 xentries[i].vector; 1295 } else { 1296 /* Fall back to single channel MSI */ 1297 efx->interrupt_mode = EFX_INT_MODE_MSI; 1298 netif_err(efx, drv, efx->net_dev, 1299 "could not enable MSI-X\n"); 1300 } 1301 } 1302 1303 /* Try single interrupt MSI */ 1304 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 1305 efx->n_channels = 1; 1306 efx->n_rx_channels = 1; 1307 efx->n_tx_channels = 1; 1308 rc = pci_enable_msi(efx->pci_dev); 1309 if (rc == 0) { 1310 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 1311 } else { 1312 netif_err(efx, drv, efx->net_dev, 1313 "could not enable MSI\n"); 1314 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 1315 } 1316 } 1317 1318 /* Assume legacy interrupts */ 1319 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 1320 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); 1321 efx->n_rx_channels = 1; 1322 efx->n_tx_channels = 1; 1323 efx->legacy_irq = efx->pci_dev->irq; 1324 } 1325 1326 /* Assign extra channels if possible */ 1327 j = efx->n_channels; 1328 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 1329 if (!efx->extra_channel_type[i]) 1330 continue; 1331 if (efx->interrupt_mode != EFX_INT_MODE_MSIX || 1332 efx->n_channels <= extra_channels) { 1333 efx->extra_channel_type[i]->handle_no_channel(efx); 1334 } else { 1335 --j; 1336 efx_get_channel(efx, j)->type = 1337 efx->extra_channel_type[i]; 1338 } 1339 } 1340 1341 /* RSS might be usable on VFs even if it is disabled on the PF */ 1342 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? 1343 efx->n_rx_channels : efx_vf_size(efx)); 1344 1345 return 0; 1346 } 1347 1348 static int efx_soft_enable_interrupts(struct efx_nic *efx) 1349 { 1350 struct efx_channel *channel, *end_channel; 1351 int rc; 1352 1353 BUG_ON(efx->state == STATE_DISABLED); 1354 1355 efx->irq_soft_enabled = true; 1356 smp_wmb(); 1357 1358 efx_for_each_channel(channel, efx) { 1359 if (!channel->type->keep_eventq) { 1360 rc = efx_init_eventq(channel); 1361 if (rc) 1362 goto fail; 1363 } 1364 efx_start_eventq(channel); 1365 } 1366 1367 efx_mcdi_mode_event(efx); 1368 1369 return 0; 1370 fail: 1371 end_channel = channel; 1372 efx_for_each_channel(channel, efx) { 1373 if (channel == end_channel) 1374 break; 1375 efx_stop_eventq(channel); 1376 if (!channel->type->keep_eventq) 1377 efx_fini_eventq(channel); 1378 } 1379 1380 return rc; 1381 } 1382 1383 static void efx_soft_disable_interrupts(struct efx_nic *efx) 1384 { 1385 struct efx_channel *channel; 1386 1387 if (efx->state == STATE_DISABLED) 1388 return; 1389 1390 efx_mcdi_mode_poll(efx); 1391 1392 efx->irq_soft_enabled = false; 1393 smp_wmb(); 1394 1395 if (efx->legacy_irq) 1396 synchronize_irq(efx->legacy_irq); 1397 1398 efx_for_each_channel(channel, efx) { 1399 if (channel->irq) 1400 synchronize_irq(channel->irq); 1401 1402 efx_stop_eventq(channel); 1403 if (!channel->type->keep_eventq) 1404 efx_fini_eventq(channel); 1405 } 1406 1407 /* Flush the asynchronous MCDI request queue */ 1408 efx_mcdi_flush_async(efx); 1409 } 1410 1411 static int efx_enable_interrupts(struct efx_nic *efx) 1412 { 1413 struct efx_channel *channel, *end_channel; 1414 int rc; 1415 1416 BUG_ON(efx->state == STATE_DISABLED); 1417 1418 if (efx->eeh_disabled_legacy_irq) { 1419 enable_irq(efx->legacy_irq); 1420 efx->eeh_disabled_legacy_irq = false; 1421 } 1422 1423 efx->type->irq_enable_master(efx); 1424 1425 efx_for_each_channel(channel, efx) { 1426 if (channel->type->keep_eventq) { 1427 rc = efx_init_eventq(channel); 1428 if (rc) 1429 goto fail; 1430 } 1431 } 1432 1433 rc = efx_soft_enable_interrupts(efx); 1434 if (rc) 1435 goto fail; 1436 1437 return 0; 1438 1439 fail: 1440 end_channel = channel; 1441 efx_for_each_channel(channel, efx) { 1442 if (channel == end_channel) 1443 break; 1444 if (channel->type->keep_eventq) 1445 efx_fini_eventq(channel); 1446 } 1447 1448 efx->type->irq_disable_non_ev(efx); 1449 1450 return rc; 1451 } 1452 1453 static void efx_disable_interrupts(struct efx_nic *efx) 1454 { 1455 struct efx_channel *channel; 1456 1457 efx_soft_disable_interrupts(efx); 1458 1459 efx_for_each_channel(channel, efx) { 1460 if (channel->type->keep_eventq) 1461 efx_fini_eventq(channel); 1462 } 1463 1464 efx->type->irq_disable_non_ev(efx); 1465 } 1466 1467 static void efx_remove_interrupts(struct efx_nic *efx) 1468 { 1469 struct efx_channel *channel; 1470 1471 /* Remove MSI/MSI-X interrupts */ 1472 efx_for_each_channel(channel, efx) 1473 channel->irq = 0; 1474 pci_disable_msi(efx->pci_dev); 1475 pci_disable_msix(efx->pci_dev); 1476 1477 /* Remove legacy interrupt */ 1478 efx->legacy_irq = 0; 1479 } 1480 1481 static void efx_set_channels(struct efx_nic *efx) 1482 { 1483 struct efx_channel *channel; 1484 struct efx_tx_queue *tx_queue; 1485 1486 efx->tx_channel_offset = 1487 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; 1488 1489 /* We need to mark which channels really have RX and TX 1490 * queues, and adjust the TX queue numbers if we have separate 1491 * RX-only and TX-only channels. 1492 */ 1493 efx_for_each_channel(channel, efx) { 1494 if (channel->channel < efx->n_rx_channels) 1495 channel->rx_queue.core_index = channel->channel; 1496 else 1497 channel->rx_queue.core_index = -1; 1498 1499 efx_for_each_channel_tx_queue(tx_queue, channel) 1500 tx_queue->queue -= (efx->tx_channel_offset * 1501 EFX_TXQ_TYPES); 1502 } 1503 } 1504 1505 static int efx_probe_nic(struct efx_nic *efx) 1506 { 1507 size_t i; 1508 int rc; 1509 1510 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); 1511 1512 /* Carry out hardware-type specific initialisation */ 1513 rc = efx->type->probe(efx); 1514 if (rc) 1515 return rc; 1516 1517 /* Determine the number of channels and queues by trying to hook 1518 * in MSI-X interrupts. */ 1519 rc = efx_probe_interrupts(efx); 1520 if (rc) 1521 goto fail1; 1522 1523 rc = efx->type->dimension_resources(efx); 1524 if (rc) 1525 goto fail2; 1526 1527 if (efx->n_channels > 1) 1528 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); 1529 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) 1530 efx->rx_indir_table[i] = 1531 ethtool_rxfh_indir_default(i, efx->rss_spread); 1532 1533 efx_set_channels(efx); 1534 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1535 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1536 1537 /* Initialise the interrupt moderation settings */ 1538 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, 1539 true); 1540 1541 return 0; 1542 1543 fail2: 1544 efx_remove_interrupts(efx); 1545 fail1: 1546 efx->type->remove(efx); 1547 return rc; 1548 } 1549 1550 static void efx_remove_nic(struct efx_nic *efx) 1551 { 1552 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); 1553 1554 efx_remove_interrupts(efx); 1555 efx->type->remove(efx); 1556 } 1557 1558 static int efx_probe_filters(struct efx_nic *efx) 1559 { 1560 int rc; 1561 1562 spin_lock_init(&efx->filter_lock); 1563 1564 rc = efx->type->filter_table_probe(efx); 1565 if (rc) 1566 return rc; 1567 1568 #ifdef CONFIG_RFS_ACCEL 1569 if (efx->type->offload_features & NETIF_F_NTUPLE) { 1570 efx->rps_flow_id = kcalloc(efx->type->max_rx_ip_filters, 1571 sizeof(*efx->rps_flow_id), 1572 GFP_KERNEL); 1573 if (!efx->rps_flow_id) { 1574 efx->type->filter_table_remove(efx); 1575 return -ENOMEM; 1576 } 1577 } 1578 #endif 1579 1580 return 0; 1581 } 1582 1583 static void efx_remove_filters(struct efx_nic *efx) 1584 { 1585 #ifdef CONFIG_RFS_ACCEL 1586 kfree(efx->rps_flow_id); 1587 #endif 1588 efx->type->filter_table_remove(efx); 1589 } 1590 1591 static void efx_restore_filters(struct efx_nic *efx) 1592 { 1593 efx->type->filter_table_restore(efx); 1594 } 1595 1596 /************************************************************************** 1597 * 1598 * NIC startup/shutdown 1599 * 1600 *************************************************************************/ 1601 1602 static int efx_probe_all(struct efx_nic *efx) 1603 { 1604 int rc; 1605 1606 rc = efx_probe_nic(efx); 1607 if (rc) { 1608 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); 1609 goto fail1; 1610 } 1611 1612 rc = efx_probe_port(efx); 1613 if (rc) { 1614 netif_err(efx, probe, efx->net_dev, "failed to create port\n"); 1615 goto fail2; 1616 } 1617 1618 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); 1619 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { 1620 rc = -EINVAL; 1621 goto fail3; 1622 } 1623 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; 1624 1625 rc = efx_probe_filters(efx); 1626 if (rc) { 1627 netif_err(efx, probe, efx->net_dev, 1628 "failed to create filter tables\n"); 1629 goto fail3; 1630 } 1631 1632 rc = efx_probe_channels(efx); 1633 if (rc) 1634 goto fail4; 1635 1636 return 0; 1637 1638 fail4: 1639 efx_remove_filters(efx); 1640 fail3: 1641 efx_remove_port(efx); 1642 fail2: 1643 efx_remove_nic(efx); 1644 fail1: 1645 return rc; 1646 } 1647 1648 /* If the interface is supposed to be running but is not, start 1649 * the hardware and software data path, regular activity for the port 1650 * (MAC statistics, link polling, etc.) and schedule the port to be 1651 * reconfigured. Interrupts must already be enabled. This function 1652 * is safe to call multiple times, so long as the NIC is not disabled. 1653 * Requires the RTNL lock. 1654 */ 1655 static void efx_start_all(struct efx_nic *efx) 1656 { 1657 EFX_ASSERT_RESET_SERIALISED(efx); 1658 BUG_ON(efx->state == STATE_DISABLED); 1659 1660 /* Check that it is appropriate to restart the interface. All 1661 * of these flags are safe to read under just the rtnl lock */ 1662 if (efx->port_enabled || !netif_running(efx->net_dev)) 1663 return; 1664 1665 efx_start_port(efx); 1666 efx_start_datapath(efx); 1667 1668 /* Start the hardware monitor if there is one */ 1669 if (efx->type->monitor != NULL) 1670 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1671 efx_monitor_interval); 1672 1673 /* If link state detection is normally event-driven, we have 1674 * to poll now because we could have missed a change 1675 */ 1676 if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) { 1677 mutex_lock(&efx->mac_lock); 1678 if (efx->phy_op->poll(efx)) 1679 efx_link_status_changed(efx); 1680 mutex_unlock(&efx->mac_lock); 1681 } 1682 1683 efx->type->start_stats(efx); 1684 } 1685 1686 /* Flush all delayed work. Should only be called when no more delayed work 1687 * will be scheduled. This doesn't flush pending online resets (efx_reset), 1688 * since we're holding the rtnl_lock at this point. */ 1689 static void efx_flush_all(struct efx_nic *efx) 1690 { 1691 /* Make sure the hardware monitor and event self-test are stopped */ 1692 cancel_delayed_work_sync(&efx->monitor_work); 1693 efx_selftest_async_cancel(efx); 1694 /* Stop scheduled port reconfigurations */ 1695 cancel_work_sync(&efx->mac_work); 1696 } 1697 1698 /* Quiesce the hardware and software data path, and regular activity 1699 * for the port without bringing the link down. Safe to call multiple 1700 * times with the NIC in almost any state, but interrupts should be 1701 * enabled. Requires the RTNL lock. 1702 */ 1703 static void efx_stop_all(struct efx_nic *efx) 1704 { 1705 EFX_ASSERT_RESET_SERIALISED(efx); 1706 1707 /* port_enabled can be read safely under the rtnl lock */ 1708 if (!efx->port_enabled) 1709 return; 1710 1711 efx->type->stop_stats(efx); 1712 efx_stop_port(efx); 1713 1714 /* Flush efx_mac_work(), refill_workqueue, monitor_work */ 1715 efx_flush_all(efx); 1716 1717 /* Stop the kernel transmit interface. This is only valid if 1718 * the device is stopped or detached; otherwise the watchdog 1719 * may fire immediately. 1720 */ 1721 WARN_ON(netif_running(efx->net_dev) && 1722 netif_device_present(efx->net_dev)); 1723 netif_tx_disable(efx->net_dev); 1724 1725 efx_stop_datapath(efx); 1726 } 1727 1728 static void efx_remove_all(struct efx_nic *efx) 1729 { 1730 efx_remove_channels(efx); 1731 efx_remove_filters(efx); 1732 efx_remove_port(efx); 1733 efx_remove_nic(efx); 1734 } 1735 1736 /************************************************************************** 1737 * 1738 * Interrupt moderation 1739 * 1740 **************************************************************************/ 1741 1742 static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) 1743 { 1744 if (usecs == 0) 1745 return 0; 1746 if (usecs * 1000 < quantum_ns) 1747 return 1; /* never round down to 0 */ 1748 return usecs * 1000 / quantum_ns; 1749 } 1750 1751 /* Set interrupt moderation parameters */ 1752 int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, 1753 unsigned int rx_usecs, bool rx_adaptive, 1754 bool rx_may_override_tx) 1755 { 1756 struct efx_channel *channel; 1757 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * 1758 efx->timer_quantum_ns, 1759 1000); 1760 unsigned int tx_ticks; 1761 unsigned int rx_ticks; 1762 1763 EFX_ASSERT_RESET_SERIALISED(efx); 1764 1765 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) 1766 return -EINVAL; 1767 1768 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); 1769 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); 1770 1771 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && 1772 !rx_may_override_tx) { 1773 netif_err(efx, drv, efx->net_dev, "Channels are shared. " 1774 "RX and TX IRQ moderation must be equal\n"); 1775 return -EINVAL; 1776 } 1777 1778 efx->irq_rx_adaptive = rx_adaptive; 1779 efx->irq_rx_moderation = rx_ticks; 1780 efx_for_each_channel(channel, efx) { 1781 if (efx_channel_has_rx_queue(channel)) 1782 channel->irq_moderation = rx_ticks; 1783 else if (efx_channel_has_tx_queues(channel)) 1784 channel->irq_moderation = tx_ticks; 1785 } 1786 1787 return 0; 1788 } 1789 1790 void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, 1791 unsigned int *rx_usecs, bool *rx_adaptive) 1792 { 1793 /* We must round up when converting ticks to microseconds 1794 * because we round down when converting the other way. 1795 */ 1796 1797 *rx_adaptive = efx->irq_rx_adaptive; 1798 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * 1799 efx->timer_quantum_ns, 1800 1000); 1801 1802 /* If channels are shared between RX and TX, so is IRQ 1803 * moderation. Otherwise, IRQ moderation is the same for all 1804 * TX channels and is not adaptive. 1805 */ 1806 if (efx->tx_channel_offset == 0) 1807 *tx_usecs = *rx_usecs; 1808 else 1809 *tx_usecs = DIV_ROUND_UP( 1810 efx->channel[efx->tx_channel_offset]->irq_moderation * 1811 efx->timer_quantum_ns, 1812 1000); 1813 } 1814 1815 /************************************************************************** 1816 * 1817 * Hardware monitor 1818 * 1819 **************************************************************************/ 1820 1821 /* Run periodically off the general workqueue */ 1822 static void efx_monitor(struct work_struct *data) 1823 { 1824 struct efx_nic *efx = container_of(data, struct efx_nic, 1825 monitor_work.work); 1826 1827 netif_vdbg(efx, timer, efx->net_dev, 1828 "hardware monitor executing on CPU %d\n", 1829 raw_smp_processor_id()); 1830 BUG_ON(efx->type->monitor == NULL); 1831 1832 /* If the mac_lock is already held then it is likely a port 1833 * reconfiguration is already in place, which will likely do 1834 * most of the work of monitor() anyway. */ 1835 if (mutex_trylock(&efx->mac_lock)) { 1836 if (efx->port_enabled) 1837 efx->type->monitor(efx); 1838 mutex_unlock(&efx->mac_lock); 1839 } 1840 1841 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1842 efx_monitor_interval); 1843 } 1844 1845 /************************************************************************** 1846 * 1847 * ioctls 1848 * 1849 *************************************************************************/ 1850 1851 /* Net device ioctl 1852 * Context: process, rtnl_lock() held. 1853 */ 1854 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1855 { 1856 struct efx_nic *efx = netdev_priv(net_dev); 1857 struct mii_ioctl_data *data = if_mii(ifr); 1858 1859 if (cmd == SIOCSHWTSTAMP) 1860 return efx_ptp_ioctl(efx, ifr, cmd); 1861 1862 /* Convert phy_id from older PRTAD/DEVAD format */ 1863 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 1864 (data->phy_id & 0xfc00) == 0x0400) 1865 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 1866 1867 return mdio_mii_ioctl(&efx->mdio, data, cmd); 1868 } 1869 1870 /************************************************************************** 1871 * 1872 * NAPI interface 1873 * 1874 **************************************************************************/ 1875 1876 static void efx_init_napi_channel(struct efx_channel *channel) 1877 { 1878 struct efx_nic *efx = channel->efx; 1879 1880 channel->napi_dev = efx->net_dev; 1881 netif_napi_add(channel->napi_dev, &channel->napi_str, 1882 efx_poll, napi_weight); 1883 } 1884 1885 static void efx_init_napi(struct efx_nic *efx) 1886 { 1887 struct efx_channel *channel; 1888 1889 efx_for_each_channel(channel, efx) 1890 efx_init_napi_channel(channel); 1891 } 1892 1893 static void efx_fini_napi_channel(struct efx_channel *channel) 1894 { 1895 if (channel->napi_dev) 1896 netif_napi_del(&channel->napi_str); 1897 channel->napi_dev = NULL; 1898 } 1899 1900 static void efx_fini_napi(struct efx_nic *efx) 1901 { 1902 struct efx_channel *channel; 1903 1904 efx_for_each_channel(channel, efx) 1905 efx_fini_napi_channel(channel); 1906 } 1907 1908 /************************************************************************** 1909 * 1910 * Kernel netpoll interface 1911 * 1912 *************************************************************************/ 1913 1914 #ifdef CONFIG_NET_POLL_CONTROLLER 1915 1916 /* Although in the common case interrupts will be disabled, this is not 1917 * guaranteed. However, all our work happens inside the NAPI callback, 1918 * so no locking is required. 1919 */ 1920 static void efx_netpoll(struct net_device *net_dev) 1921 { 1922 struct efx_nic *efx = netdev_priv(net_dev); 1923 struct efx_channel *channel; 1924 1925 efx_for_each_channel(channel, efx) 1926 efx_schedule_channel(channel); 1927 } 1928 1929 #endif 1930 1931 /************************************************************************** 1932 * 1933 * Kernel net device interface 1934 * 1935 *************************************************************************/ 1936 1937 /* Context: process, rtnl_lock() held. */ 1938 static int efx_net_open(struct net_device *net_dev) 1939 { 1940 struct efx_nic *efx = netdev_priv(net_dev); 1941 int rc; 1942 1943 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", 1944 raw_smp_processor_id()); 1945 1946 rc = efx_check_disabled(efx); 1947 if (rc) 1948 return rc; 1949 if (efx->phy_mode & PHY_MODE_SPECIAL) 1950 return -EBUSY; 1951 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) 1952 return -EIO; 1953 1954 /* Notify the kernel of the link state polled during driver load, 1955 * before the monitor starts running */ 1956 efx_link_status_changed(efx); 1957 1958 efx_start_all(efx); 1959 efx_selftest_async_start(efx); 1960 return 0; 1961 } 1962 1963 /* Context: process, rtnl_lock() held. 1964 * Note that the kernel will ignore our return code; this method 1965 * should really be a void. 1966 */ 1967 static int efx_net_stop(struct net_device *net_dev) 1968 { 1969 struct efx_nic *efx = netdev_priv(net_dev); 1970 1971 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", 1972 raw_smp_processor_id()); 1973 1974 /* Stop the device and flush all the channels */ 1975 efx_stop_all(efx); 1976 1977 return 0; 1978 } 1979 1980 /* Context: process, dev_base_lock or RTNL held, non-blocking. */ 1981 static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, 1982 struct rtnl_link_stats64 *stats) 1983 { 1984 struct efx_nic *efx = netdev_priv(net_dev); 1985 1986 spin_lock_bh(&efx->stats_lock); 1987 efx->type->update_stats(efx, NULL, stats); 1988 spin_unlock_bh(&efx->stats_lock); 1989 1990 return stats; 1991 } 1992 1993 /* Context: netif_tx_lock held, BHs disabled. */ 1994 static void efx_watchdog(struct net_device *net_dev) 1995 { 1996 struct efx_nic *efx = netdev_priv(net_dev); 1997 1998 netif_err(efx, tx_err, efx->net_dev, 1999 "TX stuck with port_enabled=%d: resetting channels\n", 2000 efx->port_enabled); 2001 2002 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); 2003 } 2004 2005 2006 /* Context: process, rtnl_lock() held. */ 2007 static int efx_change_mtu(struct net_device *net_dev, int new_mtu) 2008 { 2009 struct efx_nic *efx = netdev_priv(net_dev); 2010 int rc; 2011 2012 rc = efx_check_disabled(efx); 2013 if (rc) 2014 return rc; 2015 if (new_mtu > EFX_MAX_MTU) 2016 return -EINVAL; 2017 2018 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); 2019 2020 efx_device_detach_sync(efx); 2021 efx_stop_all(efx); 2022 2023 mutex_lock(&efx->mac_lock); 2024 net_dev->mtu = new_mtu; 2025 efx->type->reconfigure_mac(efx); 2026 mutex_unlock(&efx->mac_lock); 2027 2028 efx_start_all(efx); 2029 netif_device_attach(efx->net_dev); 2030 return 0; 2031 } 2032 2033 static int efx_set_mac_address(struct net_device *net_dev, void *data) 2034 { 2035 struct efx_nic *efx = netdev_priv(net_dev); 2036 struct sockaddr *addr = data; 2037 char *new_addr = addr->sa_data; 2038 2039 if (!is_valid_ether_addr(new_addr)) { 2040 netif_err(efx, drv, efx->net_dev, 2041 "invalid ethernet MAC address requested: %pM\n", 2042 new_addr); 2043 return -EADDRNOTAVAIL; 2044 } 2045 2046 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); 2047 efx_sriov_mac_address_changed(efx); 2048 2049 /* Reconfigure the MAC */ 2050 mutex_lock(&efx->mac_lock); 2051 efx->type->reconfigure_mac(efx); 2052 mutex_unlock(&efx->mac_lock); 2053 2054 return 0; 2055 } 2056 2057 /* Context: netif_addr_lock held, BHs disabled. */ 2058 static void efx_set_rx_mode(struct net_device *net_dev) 2059 { 2060 struct efx_nic *efx = netdev_priv(net_dev); 2061 2062 if (efx->port_enabled) 2063 queue_work(efx->workqueue, &efx->mac_work); 2064 /* Otherwise efx_start_port() will do this */ 2065 } 2066 2067 static int efx_set_features(struct net_device *net_dev, netdev_features_t data) 2068 { 2069 struct efx_nic *efx = netdev_priv(net_dev); 2070 2071 /* If disabling RX n-tuple filtering, clear existing filters */ 2072 if (net_dev->features & ~data & NETIF_F_NTUPLE) 2073 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); 2074 2075 return 0; 2076 } 2077 2078 static const struct net_device_ops efx_farch_netdev_ops = { 2079 .ndo_open = efx_net_open, 2080 .ndo_stop = efx_net_stop, 2081 .ndo_get_stats64 = efx_net_stats, 2082 .ndo_tx_timeout = efx_watchdog, 2083 .ndo_start_xmit = efx_hard_start_xmit, 2084 .ndo_validate_addr = eth_validate_addr, 2085 .ndo_do_ioctl = efx_ioctl, 2086 .ndo_change_mtu = efx_change_mtu, 2087 .ndo_set_mac_address = efx_set_mac_address, 2088 .ndo_set_rx_mode = efx_set_rx_mode, 2089 .ndo_set_features = efx_set_features, 2090 #ifdef CONFIG_SFC_SRIOV 2091 .ndo_set_vf_mac = efx_sriov_set_vf_mac, 2092 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, 2093 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, 2094 .ndo_get_vf_config = efx_sriov_get_vf_config, 2095 #endif 2096 #ifdef CONFIG_NET_POLL_CONTROLLER 2097 .ndo_poll_controller = efx_netpoll, 2098 #endif 2099 .ndo_setup_tc = efx_setup_tc, 2100 #ifdef CONFIG_RFS_ACCEL 2101 .ndo_rx_flow_steer = efx_filter_rfs, 2102 #endif 2103 }; 2104 2105 static const struct net_device_ops efx_ef10_netdev_ops = { 2106 .ndo_open = efx_net_open, 2107 .ndo_stop = efx_net_stop, 2108 .ndo_get_stats64 = efx_net_stats, 2109 .ndo_tx_timeout = efx_watchdog, 2110 .ndo_start_xmit = efx_hard_start_xmit, 2111 .ndo_validate_addr = eth_validate_addr, 2112 .ndo_do_ioctl = efx_ioctl, 2113 .ndo_change_mtu = efx_change_mtu, 2114 .ndo_set_mac_address = efx_set_mac_address, 2115 .ndo_set_rx_mode = efx_set_rx_mode, 2116 .ndo_set_features = efx_set_features, 2117 #ifdef CONFIG_NET_POLL_CONTROLLER 2118 .ndo_poll_controller = efx_netpoll, 2119 #endif 2120 #ifdef CONFIG_RFS_ACCEL 2121 .ndo_rx_flow_steer = efx_filter_rfs, 2122 #endif 2123 }; 2124 2125 static void efx_update_name(struct efx_nic *efx) 2126 { 2127 strcpy(efx->name, efx->net_dev->name); 2128 efx_mtd_rename(efx); 2129 efx_set_channel_names(efx); 2130 } 2131 2132 static int efx_netdev_event(struct notifier_block *this, 2133 unsigned long event, void *ptr) 2134 { 2135 struct net_device *net_dev = netdev_notifier_info_to_dev(ptr); 2136 2137 if ((net_dev->netdev_ops == &efx_farch_netdev_ops || 2138 net_dev->netdev_ops == &efx_ef10_netdev_ops) && 2139 event == NETDEV_CHANGENAME) 2140 efx_update_name(netdev_priv(net_dev)); 2141 2142 return NOTIFY_DONE; 2143 } 2144 2145 static struct notifier_block efx_netdev_notifier = { 2146 .notifier_call = efx_netdev_event, 2147 }; 2148 2149 static ssize_t 2150 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) 2151 { 2152 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2153 return sprintf(buf, "%d\n", efx->phy_type); 2154 } 2155 static DEVICE_ATTR(phy_type, 0444, show_phy_type, NULL); 2156 2157 static int efx_register_netdev(struct efx_nic *efx) 2158 { 2159 struct net_device *net_dev = efx->net_dev; 2160 struct efx_channel *channel; 2161 int rc; 2162 2163 net_dev->watchdog_timeo = 5 * HZ; 2164 net_dev->irq = efx->pci_dev->irq; 2165 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0) { 2166 net_dev->netdev_ops = &efx_ef10_netdev_ops; 2167 net_dev->priv_flags |= IFF_UNICAST_FLT; 2168 } else { 2169 net_dev->netdev_ops = &efx_farch_netdev_ops; 2170 } 2171 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); 2172 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; 2173 2174 rtnl_lock(); 2175 2176 /* Enable resets to be scheduled and check whether any were 2177 * already requested. If so, the NIC is probably hosed so we 2178 * abort. 2179 */ 2180 efx->state = STATE_READY; 2181 smp_mb(); /* ensure we change state before checking reset_pending */ 2182 if (efx->reset_pending) { 2183 netif_err(efx, probe, efx->net_dev, 2184 "aborting probe due to scheduled reset\n"); 2185 rc = -EIO; 2186 goto fail_locked; 2187 } 2188 2189 rc = dev_alloc_name(net_dev, net_dev->name); 2190 if (rc < 0) 2191 goto fail_locked; 2192 efx_update_name(efx); 2193 2194 /* Always start with carrier off; PHY events will detect the link */ 2195 netif_carrier_off(net_dev); 2196 2197 rc = register_netdevice(net_dev); 2198 if (rc) 2199 goto fail_locked; 2200 2201 efx_for_each_channel(channel, efx) { 2202 struct efx_tx_queue *tx_queue; 2203 efx_for_each_channel_tx_queue(tx_queue, channel) 2204 efx_init_tx_queue_core_txq(tx_queue); 2205 } 2206 2207 rtnl_unlock(); 2208 2209 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2210 if (rc) { 2211 netif_err(efx, drv, efx->net_dev, 2212 "failed to init net dev attributes\n"); 2213 goto fail_registered; 2214 } 2215 2216 return 0; 2217 2218 fail_registered: 2219 rtnl_lock(); 2220 unregister_netdevice(net_dev); 2221 fail_locked: 2222 efx->state = STATE_UNINIT; 2223 rtnl_unlock(); 2224 netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); 2225 return rc; 2226 } 2227 2228 static void efx_unregister_netdev(struct efx_nic *efx) 2229 { 2230 if (!efx->net_dev) 2231 return; 2232 2233 BUG_ON(netdev_priv(efx->net_dev) != efx); 2234 2235 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); 2236 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2237 2238 rtnl_lock(); 2239 unregister_netdevice(efx->net_dev); 2240 efx->state = STATE_UNINIT; 2241 rtnl_unlock(); 2242 } 2243 2244 /************************************************************************** 2245 * 2246 * Device reset and suspend 2247 * 2248 **************************************************************************/ 2249 2250 /* Tears down the entire software state and most of the hardware state 2251 * before reset. */ 2252 void efx_reset_down(struct efx_nic *efx, enum reset_type method) 2253 { 2254 EFX_ASSERT_RESET_SERIALISED(efx); 2255 2256 efx_stop_all(efx); 2257 efx_disable_interrupts(efx); 2258 2259 mutex_lock(&efx->mac_lock); 2260 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) 2261 efx->phy_op->fini(efx); 2262 efx->type->fini(efx); 2263 } 2264 2265 /* This function will always ensure that the locks acquired in 2266 * efx_reset_down() are released. A failure return code indicates 2267 * that we were unable to reinitialise the hardware, and the 2268 * driver should be disabled. If ok is false, then the rx and tx 2269 * engines are not restarted, pending a RESET_DISABLE. */ 2270 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) 2271 { 2272 int rc; 2273 2274 EFX_ASSERT_RESET_SERIALISED(efx); 2275 2276 rc = efx->type->init(efx); 2277 if (rc) { 2278 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); 2279 goto fail; 2280 } 2281 2282 if (!ok) 2283 goto fail; 2284 2285 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { 2286 rc = efx->phy_op->init(efx); 2287 if (rc) 2288 goto fail; 2289 if (efx->phy_op->reconfigure(efx)) 2290 netif_err(efx, drv, efx->net_dev, 2291 "could not restore PHY settings\n"); 2292 } 2293 2294 rc = efx_enable_interrupts(efx); 2295 if (rc) 2296 goto fail; 2297 efx_restore_filters(efx); 2298 efx_sriov_reset(efx); 2299 2300 mutex_unlock(&efx->mac_lock); 2301 2302 efx_start_all(efx); 2303 2304 return 0; 2305 2306 fail: 2307 efx->port_initialized = false; 2308 2309 mutex_unlock(&efx->mac_lock); 2310 2311 return rc; 2312 } 2313 2314 /* Reset the NIC using the specified method. Note that the reset may 2315 * fail, in which case the card will be left in an unusable state. 2316 * 2317 * Caller must hold the rtnl_lock. 2318 */ 2319 int efx_reset(struct efx_nic *efx, enum reset_type method) 2320 { 2321 int rc, rc2; 2322 bool disabled; 2323 2324 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", 2325 RESET_TYPE(method)); 2326 2327 efx_device_detach_sync(efx); 2328 efx_reset_down(efx, method); 2329 2330 rc = efx->type->reset(efx, method); 2331 if (rc) { 2332 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); 2333 goto out; 2334 } 2335 2336 /* Clear flags for the scopes we covered. We assume the NIC and 2337 * driver are now quiescent so that there is no race here. 2338 */ 2339 efx->reset_pending &= -(1 << (method + 1)); 2340 2341 /* Reinitialise bus-mastering, which may have been turned off before 2342 * the reset was scheduled. This is still appropriate, even in the 2343 * RESET_TYPE_DISABLE since this driver generally assumes the hardware 2344 * can respond to requests. */ 2345 pci_set_master(efx->pci_dev); 2346 2347 out: 2348 /* Leave device stopped if necessary */ 2349 disabled = rc || 2350 method == RESET_TYPE_DISABLE || 2351 method == RESET_TYPE_RECOVER_OR_DISABLE; 2352 rc2 = efx_reset_up(efx, method, !disabled); 2353 if (rc2) { 2354 disabled = true; 2355 if (!rc) 2356 rc = rc2; 2357 } 2358 2359 if (disabled) { 2360 dev_close(efx->net_dev); 2361 netif_err(efx, drv, efx->net_dev, "has been disabled\n"); 2362 efx->state = STATE_DISABLED; 2363 } else { 2364 netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); 2365 netif_device_attach(efx->net_dev); 2366 } 2367 return rc; 2368 } 2369 2370 /* Try recovery mechanisms. 2371 * For now only EEH is supported. 2372 * Returns 0 if the recovery mechanisms are unsuccessful. 2373 * Returns a non-zero value otherwise. 2374 */ 2375 int efx_try_recovery(struct efx_nic *efx) 2376 { 2377 #ifdef CONFIG_EEH 2378 /* A PCI error can occur and not be seen by EEH because nothing 2379 * happens on the PCI bus. In this case the driver may fail and 2380 * schedule a 'recover or reset', leading to this recovery handler. 2381 * Manually call the eeh failure check function. 2382 */ 2383 struct eeh_dev *eehdev = 2384 of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev)); 2385 2386 if (eeh_dev_check_failure(eehdev)) { 2387 /* The EEH mechanisms will handle the error and reset the 2388 * device if necessary. 2389 */ 2390 return 1; 2391 } 2392 #endif 2393 return 0; 2394 } 2395 2396 /* The worker thread exists so that code that cannot sleep can 2397 * schedule a reset for later. 2398 */ 2399 static void efx_reset_work(struct work_struct *data) 2400 { 2401 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); 2402 unsigned long pending; 2403 enum reset_type method; 2404 2405 pending = ACCESS_ONCE(efx->reset_pending); 2406 method = fls(pending) - 1; 2407 2408 if ((method == RESET_TYPE_RECOVER_OR_DISABLE || 2409 method == RESET_TYPE_RECOVER_OR_ALL) && 2410 efx_try_recovery(efx)) 2411 return; 2412 2413 if (!pending) 2414 return; 2415 2416 rtnl_lock(); 2417 2418 /* We checked the state in efx_schedule_reset() but it may 2419 * have changed by now. Now that we have the RTNL lock, 2420 * it cannot change again. 2421 */ 2422 if (efx->state == STATE_READY) 2423 (void)efx_reset(efx, method); 2424 2425 rtnl_unlock(); 2426 } 2427 2428 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) 2429 { 2430 enum reset_type method; 2431 2432 if (efx->state == STATE_RECOVERY) { 2433 netif_dbg(efx, drv, efx->net_dev, 2434 "recovering: skip scheduling %s reset\n", 2435 RESET_TYPE(type)); 2436 return; 2437 } 2438 2439 switch (type) { 2440 case RESET_TYPE_INVISIBLE: 2441 case RESET_TYPE_ALL: 2442 case RESET_TYPE_RECOVER_OR_ALL: 2443 case RESET_TYPE_WORLD: 2444 case RESET_TYPE_DISABLE: 2445 case RESET_TYPE_RECOVER_OR_DISABLE: 2446 method = type; 2447 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", 2448 RESET_TYPE(method)); 2449 break; 2450 default: 2451 method = efx->type->map_reset_reason(type); 2452 netif_dbg(efx, drv, efx->net_dev, 2453 "scheduling %s reset for %s\n", 2454 RESET_TYPE(method), RESET_TYPE(type)); 2455 break; 2456 } 2457 2458 set_bit(method, &efx->reset_pending); 2459 smp_mb(); /* ensure we change reset_pending before checking state */ 2460 2461 /* If we're not READY then just leave the flags set as the cue 2462 * to abort probing or reschedule the reset later. 2463 */ 2464 if (ACCESS_ONCE(efx->state) != STATE_READY) 2465 return; 2466 2467 /* efx_process_channel() will no longer read events once a 2468 * reset is scheduled. So switch back to poll'd MCDI completions. */ 2469 efx_mcdi_mode_poll(efx); 2470 2471 queue_work(reset_workqueue, &efx->reset_work); 2472 } 2473 2474 /************************************************************************** 2475 * 2476 * List of NICs we support 2477 * 2478 **************************************************************************/ 2479 2480 /* PCI device ID table */ 2481 static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { 2482 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2483 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), 2484 .driver_data = (unsigned long) &falcon_a1_nic_type}, 2485 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2486 PCI_DEVICE_ID_SOLARFLARE_SFC4000B), 2487 .driver_data = (unsigned long) &falcon_b0_nic_type}, 2488 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ 2489 .driver_data = (unsigned long) &siena_a0_nic_type}, 2490 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ 2491 .driver_data = (unsigned long) &siena_a0_nic_type}, 2492 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0903), /* SFC9120 PF */ 2493 .driver_data = (unsigned long) &efx_hunt_a0_nic_type}, 2494 {0} /* end of list */ 2495 }; 2496 2497 /************************************************************************** 2498 * 2499 * Dummy PHY/MAC operations 2500 * 2501 * Can be used for some unimplemented operations 2502 * Needed so all function pointers are valid and do not have to be tested 2503 * before use 2504 * 2505 **************************************************************************/ 2506 int efx_port_dummy_op_int(struct efx_nic *efx) 2507 { 2508 return 0; 2509 } 2510 void efx_port_dummy_op_void(struct efx_nic *efx) {} 2511 2512 static bool efx_port_dummy_op_poll(struct efx_nic *efx) 2513 { 2514 return false; 2515 } 2516 2517 static const struct efx_phy_operations efx_dummy_phy_operations = { 2518 .init = efx_port_dummy_op_int, 2519 .reconfigure = efx_port_dummy_op_int, 2520 .poll = efx_port_dummy_op_poll, 2521 .fini = efx_port_dummy_op_void, 2522 }; 2523 2524 /************************************************************************** 2525 * 2526 * Data housekeeping 2527 * 2528 **************************************************************************/ 2529 2530 /* This zeroes out and then fills in the invariants in a struct 2531 * efx_nic (including all sub-structures). 2532 */ 2533 static int efx_init_struct(struct efx_nic *efx, 2534 struct pci_dev *pci_dev, struct net_device *net_dev) 2535 { 2536 int i; 2537 2538 /* Initialise common structures */ 2539 spin_lock_init(&efx->biu_lock); 2540 #ifdef CONFIG_SFC_MTD 2541 INIT_LIST_HEAD(&efx->mtd_list); 2542 #endif 2543 INIT_WORK(&efx->reset_work, efx_reset_work); 2544 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); 2545 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); 2546 efx->pci_dev = pci_dev; 2547 efx->msg_enable = debug; 2548 efx->state = STATE_UNINIT; 2549 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); 2550 2551 efx->net_dev = net_dev; 2552 efx->rx_prefix_size = efx->type->rx_prefix_size; 2553 efx->rx_packet_hash_offset = 2554 efx->type->rx_hash_offset - efx->type->rx_prefix_size; 2555 spin_lock_init(&efx->stats_lock); 2556 mutex_init(&efx->mac_lock); 2557 efx->phy_op = &efx_dummy_phy_operations; 2558 efx->mdio.dev = net_dev; 2559 INIT_WORK(&efx->mac_work, efx_mac_work); 2560 init_waitqueue_head(&efx->flush_wq); 2561 2562 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 2563 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 2564 if (!efx->channel[i]) 2565 goto fail; 2566 efx->msi_context[i].efx = efx; 2567 efx->msi_context[i].index = i; 2568 } 2569 2570 /* Higher numbered interrupt modes are less capable! */ 2571 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 2572 interrupt_mode); 2573 2574 /* Would be good to use the net_dev name, but we're too early */ 2575 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", 2576 pci_name(pci_dev)); 2577 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); 2578 if (!efx->workqueue) 2579 goto fail; 2580 2581 return 0; 2582 2583 fail: 2584 efx_fini_struct(efx); 2585 return -ENOMEM; 2586 } 2587 2588 static void efx_fini_struct(struct efx_nic *efx) 2589 { 2590 int i; 2591 2592 for (i = 0; i < EFX_MAX_CHANNELS; i++) 2593 kfree(efx->channel[i]); 2594 2595 if (efx->workqueue) { 2596 destroy_workqueue(efx->workqueue); 2597 efx->workqueue = NULL; 2598 } 2599 } 2600 2601 /************************************************************************** 2602 * 2603 * PCI interface 2604 * 2605 **************************************************************************/ 2606 2607 /* Main body of final NIC shutdown code 2608 * This is called only at module unload (or hotplug removal). 2609 */ 2610 static void efx_pci_remove_main(struct efx_nic *efx) 2611 { 2612 /* Flush reset_work. It can no longer be scheduled since we 2613 * are not READY. 2614 */ 2615 BUG_ON(efx->state == STATE_READY); 2616 cancel_work_sync(&efx->reset_work); 2617 2618 efx_disable_interrupts(efx); 2619 efx_nic_fini_interrupt(efx); 2620 efx_fini_port(efx); 2621 efx->type->fini(efx); 2622 efx_fini_napi(efx); 2623 efx_remove_all(efx); 2624 } 2625 2626 /* Final NIC shutdown 2627 * This is called only at module unload (or hotplug removal). 2628 */ 2629 static void efx_pci_remove(struct pci_dev *pci_dev) 2630 { 2631 struct efx_nic *efx; 2632 2633 efx = pci_get_drvdata(pci_dev); 2634 if (!efx) 2635 return; 2636 2637 /* Mark the NIC as fini, then stop the interface */ 2638 rtnl_lock(); 2639 dev_close(efx->net_dev); 2640 efx_disable_interrupts(efx); 2641 rtnl_unlock(); 2642 2643 efx_sriov_fini(efx); 2644 efx_unregister_netdev(efx); 2645 2646 efx_mtd_remove(efx); 2647 2648 efx_pci_remove_main(efx); 2649 2650 efx_fini_io(efx); 2651 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); 2652 2653 efx_fini_struct(efx); 2654 pci_set_drvdata(pci_dev, NULL); 2655 free_netdev(efx->net_dev); 2656 2657 pci_disable_pcie_error_reporting(pci_dev); 2658 }; 2659 2660 /* NIC VPD information 2661 * Called during probe to display the part number of the 2662 * installed NIC. VPD is potentially very large but this should 2663 * always appear within the first 512 bytes. 2664 */ 2665 #define SFC_VPD_LEN 512 2666 static void efx_print_product_vpd(struct efx_nic *efx) 2667 { 2668 struct pci_dev *dev = efx->pci_dev; 2669 char vpd_data[SFC_VPD_LEN]; 2670 ssize_t vpd_size; 2671 int i, j; 2672 2673 /* Get the vpd data from the device */ 2674 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); 2675 if (vpd_size <= 0) { 2676 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); 2677 return; 2678 } 2679 2680 /* Get the Read only section */ 2681 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 2682 if (i < 0) { 2683 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); 2684 return; 2685 } 2686 2687 j = pci_vpd_lrdt_size(&vpd_data[i]); 2688 i += PCI_VPD_LRDT_TAG_SIZE; 2689 if (i + j > vpd_size) 2690 j = vpd_size - i; 2691 2692 /* Get the Part number */ 2693 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); 2694 if (i < 0) { 2695 netif_err(efx, drv, efx->net_dev, "Part number not found\n"); 2696 return; 2697 } 2698 2699 j = pci_vpd_info_field_size(&vpd_data[i]); 2700 i += PCI_VPD_INFO_FLD_HDR_SIZE; 2701 if (i + j > vpd_size) { 2702 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); 2703 return; 2704 } 2705 2706 netif_info(efx, drv, efx->net_dev, 2707 "Part Number : %.*s\n", j, &vpd_data[i]); 2708 } 2709 2710 2711 /* Main body of NIC initialisation 2712 * This is called at module load (or hotplug insertion, theoretically). 2713 */ 2714 static int efx_pci_probe_main(struct efx_nic *efx) 2715 { 2716 int rc; 2717 2718 /* Do start-of-day initialisation */ 2719 rc = efx_probe_all(efx); 2720 if (rc) 2721 goto fail1; 2722 2723 efx_init_napi(efx); 2724 2725 rc = efx->type->init(efx); 2726 if (rc) { 2727 netif_err(efx, probe, efx->net_dev, 2728 "failed to initialise NIC\n"); 2729 goto fail3; 2730 } 2731 2732 rc = efx_init_port(efx); 2733 if (rc) { 2734 netif_err(efx, probe, efx->net_dev, 2735 "failed to initialise port\n"); 2736 goto fail4; 2737 } 2738 2739 rc = efx_nic_init_interrupt(efx); 2740 if (rc) 2741 goto fail5; 2742 rc = efx_enable_interrupts(efx); 2743 if (rc) 2744 goto fail6; 2745 2746 return 0; 2747 2748 fail6: 2749 efx_nic_fini_interrupt(efx); 2750 fail5: 2751 efx_fini_port(efx); 2752 fail4: 2753 efx->type->fini(efx); 2754 fail3: 2755 efx_fini_napi(efx); 2756 efx_remove_all(efx); 2757 fail1: 2758 return rc; 2759 } 2760 2761 /* NIC initialisation 2762 * 2763 * This is called at module load (or hotplug insertion, 2764 * theoretically). It sets up PCI mappings, resets the NIC, 2765 * sets up and registers the network devices with the kernel and hooks 2766 * the interrupt service routine. It does not prepare the device for 2767 * transmission; this is left to the first time one of the network 2768 * interfaces is brought up (i.e. efx_net_open). 2769 */ 2770 static int efx_pci_probe(struct pci_dev *pci_dev, 2771 const struct pci_device_id *entry) 2772 { 2773 struct net_device *net_dev; 2774 struct efx_nic *efx; 2775 int rc; 2776 2777 /* Allocate and initialise a struct net_device and struct efx_nic */ 2778 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, 2779 EFX_MAX_RX_QUEUES); 2780 if (!net_dev) 2781 return -ENOMEM; 2782 efx = netdev_priv(net_dev); 2783 efx->type = (const struct efx_nic_type *) entry->driver_data; 2784 net_dev->features |= (efx->type->offload_features | NETIF_F_SG | 2785 NETIF_F_HIGHDMA | NETIF_F_TSO | 2786 NETIF_F_RXCSUM); 2787 if (efx->type->offload_features & NETIF_F_V6_CSUM) 2788 net_dev->features |= NETIF_F_TSO6; 2789 /* Mask for features that also apply to VLAN devices */ 2790 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | 2791 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | 2792 NETIF_F_RXCSUM); 2793 /* All offloads can be toggled */ 2794 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; 2795 pci_set_drvdata(pci_dev, efx); 2796 SET_NETDEV_DEV(net_dev, &pci_dev->dev); 2797 rc = efx_init_struct(efx, pci_dev, net_dev); 2798 if (rc) 2799 goto fail1; 2800 2801 netif_info(efx, probe, efx->net_dev, 2802 "Solarflare NIC detected\n"); 2803 2804 efx_print_product_vpd(efx); 2805 2806 /* Set up basic I/O (BAR mappings etc) */ 2807 rc = efx_init_io(efx); 2808 if (rc) 2809 goto fail2; 2810 2811 rc = efx_pci_probe_main(efx); 2812 if (rc) 2813 goto fail3; 2814 2815 rc = efx_register_netdev(efx); 2816 if (rc) 2817 goto fail4; 2818 2819 rc = efx_sriov_init(efx); 2820 if (rc) 2821 netif_err(efx, probe, efx->net_dev, 2822 "SR-IOV can't be enabled rc %d\n", rc); 2823 2824 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); 2825 2826 /* Try to create MTDs, but allow this to fail */ 2827 rtnl_lock(); 2828 rc = efx_mtd_probe(efx); 2829 rtnl_unlock(); 2830 if (rc) 2831 netif_warn(efx, probe, efx->net_dev, 2832 "failed to create MTDs (%d)\n", rc); 2833 2834 rc = pci_enable_pcie_error_reporting(pci_dev); 2835 if (rc && rc != -EINVAL) 2836 netif_warn(efx, probe, efx->net_dev, 2837 "pci_enable_pcie_error_reporting failed (%d)\n", rc); 2838 2839 return 0; 2840 2841 fail4: 2842 efx_pci_remove_main(efx); 2843 fail3: 2844 efx_fini_io(efx); 2845 fail2: 2846 efx_fini_struct(efx); 2847 fail1: 2848 pci_set_drvdata(pci_dev, NULL); 2849 WARN_ON(rc > 0); 2850 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); 2851 free_netdev(net_dev); 2852 return rc; 2853 } 2854 2855 static int efx_pm_freeze(struct device *dev) 2856 { 2857 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2858 2859 rtnl_lock(); 2860 2861 if (efx->state != STATE_DISABLED) { 2862 efx->state = STATE_UNINIT; 2863 2864 efx_device_detach_sync(efx); 2865 2866 efx_stop_all(efx); 2867 efx_disable_interrupts(efx); 2868 } 2869 2870 rtnl_unlock(); 2871 2872 return 0; 2873 } 2874 2875 static int efx_pm_thaw(struct device *dev) 2876 { 2877 int rc; 2878 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2879 2880 rtnl_lock(); 2881 2882 if (efx->state != STATE_DISABLED) { 2883 rc = efx_enable_interrupts(efx); 2884 if (rc) 2885 goto fail; 2886 2887 mutex_lock(&efx->mac_lock); 2888 efx->phy_op->reconfigure(efx); 2889 mutex_unlock(&efx->mac_lock); 2890 2891 efx_start_all(efx); 2892 2893 netif_device_attach(efx->net_dev); 2894 2895 efx->state = STATE_READY; 2896 2897 efx->type->resume_wol(efx); 2898 } 2899 2900 rtnl_unlock(); 2901 2902 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ 2903 queue_work(reset_workqueue, &efx->reset_work); 2904 2905 return 0; 2906 2907 fail: 2908 rtnl_unlock(); 2909 2910 return rc; 2911 } 2912 2913 static int efx_pm_poweroff(struct device *dev) 2914 { 2915 struct pci_dev *pci_dev = to_pci_dev(dev); 2916 struct efx_nic *efx = pci_get_drvdata(pci_dev); 2917 2918 efx->type->fini(efx); 2919 2920 efx->reset_pending = 0; 2921 2922 pci_save_state(pci_dev); 2923 return pci_set_power_state(pci_dev, PCI_D3hot); 2924 } 2925 2926 /* Used for both resume and restore */ 2927 static int efx_pm_resume(struct device *dev) 2928 { 2929 struct pci_dev *pci_dev = to_pci_dev(dev); 2930 struct efx_nic *efx = pci_get_drvdata(pci_dev); 2931 int rc; 2932 2933 rc = pci_set_power_state(pci_dev, PCI_D0); 2934 if (rc) 2935 return rc; 2936 pci_restore_state(pci_dev); 2937 rc = pci_enable_device(pci_dev); 2938 if (rc) 2939 return rc; 2940 pci_set_master(efx->pci_dev); 2941 rc = efx->type->reset(efx, RESET_TYPE_ALL); 2942 if (rc) 2943 return rc; 2944 rc = efx->type->init(efx); 2945 if (rc) 2946 return rc; 2947 rc = efx_pm_thaw(dev); 2948 return rc; 2949 } 2950 2951 static int efx_pm_suspend(struct device *dev) 2952 { 2953 int rc; 2954 2955 efx_pm_freeze(dev); 2956 rc = efx_pm_poweroff(dev); 2957 if (rc) 2958 efx_pm_resume(dev); 2959 return rc; 2960 } 2961 2962 static const struct dev_pm_ops efx_pm_ops = { 2963 .suspend = efx_pm_suspend, 2964 .resume = efx_pm_resume, 2965 .freeze = efx_pm_freeze, 2966 .thaw = efx_pm_thaw, 2967 .poweroff = efx_pm_poweroff, 2968 .restore = efx_pm_resume, 2969 }; 2970 2971 /* A PCI error affecting this device was detected. 2972 * At this point MMIO and DMA may be disabled. 2973 * Stop the software path and request a slot reset. 2974 */ 2975 static pci_ers_result_t efx_io_error_detected(struct pci_dev *pdev, 2976 enum pci_channel_state state) 2977 { 2978 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 2979 struct efx_nic *efx = pci_get_drvdata(pdev); 2980 2981 if (state == pci_channel_io_perm_failure) 2982 return PCI_ERS_RESULT_DISCONNECT; 2983 2984 rtnl_lock(); 2985 2986 if (efx->state != STATE_DISABLED) { 2987 efx->state = STATE_RECOVERY; 2988 efx->reset_pending = 0; 2989 2990 efx_device_detach_sync(efx); 2991 2992 efx_stop_all(efx); 2993 efx_disable_interrupts(efx); 2994 2995 status = PCI_ERS_RESULT_NEED_RESET; 2996 } else { 2997 /* If the interface is disabled we don't want to do anything 2998 * with it. 2999 */ 3000 status = PCI_ERS_RESULT_RECOVERED; 3001 } 3002 3003 rtnl_unlock(); 3004 3005 pci_disable_device(pdev); 3006 3007 return status; 3008 } 3009 3010 /* Fake a successfull reset, which will be performed later in efx_io_resume. */ 3011 static pci_ers_result_t efx_io_slot_reset(struct pci_dev *pdev) 3012 { 3013 struct efx_nic *efx = pci_get_drvdata(pdev); 3014 pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; 3015 int rc; 3016 3017 if (pci_enable_device(pdev)) { 3018 netif_err(efx, hw, efx->net_dev, 3019 "Cannot re-enable PCI device after reset.\n"); 3020 status = PCI_ERS_RESULT_DISCONNECT; 3021 } 3022 3023 rc = pci_cleanup_aer_uncorrect_error_status(pdev); 3024 if (rc) { 3025 netif_err(efx, hw, efx->net_dev, 3026 "pci_cleanup_aer_uncorrect_error_status failed (%d)\n", rc); 3027 /* Non-fatal error. Continue. */ 3028 } 3029 3030 return status; 3031 } 3032 3033 /* Perform the actual reset and resume I/O operations. */ 3034 static void efx_io_resume(struct pci_dev *pdev) 3035 { 3036 struct efx_nic *efx = pci_get_drvdata(pdev); 3037 int rc; 3038 3039 rtnl_lock(); 3040 3041 if (efx->state == STATE_DISABLED) 3042 goto out; 3043 3044 rc = efx_reset(efx, RESET_TYPE_ALL); 3045 if (rc) { 3046 netif_err(efx, hw, efx->net_dev, 3047 "efx_reset failed after PCI error (%d)\n", rc); 3048 } else { 3049 efx->state = STATE_READY; 3050 netif_dbg(efx, hw, efx->net_dev, 3051 "Done resetting and resuming IO after PCI error.\n"); 3052 } 3053 3054 out: 3055 rtnl_unlock(); 3056 } 3057 3058 /* For simplicity and reliability, we always require a slot reset and try to 3059 * reset the hardware when a pci error affecting the device is detected. 3060 * We leave both the link_reset and mmio_enabled callback unimplemented: 3061 * with our request for slot reset the mmio_enabled callback will never be 3062 * called, and the link_reset callback is not used by AER or EEH mechanisms. 3063 */ 3064 static struct pci_error_handlers efx_err_handlers = { 3065 .error_detected = efx_io_error_detected, 3066 .slot_reset = efx_io_slot_reset, 3067 .resume = efx_io_resume, 3068 }; 3069 3070 static struct pci_driver efx_pci_driver = { 3071 .name = KBUILD_MODNAME, 3072 .id_table = efx_pci_table, 3073 .probe = efx_pci_probe, 3074 .remove = efx_pci_remove, 3075 .driver.pm = &efx_pm_ops, 3076 .err_handler = &efx_err_handlers, 3077 }; 3078 3079 /************************************************************************** 3080 * 3081 * Kernel module interface 3082 * 3083 *************************************************************************/ 3084 3085 module_param(interrupt_mode, uint, 0444); 3086 MODULE_PARM_DESC(interrupt_mode, 3087 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 3088 3089 static int __init efx_init_module(void) 3090 { 3091 int rc; 3092 3093 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); 3094 3095 rc = register_netdevice_notifier(&efx_netdev_notifier); 3096 if (rc) 3097 goto err_notifier; 3098 3099 rc = efx_init_sriov(); 3100 if (rc) 3101 goto err_sriov; 3102 3103 reset_workqueue = create_singlethread_workqueue("sfc_reset"); 3104 if (!reset_workqueue) { 3105 rc = -ENOMEM; 3106 goto err_reset; 3107 } 3108 3109 rc = pci_register_driver(&efx_pci_driver); 3110 if (rc < 0) 3111 goto err_pci; 3112 3113 return 0; 3114 3115 err_pci: 3116 destroy_workqueue(reset_workqueue); 3117 err_reset: 3118 efx_fini_sriov(); 3119 err_sriov: 3120 unregister_netdevice_notifier(&efx_netdev_notifier); 3121 err_notifier: 3122 return rc; 3123 } 3124 3125 static void __exit efx_exit_module(void) 3126 { 3127 printk(KERN_INFO "Solarflare NET driver unloading\n"); 3128 3129 pci_unregister_driver(&efx_pci_driver); 3130 destroy_workqueue(reset_workqueue); 3131 efx_fini_sriov(); 3132 unregister_netdevice_notifier(&efx_netdev_notifier); 3133 3134 } 3135 3136 module_init(efx_init_module); 3137 module_exit(efx_exit_module); 3138 3139 MODULE_AUTHOR("Solarflare Communications and " 3140 "Michael Brown <mbrown@fensystems.co.uk>"); 3141 MODULE_DESCRIPTION("Solarflare Communications network driver"); 3142 MODULE_LICENSE("GPL"); 3143 MODULE_DEVICE_TABLE(pci, efx_pci_table); 3144